PHILIPS 74HC2G86DP

INTEGRATED CIRCUITS
DATA SHEET
74HC2G86; 74HCT2G86
Dual 2-input exclusive-OR gate
Product specification
Supersedes data of 2002 Jul 17
2003 Jul 28
Philips Semiconductors
Product specification
Dual 2-input exclusive-OR gate
74HC2G86; 74HCT2G86
FEATURES
DESCRIPTION
• Wide supply voltage range from 2.0 to 6.0 V
The 74HC2G/HCT2G86 is a high-speed Si-gate CMOS
device.
• Symmetrical output impedance
• High noise immunity
The 74HC2G/HCT2G86 provides dual 2-input
exclusive-OR gate.
• Low power dissipation
• Balanced propagation delays
• Very small 8 pins package
• ESD protection:
HBM EIA/JESD22-A114-A exceeds 2000 V
MM EIA/JESD22-A115-A exceeds 200 V.
QUICK REFERENCE DATA
GND = 0 V; Tamb = 25 °C; tr = tf ≤ 6.0 ns.
TYPICAL
SYMBOL
PARAMETER
CONDITIONS
UNIT
HC2G86
tPHL/tPLH
propagation delay nA to nY
CI
input capacitance
CPD
power dissipation capacitance per gate
CL = 50 pF; VCC = 4.5 V
notes 1 and 2
Notes
1. CPD is used to determine the dynamic power dissipation (PD in µW).
PD = CPD × VCC2 × fi × N + ∑ (CL × VCC2 × fo) where:
fi = input frequency in MHz;
fo = output frequency in MHz;
CL = output load capacitance in pF;
VCC = supply voltage in Volts;
N = total switching outputs;
∑ (CL × VCC2 × fo) = sum of outputs.
2. For 74HC2G86 the condition is VI = GND to VCC.
For 74HCT2G86 the condition is VI = GND to VCC − 1.5 V.
2003 Jul 28
2
HCT2G86
11
11
ns
1.5
1.5
pF
10
9
pF
Philips Semiconductors
Product specification
Dual 2-input exclusive-OR gate
74HC2G86; 74HCT2G86
FUNCTION TABLE
See note 1.
INPUT
OUTPUT
nA
nA
nY
L
L
L
L
H
H
H
L
H
H
H
L
Note
1. H = HIGH voltage level;
L = LOW voltage level.
ORDERING INFORMATION
PACKAGE
TYPE NUMBER
TEMPERATURE
RANGE
PINS
PACKAGE
MATERIAL
CODE
MARKING
−40 to +125 °C
8
TSSOP8
plastic
SOT505-2
H86
74HC2G86DP
74HCT2G86DP
−40 to +125 °C
8
TSSOP8
plastic
SOT505-2
T86
74HC2G86DC
−40 to +125 °C
8
VSSOP8
plastic
SOT765-1
H86
74HCT2G86DC
−40 to +125 °C
8
VSSOP8
plastic
SOT765-1
H86
PINNING
PIN
2003 Jul 28
SYMBOL
DESCRIPTION
1
1A
data input 1A
2
1B
data input 1B
3
2Y
data output 2Y
4
GND
ground (0 V)
5
2A
data input 2A
6
2B
data input 2B
7
1Y
data output 1Y
8
VCC
supply voltage
3
Philips Semiconductors
Product specification
Dual 2-input exclusive-OR gate
74HC2G86; 74HCT2G86
handbook, halfpage
1A 1
8 VCC
1B 2
7
1Y
handbook, halfpage
86
2Y
3
6
2B
GND
4
5
2A
Fig.1 Pin configuration.
1
=1
1Y
7
5
6
2A
2B
2Y
3
Fig.2 Logic symbol.
7
handbook, halfpage
B
2
5
1A
1B
MNA737
MNA736
handbook, halfpage
1
2
Y
=1
3
6
A
MNA040
MNA738
Fig.3 IEC logic symbol.
2003 Jul 28
Fig.4 Logic diagram (one driver).
4
Philips Semiconductors
Product specification
Dual 2-input exclusive-OR gate
74HC2G86; 74HCT2G86
RECOMMENDED OPERATING CONDITIONS
74HC2G86
SYMBOL
PARAMETER
74HCT2G86
CONDITIONS
UNIT
MIN.
TYP.
MAX.
MIN.
TYP.
MAX.
VCC
supply voltage
2.0
5.0
6.0
4.5
5.0
5.5
V
VI
input voltage
0
−
VCC
0
−
VCC
V
VO
output voltage
0
−
VCC
0
−
VCC
V
Tamb
operating ambient
temperature
+25
+125
−40
+25
+125
°C
tr, tf
input rise and fall times
see DC and AC
−40
characteristics per
device
VCC = 2.0 V
−
−
1000
−
−
−
ns
VCC = 4.5 V
−
6.0
500
−
6.0
500
ns
VCC = 6.0 V
−
−
400
−
−
−
ns
LIMITING VALUES
In accordance with the Absolute Maximum Rating System (IEC 60134); voltages are referenced to GND (ground = 0 V).
SYMBOL
PARAMETER
VCC
supply voltage
IIK
input diode current
CONDITIONS
VI < −0.5 V or VI > VCC + 0.5 V; note 1
MIN.
MAX.
UNIT
−0.5
+7.0
V
−
±20
mA
IOK
output diode current
VO < −0.5 V or VO > VCC + 0.5 V; note 1
−
±20
mA
IO
output source or sink current
−0.5 V < VO < VCC + 0.5 V; note 1
−
25
mA
ICC
VCC or GND current
note 1
−
50
mA
Tstg
storage temperature
−65
+150
°C
PD
power dissipation
Tamb = −40 to +125 °C; note 2
−
300
mW
Notes
1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. Above 110 °C the value of PD derates linearly with 8 mW/K.
2003 Jul 28
5
Philips Semiconductors
Product specification
Dual 2-input exclusive-OR gate
74HC2G86; 74HCT2G86
DC CHARACTERISTICS
Type 74HC2G86
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
TEST CONDITIONS
SYMBOL
PARAMETER
MIN.
OTHER
TYP.
MAX.
UNIT
VCC (V)
Tamb = 25 °C
VIH
VIL
VOH
VOL
2.0
1.5
1.2
−
V
4.5
3.15
2.4
−
V
6.0
4.2
3.2
−
V
2.0
−
0.8
0.5
V
4.5
−
2.1
1.35
V
6.0
−
2.8
1.8
V
IO = −20 µA
2.0
1.9
2.0
−
V
IO = −20 µA
4.5
4.4
4.5
−
V
IO = −20 µA
6.0
5.9
6.0
−
V
IO = −4.0 mA
4.5
4.18
4.32
−
V
IO = −5.2 mA
6.0
5.68
5.81
−
V
IO = 20 µA
2.0
−
0
0.1
V
IO = 20 µA
4.5
−
0
0.1
V
IO = 20 µA
6.0
−
0
0.1
V
IO = 4.0 mA
4.5
−
0.15
0.26
V
HIGH-level input voltage
LOW-level input voltage
HIGH-level output voltage
LOW-level output voltage
VI = VIH or VIL
VI = VIH or VIL
IO = 5.2 mA
6.0
−
0.16
0.26
V
ILI
input leakage current
VI = VCC or GND
6.0
−
−
±0.1
µA
ICC
quiescent supply current
VI = VCC or GND;
IO = 0
6.0
−
−
1.0
µA
2003 Jul 28
6
Philips Semiconductors
Product specification
Dual 2-input exclusive-OR gate
74HC2G86; 74HCT2G86
TEST CONDITIONS
SYMBOL
PARAMETER
MIN.
OTHER
TYP.
MAX.
UNIT
VCC (V)
Tamb = −40 to +85 °C
VIH
VIL
VOH
VOL
HIGH-level input voltage
LOW-level output voltage
1.5
−
−
V
4.5
3.15
−
−
V
6.0
4.2
−
−
V
2.0
−
−
0.5
V
4.5
−
−
1.35
V
6.0
−
−
1.8
V
IO = −20 µA
2.0
1.9
−
−
V
IO = −20 µA
4.5
4.4
−
−
V
IO = −20 µA
6.0
5.9
−
−
V
IO = −4.0 mA
4.5
4.13
−
−
V
IO = −5.2 mA
6.0
5.63
−
−
V
IO = 20 µA
2.0
−
−
0.1
V
IO = 20 µA
4.5
−
−
0.1
V
IO = 20 µA
6.0
−
−
0.1
V
IO = 4.0 mA
4.5
−
−
0.33
V
IO = 5.2 mA
6.0
−
−
0.33
V
LOW-level input voltage
HIGH-level output voltage
2.0
VI = VIH or VIL
VI = VIH or VIL
ILI
input leakage current
VI = VCC or GND
6.0
−
−
±1.0
µA
ICC
quiescent supply current
VI = VCC or GND;
IO = 0
6.0
−
−
10
µA
2003 Jul 28
7
Philips Semiconductors
Product specification
Dual 2-input exclusive-OR gate
74HC2G86; 74HCT2G86
TEST CONDITIONS
SYMBOL
PARAMETER
MIN.
OTHER
TYP.
MAX.
UNIT
VCC (V)
Tamb = −40 to +125 °C
VIH
VIL
VOH
VOL
HIGH-level input voltage
LOW-level output voltage
1.5
−
−
V
4.5
3.15
−
−
V
6.0
4.2
−
−
V
2.0
−
−
0.5
V
4.5
−
−
1.35
V
6.0
−
−
1.8
V
IO = −20 µA
2.0
1.9
−
−
V
IO = −20 µA
4.5
4.4
−
−
V
IO = −20 µA
6.0
5.9
−
−
V
IO = −4.0 mA
4.5
3.7
−
−
V
IO = −5.2 mA
6.0
5.2
−
−
V
IO = 20 µA
2.0
−
−
0.1
V
IO = 20 µA
4.5
−
−
0.1
V
IO = 20 µA
6.0
−
−
0.1
V
IO = 4.0 mA
4.5
−
−
0.4
V
IO = 5.2 mA
6.0
−
−
0.4
V
LOW-level input voltage
HIGH-level output voltage
2.0
VI = VIH or VIL
VI = VIH or VIL
ILI
input leakage current
VI = VCC or GND
6.0
−
−
±1.0
µA
ICC
quiescent supply current
VI = VCC or GND;
IO = 0
6.0
−
−
20
µA
2003 Jul 28
8
Philips Semiconductors
Product specification
Dual 2-input exclusive-OR gate
74HC2G86; 74HCT2G86
Type 74HCT2G86
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
TEST CONDITIONS
SYMBOL
PARAMETER
MIN.
TYP.
MAX.
UNIT
VCC (V)
OTHER
Tamb = 25 °C
VIH
HIGH-level input voltage
4.5 to 5.5
2.0
1.6
−
V
VIL
LOW-level input voltage
4.5 to 5.5
−
1.2
0.8
V
VOH
HIGH-level output voltage
IO = −20 µA
4.5
4.4
4.5
−
V
IO = −4.0 mA
4.5
4.18
4.32
−
V
VOL
LOW-level output voltage
VI = VIH or VIL
VI = VIH or VIL
IO = 20 µA
4.5
−
0
0.1
V
IO = 4.0 mA
4.5
−
0.15
0.26
V
ILI
input leakage current
VI = VCC or GND
5.5
−
−
±0.1
µA
ICC
quiescent supply current
VI = VCC or GND;
IO = 0
5.5
−
−
1.0
µA
∆ICC
additional supply current
per input
VI = VCC − 2.1 V;
IO = 0
4.5 to 5.5
−
−
300
µA
Tamb = −40 to +85 °C
VIH
HIGH-level input voltage
4.5 to 5.5
2.0
−
−
V
VIL
LOW-level input voltage
4.5 to 5.5
−
−
0.8
V
VOH
HIGH-level output voltage
IO = −20 µA
4.5
4.4
−
−
V
IO = −4.0 mA
4.5
4.13
−
−
V
4.5
−
−
0.1
V
VOL
LOW-level output voltage
VI = VIH or VIL
VI = VIH or VIL
IO = 20 µA
IO = 4.0 mA
4.5
−
−
0.33
V
ILI
input leakage current
VI = VCC or GND
5.5
−
−
±1.0
µA
ICC
quiescent supply current
VI = VCC or GND;
IO = 0
5.5
−
−
10
µA
∆ICC
additional supply current
per input
VI = VCC − 2.1 V;
IO = 0
4.5 to 5.5
−
−
375
µA
2003 Jul 28
9
Philips Semiconductors
Product specification
Dual 2-input exclusive-OR gate
74HC2G86; 74HCT2G86
TEST CONDITIONS
SYMBOL
PARAMETER
MIN.
OTHER
TYP.
MAX.
UNIT
VCC (V)
Tamb = −40 to +125 °C
VIH
HIGH-level input voltage
4.5 to 5.5
2.0
−
−
V
VIL
LOW-level input voltage
4.5 to 5.5
−
−
0.8
V
VOH
HIGH-level output voltage
IO = −20 µA
4.5
4.4
−
−
V
IO = −4.0 mA
4.5
3.7
−
−
V
IO = 20 µA
4.5
−
−
0.1
V
IO = 4.0 mA
4.5
−
−
0.4
V
VOL
LOW-level output voltage
VI = VIH or VIL
VI = VIH or VIL
ILI
input leakage current
VI = VCC or GND
5.5
−
−
±1.0
µA
ICC
quiescent supply current
VI = VCC or GND;
IO = 0
5.5
−
−
20
µA
∆ICC
additional supply current
per input
VI = VCC − 2.1 V;
IO = 0
4.5 to 5.5
−
−
410
µA
2003 Jul 28
10
Philips Semiconductors
Product specification
Dual 2-input exclusive-OR gate
74HC2G86; 74HCT2G86
AC CHARACTERISTICS
Type 74HC2G86
GND = 0 V; tr = tf ≤ 6.0 ns; CL = 50 pF.
TEST CONDITIONS
SYMBOL
PARAMETER
MIN.
WAVEFORMS
TYP.
MAX.
UNIT
VCC (V)
Tamb = 25 °C
tPHL/tPLH
tTHL/tTLH
propagation delay nA, nB to nY
output transition time
see Figs 5 and 6
see Figs 5 and 6
2.0
−
34
120
ns
4.5
−
11
20
ns
6.0
−
9
17
ns
2.0
−
18
75
ns
4.5
−
6
15
ns
6.0
−
5
13
ns
2.0
−
−
150
ns
Tamb = −40 to +85 °C
tPHL/tPLH
tTHL/tTLH
propagation delay nA, nB to nY
output transition time
see Figs 5 and 6
see Figs 5 and 6
4.5
−
−
25
ns
6.0
−
−
21
ns
2.0
−
−
95
ns
4.5
−
−
19
ns
6.0
−
−
16
ns
2.0
−
−
180
ns
Tamb = −40 to +125 °C
tPHL/tPLH
tTHL/tTLH
2003 Jul 28
propagation delay nA, nB to nY
output transition time
see Figs 5 and 6
see Figs 5 and 6
11
4.5
−
−
36
ns
6.0
−
−
30
ns
2.0
−
−
110
ns
4.5
−
−
22
ns
6.0
−
−
20
ns
Philips Semiconductors
Product specification
Dual 2-input exclusive-OR gate
74HC2G86; 74HCT2G86
Type 74HCT2G86
GND = 0 V; tr = tf ≤ 6.0 ns; CL = 50 pF.
TEST CONDITIONS
SYMBOL
PARAMETER
MIN.
TYP.
MAX.
UNIT
VCC (V)
WAVEFORMS
Tamb = 25 °C
tPHL/tPLH
propagation delay nA, nB to nY
see Figs 5 and 6
4.5
−
11
19
ns
tTHL/tTLH
output transition time
see Figs 5 and 6
4.5
−
6
15
ns
Tamb = −40 to +85 °C
tPHL/tPLH
propagation delay nA, nB to nY
see Figs 5 and 6
4.5
−
−
23
ns
tTHL/tTLH
output transition time
see Figs 5 and 6
4.5
−
−
19
ns
Tamb = −40 to +125 °C
tPHL/tPLH
propagation delay nA, nB to nY
see Figs 5 and 6
4.5
−
−
48
ns
tTHL/tTLH
output transition time
see Figs 5 and 6
4.5
−
−
22
ns
AC WAVEFORMS
VI
handbook, halfpage
nA, nB input
VM
VM
GND
t PHL
t PLH
VOH
nY output
90%
VM
VM
10%
VOL
t THL
t TLH
MNA726
For HC2G: VM = 50%; VI = GND to VCC.
For HCT2G: VM = 1.3 V; VI = GND to 3.0 V.
Fig.5 The input (nA, nB) to output (nY) propagation delays.
2003 Jul 28
12
Philips Semiconductors
Product specification
Dual 2-input exclusive-OR gate
74HC2G86; 74HCT2G86
S1
handbook, full pagewidth
VCC
PULSE
GENERATOR
RL =
VI
VCC
open
GND
1 kΩ
VO
D.U.T.
CL =
50 pF
RT
MNA742
TEST
S1
tPLH/tPHL
open
tPLZ/tPZL
VCC
tPHZ/tPZH
GND
Definitions for test circuit:
RL = Load resistor.
CL = Load capacitance including jig and probe capacitance.
RT = Termination resistance should be equal to the output impedance Zo of the pulse generator.
Fig.6 Load circuitry for switching times.
2003 Jul 28
13
Philips Semiconductors
Product specification
Dual 2-input exclusive-OR gate
74HC2G86; 74HCT2G86
PACKAGE OUTLINES
TSSOP8: plastic thin shrink small outline package; 8 leads; body width 3 mm; lead length 0.5 mm
D
E
A
SOT505-2
X
c
HE
y
v M A
Z
5
8
A
A2
(A3)
A1
pin 1 index
θ
Lp
L
1
4
e
detail X
w M
bp
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
UNIT
A
max.
A1
A2
A3
bp
c
D(1)
E(1)
e
HE
L
Lp
v
w
y
Z(1)
θ
mm
1.1
0.15
0.00
0.95
0.75
0.25
0.38
0.22
0.18
0.08
3.1
2.9
3.1
2.9
0.65
4.1
3.9
0.5
0.47
0.33
0.2
0.13
0.1
0.70
0.35
8°
0°
Note
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
OUTLINE
VERSION
SOT505-2
2003 Jul 28
REFERENCES
IEC
JEDEC
JEITA
EUROPEAN
PROJECTION
ISSUE DATE
02-01-16
---
14
Philips Semiconductors
Product specification
Dual 2-input exclusive-OR gate
74HC2G86; 74HCT2G86
VSSOP8: plastic very thin shrink small outline package; 8 leads; body width 2.3 mm
D
E
SOT765-1
A
X
c
y
HE
v M A
Z
5
8
Q
A
A2
A1
pin 1 index
(A3)
θ
Lp
1
4
e
L
detail X
w M
bp
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
UNIT
A
max.
A1
A2
A3
bp
c
D(1)
E(2)
e
HE
L
Lp
Q
v
w
y
Z(1)
θ
mm
1
0.15
0.00
0.85
0.60
0.12
0.27
0.17
0.23
0.08
2.1
1.9
2.4
2.2
0.5
3.2
3.0
0.4
0.40
0.15
0.21
0.19
0.2
0.13
0.1
0.4
0.1
8°
0°
Notes
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
2. Plastic or metal protrusions of 0.25 mm maximum per side are not included.
OUTLINE
VERSION
SOT765-1
2003 Jul 28
REFERENCES
IEC
JEDEC
JEITA
EUROPEAN
PROJECTION
ISSUE DATE
02-06-07
MO-187
15
Philips Semiconductors
Product specification
Dual 2-input exclusive-OR gate
74HC2G86; 74HCT2G86
DATA SHEET STATUS
LEVEL
DATA SHEET
STATUS(1)
PRODUCT
STATUS(2)(3)
Development
DEFINITION
I
Objective data
II
Preliminary data Qualification
This data sheet contains data from the preliminary specification.
Supplementary data will be published at a later date. Philips
Semiconductors reserves the right to change the specification without
notice, in order to improve the design and supply the best possible
product.
III
Product data
This data sheet contains data from the product specification. Philips
Semiconductors reserves the right to make changes at any time in order
to improve the design, manufacturing and supply. Relevant changes will
be communicated via a Customer Product/Process Change Notification
(CPCN).
Production
This data sheet contains data from the objective specification for product
development. Philips Semiconductors reserves the right to change the
specification in any manner without notice.
Notes
1. Please consult the most recently issued data sheet before initiating or completing a design.
2. The product status of the device(s) described in this data sheet may have changed since this data sheet was
published. The latest information is available on the Internet at URL http://www.semiconductors.philips.com.
3. For data sheets describing multiple type numbers, the highest-level product status determines the data sheet status.
DEFINITIONS
DISCLAIMERS
Short-form specification  The data in a short-form
specification is extracted from a full data sheet with the
same type number and title. For detailed information see
the relevant data sheet or data handbook.
Life support applications  These products are not
designed for use in life support appliances, devices, or
systems where malfunction of these products can
reasonably be expected to result in personal injury. Philips
Semiconductors customers using or selling these products
for use in such applications do so at their own risk and
agree to fully indemnify Philips Semiconductors for any
damages resulting from such application.
Limiting values definition  Limiting values given are in
accordance with the Absolute Maximum Rating System
(IEC 60134). Stress above one or more of the limiting
values may cause permanent damage to the device.
These are stress ratings only and operation of the device
at these or at any other conditions above those given in the
Characteristics sections of the specification is not implied.
Exposure to limiting values for extended periods may
affect device reliability.
Right to make changes  Philips Semiconductors
reserves the right to make changes in the products including circuits, standard cells, and/or software described or contained herein in order to improve design
and/or performance. When the product is in full production
(status ‘Production’), relevant changes will be
communicated via a Customer Product/Process Change
Notification (CPCN). Philips Semiconductors assumes no
responsibility or liability for the use of any of these
products, conveys no licence or title under any patent,
copyright, or mask work right to these products, and
makes no representations or warranties that these
products are free from patent, copyright, or mask work
right infringement, unless otherwise specified.
Application information  Applications that are
described herein for any of these products are for
illustrative purposes only. Philips Semiconductors make
no representation or warranty that such applications will be
suitable for the specified use without further testing or
modification.
2003 Jul 28
16
Philips Semiconductors – a worldwide company
Contact information
For additional information please visit http://www.semiconductors.philips.com.
Fax: +31 40 27 24825
For sales offices addresses send e-mail to: [email protected].
SCA75
© Koninklijke Philips Electronics N.V. 2003
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner.
The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed
without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license
under patent- or other industrial or intellectual property rights.
Printed in The Netherlands
613508/02/pp17
Date of release: 2003
Jul 28
Document order number:
9397 750 10567