PHILIPS 74ALVT16260DGG

INTEGRATED CIRCUITS
74ALVT16260
12-bit to 24-bit multiplexed D-type latches
(3-State)
Product specification
IC23 Data Handbook
1998 Jan 30
Philips Semiconductors
Product specification
2.5V/3.3V 12-bit to 24-bit multiplexed D-type latches
(3-State)
FEATURES
74ALVT16260
DESCRIPTION
• ESD protection exceeds 2000V per Mil-Std-883C, Method 3015;
The 74ALVT16260 is a 12-bit to 24-bit multiplexed D-type latch used
in applications where two separate data paths must be multiplexed
onto, or demultiplexed from, a single data path. Typical applications
include multiplexing and/or demultiplexing of address and data
information in microprocessor or bus-interface applications. This
device is alto useful in memory-interleaving applications.
exceeds 200V using machine model
• Latch-up protection exceeds 500mA per JEDEC Standard
JESD-17.
• Distributed VCC and GND pin configuration minimizes high-speed
Three 12-bit I/O ports (A1–A12, 1B1–1B12, and 2B1–2B12) are
available for address and/or data transfer. The output enable (OE1B,
OE2B, and OEA) inputs control the bus transceiver functions. The
OE1B and OE2B control signals also allow bank control in the A to
B direction.
switching noise.
• Output capability (–32mA IOH, 64mA IOL).
• Bus hold inputs eliminate the need for external pull-up resistors.
• 5V I/O compatible
• Live insertion/extraction permitted
• Power-up 3-State
• Power-up Reset
Address and/or data information can be stored using the internal
storage latches. The latch enable (LE1B, LE2B, LEA1B, and
LEA2B) inputs are used to control data storage. When the latch
enable input is high, the latch is transparent. When the latch enable
input goes low, the data present at the inputs is latched and remains
latched until the latch enable input is returned high.
To ensure the high-impedance state during power-up or
power-down, OE should be tied to VCC through a pull-up resistor;
the minimum value of the resistor is determined by the current
sinking capability of the driver.
The 74ALVT16260 is available in a 56-pin Shrink Small Outline
Package (SSOP) and 56-pin Thin Shrink Small Outline Package
(TSSOP).
QUICK REFERENCE DATA
SYMBOL
CONDITIONS
Tamb = 25°C; GND = 0V
PARAMETER
tPLH
Propagation delay
tPHL
nAx to nBx
CIN
Input capacitance
CL = 50 pF
nBx to nAx
TYPICAL
2.5V
3.3V
3.5
2.8
3.3
2.6
UNIT
ns
VI = 0 V or VCC
4
4
pF
COUT
Output capacitance
VI/O = 0 V or 5.0 V
9
9
pF
ICCZ
Total supply current
Outputs disabled
100
80
µA
ORDERING INFORMATION
TEMPERATURE RANGE
OUTSIDE NORTH AMERICA
NORTH AMERICA
DWG NUMBER
56-Pin Plastic SSOP Type III
PACKAGES
–40°C to +85°C
74ALVT16260 DL
AV16260 DL
SOT371-1
56-Pin Plastic TSSOP Type II
–40°C to +85°C
74ALVT16260 DGG
AV16260 DGG
SOT364-1
1998 Jan 30
2
853-2046-18918
Philips Semiconductors
Product specification
2.5V/3.3V 12-bit to 24-bit multiplexed D-type latches
(3-State)
74ALVT16260
PIN DESCRIPTION
PIN NUMBER
SYMBOL
FUNCTION
8, 9, 10, 12, 13, 14, 15, 16, 17, 19, 20, 21
An
Data inputs/outputs (A)
23, 24, 26, 31, 33, 34, 36, 37, 38, 40, 41, 42
1Bn
Data inputs/outputs (B1)
6, 5, 3, 54, 52, 51, 49, 48, 47, 45, 44, 43
2Bn
Data inputs/outputs (B2)
1, 29, 56
OEA, OE1B, OE2B
2, 27, 30, 55
LE1B, LE2B, LEA1B, LEA2B
28
SEL
B1/B2 input select input
4, 11, 18, 25, 32, 39, 46, 53
GND
Ground (0V)
7, 22, 35, 50
VCC
Positive supply voltage
PIN CONFIGURATION
1
56 OE2B
LE1B
2
55 LEA2B
2B3
3
54 2B4
GND
4
53 GND
2B2
5
52 2B5
2B1
6
51 2B6
VCC
7
50 VCC
A1
8
49 2B7
A2
9
48 2B8
GND 11
B to A (OEB = H)
INPUTS
OUTPUT
1B
2B
SEL
LE1B
LE2B
OEA
A
H
L
X
X
X
X
X
X
X
X
H
L
X
X
H
H
H
L
L
L
X
H
H
L
X
X
X
X
X
X
X
H
H
L
X
L
L
L
L
L
L
H
H
L
A0
H
L
A0
Z
47 2B9
A to B (OEA = H)
46 GND
INPUTS
OUTPUT
A4 12
45 2B10
A5 13
44 2B11
A
LEA1B
LEA2B
OE1B
OE2B
1B
2B
A6 14
43 2B12
H
H
H
L
L
H
H
A7 15
42 1B12
L
H
H
L
L
L
L
A8 16
41 1B11
H
H
L
L
L
H
2B0
A9 17
40 1B10
GND 18
39 GND
A10 19
38 1B9
A11 20
37 1B8
A12 21
36 1B7
VCC 22
35 VCC
L
H
L
L
L
L
2B0
H
L
H
L
L
1B0
H
L
L
H
L
L
1B0
L
X
L
L
L
L
1B0
2B0
X
X
X
H
H
Z
Z
X
X
L
H
Active
Z
1B1 23
34 1B6
X
1B2 24
33 1B5
X
X
X
H
L
Z
Active
GND 25
32 GND
X
X
X
L
L
Active
Active
1B3 26
31 1B4
LE2B 27
30 LEA1B
SEL 28
29 OE1B
SA00435
1998 Jan 30
Latch enable inputs
FUNCTION TABLES
OEA
A3 10
Output enable input (active low)
3
Philips Semiconductors
Product specification
2.5V/3.3V 12-bit to 24-bit multiplexed D-type latches
(3-State)
74ALVT16260
LOGIC DIAGRAM (POSITIVE LOGIC)
LE1B
LE2B
LEA1B
LEA2B
OE2B
OE1B
OEA
SEL
2
27
30
55
56
29
1
28
C1
G1
A1
8
1
1D
23
1B1
1
C1
1D
6
2B1
C1
1D
C1
1D
TO 11 OTHER CHANNELS
SA00436
1998 Jan 30
4
Philips Semiconductors
Product specification
2.5V/3.3V 12-bit to 24-bit multiplexed D-type latches
(3-State)
74ALVT16260
ABSOLUTE MAXIMUM RATINGS1, 2
PARAMETER
SYMBOL
VCC
IIK
RATING
UNIT
–0.5 to +4.6
V
–50
mA
–0.5 to +7.0
V
VO < 0
–50
mA
Output in Off or High state
–0.5 to +7.0
V
Output in Low state
128
Output in High state
–64
DC supply voltage
DC input diode current
VI < 0
voltage3
VI
DC input
IOK
DC output diode current
VOUT
CONDITIONS
DC output
voltage3
IOUT
O
DC output current
mA
Tstg
Storage temperature range
–65 to +150
°C
NOTES:
1. Stresses beyond those listed may cause permanent damage to the device. These are stress ratings only and functional operation of the
device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to
absolute-maximum-rated conditions for extended periods may affect device reliability.
2. The performance capability of a high-performance integrated circuit in conjunction with its thermal environment can create junction
temperatures which are detrimental to reliability. The maximum junction temperature of this integrated circuit should not exceed 150°C.
3. The input and output negative voltage ratings may be exceeded if the input and output clamp current ratings are observed.
RECOMMENDED OPERATING CONDITIONS
SYMBOL
VCC
2.5V RANGE LIMITS
PARAMETER
DC supply voltage
3.3V RANGE LIMITS
UNIT
MIN
MAX
MIN
MAX
2.3
2.7
3.0
3.6
V
0
5.5
0
5.5
V
VI
Input voltage
VIH
High-level input voltage
VIL
Input voltage
0.7
0.8
V
IOH
High-level output current
–8
–32
mA
Low-level output current
8
32
Low-level output current; current duty cycle ≤ 50%; f ≥ 1kHz
24
64
∆t/∆v
Input transition rise or fall rate; Outputs enabled
10
10
ns/V
Tamb
Operating free-air temperature range
+85
°C
IOL
1998 Jan 30
1.7
–40
5
2.0
+85
–40
V
mA
Philips Semiconductors
Product specification
2.5V/3.3V 12-bit to 24-bit multiplexed D-type latches
(3-State)
74ALVT16260
DC ELECTRICAL CHARACTERISTICS (3.3V 0.3V RANGE)
LIMITS
SYMBOL
PARAMETER
TEST CONDITIONS
Temp = -40°C to +85°C
MIN
VIK
VOH
VOL
VRST
Input clamp voltage
VCC = 3.0V; IIK = –18mA
High-level out
output
ut voltage
output
Low–level out
ut voltage
Power-up output low
voltage6
VCC = 3.0 to 3.6V; IOH = –100µA
VCC = 3.0V; IOH = –32mA
Input
In
ut leakage current
IHOLD
Off current
Bus Hold current
Data inputs7
–0.85
1.2
VCC–0.2
VCC
2.0
2.3
0.07
0.2
0.25
0.4
VCC = 3.0V; IOL = 32mA
0.3
0.5
VCC = 3.0V; IOL = 64mA
0.4
0.55
VCC = 3.6V; IO = 1mA; VI = VCC or GND
0.55
0.1
±1
VCC = 0 or 3.6V; VI = 5.5V
0.1
10
VCC = 3.6V; VI = VCC
0.1
1
0.1
-5
0.1
±100
Control pins
Data pins
ins4
VCC = 0V; VI or VO = 0 to 4.5V
VCC = 3V; VI = 0.8V
75
130
VCC = 3V; VI = 2.0V
–75
–140
VCC = 0V to 3.6V; VCC = 3.6V
±500
UNIT
V
V
VCC = 3.0V; IOL = 16mA
VCC = 3.6V; VI = 0V
IOFF
MAX
VCC = 3.0V; IOL = 100µA
VCC = 3.6V; VI = VCC or GND
II
TYP1
V
V
µA
µA
µA
Current into an output in the
High state when VO > VCC
VO = 5.5V; VCC = 3.0V
10
125
µA
Power up/down 3-State output
current3
VCC ≤ 1.2V; VO = 0.5V to VCC; VI = GND or VCC
OE/OE = Don’t care
1
±100
µA
IOZH
3-State output High current
VCC = 3.6V; VO = 3.0V; VI = VIL or VIH
0.5
5
µA
IOZL
3-State output Low current
VCC = 3.6V; VO = 0.5V; VI = VIL or VIH
0.5
5
µA
VCC = 3.6V; Outputs High, VI = GND or VCC, IO = 0
0.04
0.1
IEX
IPU/PD
ICCH
ICCL
Quiescent supply current
ICCZ
∆ICC
Additional supply current per
input pin2
VCC = 3.6V; Outputs Low, VI = GND or VCC, IO = 0
3.7
6
VCC = 3.6V; Outputs Disabled; VI = GND or VCC, IO = 05
0.04
0.1
VCC = 3V to 3.6V; One input at VCC–0.6V,
Other inputs at VCC or GND
0.04
0.4
mA
mA
NOTES:
1. All typical values are at VCC = 3.3V and Tamb = 25°C.
2. This is the increase in supply current for each input at the specified voltage level other than VCC or GND
3. This parameter is valid for any VCC between 0V and 1.2V with a transition time of up to 10msec. From VCC = 1.2V to VCC = 3.3V ± 0.2V a
transition time of 100µsec is permitted. This parameter is valid for Tamb = 25°C only.
4. Unused pins at VCC or GND.
5. ICCZ is measured with outputs pulled up to VCC or pulled down to ground.
6. For valid test results, data must not be loaded into the flip-flops (or latches) after applying power.
7. This is the bus hold overdrive current required to force the input to the opposite logic state.
1998 Jan 30
6
Philips Semiconductors
Product specification
2.5V/3.3V 12-bit to 24-bit multiplexed D-type latches
(3-State)
74ALVT16260
AC ELECTRICAL CHARACTERISTICS (3.3V ± 0.3V RANGE)
GND = 0V; tR = tF = 2.5ns; CL = 50pF; RL = 500Ω
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
tPZH
tPZL
tPHZ
tPLZ
Tamb = –40°C to +85°C
VCC = +3.3V ± 0.3V
PARAMETER
SYMBOL
FROM (INPUT)
TO (OUTPUT)
A or B
B or A
UNIT
MIN
TYP
MAX
1
2.8
4.8
ns
1
2.6
4.6
ns
1.1
2.9
4.6
ns
1.1
3.1
4.7
ns
LE
A or B
SEL (B1)
A
1.3
2.3
3.4
ns
SEL (B2)
A
1.1
2.4
3.8
ns
SEL (B1)
A
1.5
2.4
3.6
ns
SEL (B2)
A
1.6
2.4
3.6
ns
1
2.3
4.2
ns
OE
A or B
1.6
2.3
4.0
ns
2.2
4.4
6.0
ns
1.3
3.1
5.0
ns
OE
A or B
AC SETUP CHARACTERISTICS (3.3V ± 0.3V RANGE)
GND = 0V; tR = tF = 2.5ns; CL = 50pF; RL = 500Ω
SYMBOL
Tamb = –40°C to +85°C
VCC = +3.3V ± 0.3V
PARAMETER
MIN
tw
Pulse duration, LE1B, LE2B, LEA1B, or LEA2B high
tsu
th
1998 Jan 30
UNIT
MAX
3.3
ns
Setup time, data before LE1B, LE2B, LEA1B, or LEA2B↓
1
ns
Hold time, data after LE1B, LE2B, LEA1B, or LEA2B↓
1
ns
7
Philips Semiconductors
Product specification
2.5V/3.3V 12-bit to 24-bit multiplexed D-type latches
(3-State)
74ALVT16260
DC ELECTRICAL CHARACTERISTICS (2.5V 0.2V RANGE)
LIMITS
SYMBOL
PARAMETER
TEST CONDITIONS
Temp = -40°C to +85°C
MIN
VIK
Input clamp voltage
VCC = 2.3V; IIK = –18mA
VOH
High-level out
output
ut voltage
VOL
output
Low-level out
ut voltage
VRST
Power-up output low
voltage7
VCC = 2.3 to 3.6V; IOH = –100µA
VCC = 2.3V; IOH = –8mA
Input
In
ut leakage current
MAX
–0.85
–1.2
VCC–0.2
VCC
1.8
2.1
0.07
0.2
VCC = 2.3V; IOL = 24mA
0.3
0.5
VCC = 2.7V; IO = 1mA; VI = VCC or GND
0.55
0.1
±1
VCC = 0 or 2.7V; VI = 5.5V
0.1
10
VCC = 2.7V; VI = VCC
0.1
1
Control pins
Data pins
ins4
VCC = 2.7V; VI = 0
UNIT
V
V
VCC = 2.3V; IOL = 100µA
VCC = 2.7V; VI = VCC or GND
II
TYP1
V
µA
0.1
-5
Off current
VCC = 0V; VI or VO = 0 to 4.5V
0.1
100
Bus Hold current
VCC = 2.3V; VI = 0.7V
90
Data inputs6
VCC = 2.3V; VI = 1.7V
–10
Current into an output in the
High state when VO > VCC
VO = 5.5V; VCC = 2.3V
10
125
µA
Power up/down 3-State output
current3
VCC ≤ 1.2V; VO = 0.5V to VCC; VI = GND or VCC;
OE/OE = Don’t care
1
100
µA
IOZH
3-State output High current
VCC = 2.7V; VO = 2.3V; VI = VIL or VIH
0.5
5
µA
IOZL
3-State output Low current
VCC = 2.7V; VO = 0.5V; VI = VIL or VIH
0.5
–5
µA
VCC = 2.7V; Outputs High, VI = GND or VCC, IO = 0
0.04
0.1
VCC = 2.7V; Outputs Low, VI = GND or VCC, IO = 0
2.7
4.5
VCC = 2.7V; Outputs Disabled; VI = GND or VCC, IO = 05
0.04
0.1
VCC = 2.3V to 2.7V; One input at VCC–0.6V,
Other inputs at VCC or GND
0.04
0.4
IOFF
IHOLD
IEX
IPU/PD
ICCH
ICCL
Quiescent supply current
ICCZ
∆ICC
Additional supply current per
input pin2
µA
µA
mA
mA
NOTES:
1. All typical values are at VCC = 2.5V and Tamb = 25°C.
2. This is the increase in supply current for each input at the specified voltage level other than VCC or GND
3. This parameter is valid for any VCC between 0V and 1.2V with a transition time of up to 10msec. From VCC = 1.2V to VCC = 2.5V ± 0.3V a
transition time of 100µsec is permitted. This parameter is valid for Tamb = 25°C only.
4. Unused pins at VCC or GND.
5. ICCZ is measured with outputs pulled up to VCC or pulled down to ground.
6. Not guaranteed.
7. For valid test results, data must not be loaded into the flip-flops (or latches) after applying power.
1998 Jan 30
8
Philips Semiconductors
Product specification
2.5V/3.3V 12-bit to 24-bit multiplexed D-type latches
(3-State)
74ALVT16260
AC ELECTRICAL CHARACTERISTICS (2.5V ± 0.2V RANGE)
GND = 0V; tR = tF = 2.5ns; CL = 50pF; RL = 500Ω
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
tPZH
tPZL
tPHZ
tPLZ
Tamb = –40°C to +85°C
VCC = +2.5V ± 0.2V
PARAMETER
SYMBOL
FROM (INPUT)
TO (OUTPUT)
A or B
B or A
UNIT
MIN
TYP
MAX
1
3.5
5.3
ns
1
3.3
5.4
ns
1.1
3.9
6.0
ns
1.1
4.2
6.2
ns
LE
A or B
SEL (B1)
A
1.3
2.9
4.5
ns
SEL (B2)
A
1.1
3.3
4.8
ns
SEL (B1)
A
1.5
3.0
4.5
ns
SEL (B2)
A
1.6
3.2
4.6
ns
1
3.1
5.0
ns
OE
A or B
1.6
2.0
3.0
ns
2.2
4.0
6.6
ns
1.3
2.0
3.4
ns
OE
A or B
AC SETUP CHARACTERISTICS (2.5V ± 0.2V RANGE)
GND = 0V; tR = tF = 2.5ns; CL = 50pF; RL = 500Ω
SYMBOL
Tamb = –40°C to +85°C
VCC = +2.5V ± 0.2V
PARAMETER
MIN
tw
Pulse duration, LE1B, LE2B, LEA1B, or LEA2B high
tsu
th
1998 Jan 30
UNIT
MAX
3.3
ns
Setup time, data before LE1B, LE2B, LEA1B, or LEA2B↓
1
ns
Hold time, data after LE1B, LE2B, LEA1B, or LEA2B↓
1
ns
9
Philips Semiconductors
Product specification
2.5V/3.3V 12-bit to 24-bit multiplexed D-type latches
(3-State)
74ALVT16260
AC WAVEFORMS
VM = 1.5V for all waveforms
The outputs are measured one at a time with one transition per measurement.
3V
VM
TIMING INPUT
tw
0V
3V
INPUT
VM
tsu
VM
th
3V
0V
DATA INPUT
VM
VM
0V
SA00437
SA00439
Figure 1. Pulse duration
Figure 3. Setup and hold times
3V
INPUT
VM
VM
tPLH
tPHL
3V
OUTPUT
CONTROL
VM
VM
tPZL
tPLZ
0V
0V
VOH
VM
OUTPUT
VOL
tPHL
VM
tPZH
tPLH
VOH
VM
OUTPUT
3.5V
OUTPUT
WAVEFORM 1
S1 AT 7V
VM
VM
VOH – 0.3V
≈0V
VOL
SA00438
SA00440
All input pulses are supplied by generators having the following
characteristics: PRR ≤ 10MHz, ZO = 50Ω, tr ≤ 2.5ns, tf ≤ 2.5ns.
Figure 2. Propagation delay times;
inverting and non-inverting outputs
Waveform 1 is for an output with internal conditions such that the
output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the
output is high except when disabled by the output control.
Figure 4. Enable and disable times;
low- and high-level enabling
TEST LOAD CIRCUIT
7V
500Ω
FROM OUTPUT UNDER TEST
CL = 50pF
(INCLUDES PROBE AND
JIG CAPACITANCE)
S1
OPEN
GND
500Ω
Load Circuit for Outputs
TEST
tPLH/tPHL
tPLZ/tPZL
tPHZ/tPZH
S1
Open
7V
Open
SA00441
Figure 5. Test load circuit
1998 Jan 30
VOL
VOH
OUTPUT
WAVEFORM 2
S1 AT OPEN
VM
VOL + 0.3V
tPHZ
10
Philips Semiconductors
Product specification
12-bit to 24-bit multiplexed D-type latches (3-State)
SSOP56: plastic shrink small outline package; 56 leads; body width 7.5 mm
1988 Jan 30
11
74ALVT16260
SOT371-1
Philips Semiconductors
Product specification
12-bit to 24-bit multiplexed D-type latches (3-State)
TSSOP56: plastic thin shrink small outline package; 56 leads; body width 6.1mm
1988 Jan 30
12
74ALVT16260
SOT364-1
Philips Semiconductors
Product specification
12-bit to 24-bit multiplexed D-type latches (3-State)
NOTES
1988 Jan 30
13
74ALVT16260
Philips Semiconductors
Product specification
12-bit to 24-bit multiplexed D-type latches (3-State)
74ALVT16260
Data sheet status
Data sheet
status
Product
status
Definition [1]
Objective
specification
Development
This data sheet contains the design target or goal specifications for product development.
Specification may change in any manner without notice.
Preliminary
specification
Qualification
This data sheet contains preliminary data, and supplementary data will be published at a later date.
Philips Semiconductors reserves the right to make chages at any time without notice in order to
improve design and supply the best possible product.
Product
specification
Production
This data sheet contains final specifications. Philips Semiconductors reserves the right to make
changes at any time without notice in order to improve design and supply the best possible product.
[1] Please consult the most recently issued datasheet before initiating or completing a design.
Definitions
Short-form specification — The data in a short-form specification is extracted from a full data sheet with the same type number and title. For
detailed information see the relevant data sheet or data handbook.
Limiting values definition — Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one
or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or
at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended
periods may affect device reliability.
Application information — Applications that are described herein for any of these products are for illustrative purposes only. Philips
Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or
modification.
Disclaimers
Life support — These products are not designed for use in life support appliances, devices or systems where malfunction of these products can
reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications
do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application.
Right to make changes — Philips Semiconductors reserves the right to make changes, without notice, in the products, including circuits, standard
cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no
responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these
products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless
otherwise specified.
 Copyright Philips Electronics North America Corporation 1998
All rights reserved. Printed in U.S.A.
Philips Semiconductors
811 East Arques Avenue
P.O. Box 3409
Sunnyvale, California 94088–3409
Telephone 800-234-7381
print code
Document order number:
1988 Jan 30
14
Date of release: 05-96
9397-750-03337