74HC27; 74HCT27 Triple 3-input NOR gate Rev. 03 — 7 January 2008 Product data sheet 1. General description The 74HC27; 74HCT27 is a high-speed Si-gate CMOS device and is pin compatible with Low-Power Schottky TTL (LSTTL). The 74HC27; 74HCT27 provides the 3-input NOR function. 2. Features ■ Multiple package options ■ Complies with JEDEC standard no. 7A ■ ESD protection: ◆ HBM JESD22-A114E exceeds 2000 V ◆ MM JESD22-A115-A exceeds 200 V ■ Specified from −40 °C to +85 °C and from −40 °C to +125 °C 3. Ordering information Table 1. Ordering information Type number Package Temperature range Name Description Version 74HC27N −40 °C to +125 °C DIP14 plastic dual in-line package; 14 leads (300 mil) SOT27-1 74HC27D −40 °C to +125 °C SO14 plastic small outline package; 14 leads; body width 3.9 mm SOT108-1 74HC27DB −40 °C to +125 °C SSOP14 plastic shrink small outline package; 14 leads; body width SOT337-1 5.3 mm 74HC27PW −40 °C to +125 °C TSSOP14 plastic thin shrink small outline package; 14 leads; body width 4.4 mm 74HC27BQ −40 °C to +125 °C DHVQFN14 plastic dual in-line compatible thermal enhanced very thin SOT762-1 quad flat package; no leads; 14 terminals; body 2.5 × 3 × 0.85 mm 74HCT27N −40 °C to +125 °C DIP14 plastic dual in-line package; 14 leads (300 mil) SOT27-1 74HCT27D −40 °C to +125 °C SO14 plastic small outline package; 14 leads; body width 3.9 mm SOT108-1 SOT402-1 74HC27; 74HCT27 NXP Semiconductors Triple 3-input NOR gate Table 1. Ordering information …continued Type number Package Temperature range Name Description Version 74HCT27DB −40 °C to +125 °C SSOP14 plastic shrink small outline package; 14 leads; body width SOT337-1 5.3 mm 74HCT27PW −40 °C to +125 °C TSSOP14 plastic thin shrink small outline package; 14 leads; body width 4.4 mm 74HCT27BQ −40 °C to +125 °C DHVQFN14 plastic dual in-line compatible thermal enhanced very thin SOT762-1 quad flat package; no leads; 14 terminals; body 2.5 × 3 × 0.85 mm SOT402-1 4. Functional diagram 1 2 1 1A 2 1B 1C 3 3 2A 4 4 2B 5 2C 9 3A 10 3B 11 3C 12 2Y 6 3Y 8 12 13 13 1Y ≥1 ≥1 6 5 9 10 A ≥1 8 mna936 Fig 1. Logic symbol mna935 Fig 2. IEC logic symbol 74HC_HCT27_3 Product data sheet B Y 11 C mna937 Fig 3. Logic diagram (one gate) © NXP B.V. 2008. All rights reserved. Rev. 03 — 7 January 2008 2 of 16 74HC27; 74HCT27 NXP Semiconductors Triple 3-input NOR gate 5. Pinning information 5.1 Pinning 74HC27 74HCT27 1 1A terminal 1 index area 1A 1 14 VCC 1B 2 13 1C 14 VCC 74HC27 74HCT27 1B 2 13 1C 2A 3 12 1Y 4 11 3C 2B 4 11 3C 2C 5 10 3B 2C 5 10 3B 2Y 6 9 2Y 6 9 3A 8 GND 7 8 3Y 3Y 12 1Y 7 3 GND 2A 2B 3A 001aag760 Transparent top view 001aag759 (1) The die substrate is attached to this pad using conductive die attach material. It can not be used as supply pin or input Fig 4. Pin configuration DIP14, SO14, (T)SSOP14 Fig 5. Pin configuration DHVQFN14 5.2 Pin description Table 2. Pin description Symbol Pin Description 1A 1 data input 1B 2 data input 2A 3 data input 2B 4 data input 2C 5 data input 2Y 6 data output GND 7 ground (0 V) 3Y 8 data output 3A 9 data input 3B 10 data input 3C 11 data input 1Y 12 data output 1C 13 data input VCC 14 supply voltage 74HC_HCT27_3 Product data sheet © NXP B.V. 2008. All rights reserved. Rev. 03 — 7 January 2008 3 of 16 74HC27; 74HCT27 NXP Semiconductors Triple 3-input NOR gate 6. Functional description Table 3. Function table[1] Inputs Outputs nA nB nC nY L L L H X X H L X H X L H X X L [1] H = HIGH voltage level; L = LOW voltage level; X = don’t care. 7. Limiting values Table 4. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V). Symbol Parameter Conditions Min Max Unit VCC supply voltage −0.5 +7 V IIK input clamping current VI < −0.5 V or VI > VCC + 0.5 V [1] - ±20 mA IOK output clamping current VO < −0.5 V or VO > VCC + 0.5 V [1] - ±20 mA IO output current −0.5 V < VO < VCC + 0.5 V - ±25 mA ICC supply current - 50 mA IGND ground current −50 - mA Tstg storage temperature −65 +150 °C DIP14 package - 750 mW SO14, (T)SSOP14 and DHVQFN14 packages - 500 mW [2] total power dissipation Ptot [1] The input and output voltage ratings may be exceeded if the input and output current ratings are observed. [2] For DIP14 package: Ptot derates linearly with 12 mW/K above 70 °C. For SO14 package: Ptot derates linearly with 8 mW/K above 70 °C. For (T)SSOP14 packages: Ptot derates linearly with 5.5 mW/K above 60 °C. For DHVQFN14 packages: Ptot derates linearly with 4.5 mW/K above 60 °C. 8. Recommended operating conditions Table 5. Recommended operating conditions Symbol Parameter Conditions Min Typ Max Unit Type 74HC27 VCC supply voltage 2.0 5.0 6.0 V VI input voltage 0 - VCC V VO output voltage 0 - VCC V 74HC_HCT27_3 Product data sheet © NXP B.V. 2008. All rights reserved. Rev. 03 — 7 January 2008 4 of 16 74HC27; 74HCT27 NXP Semiconductors Triple 3-input NOR gate Table 5. Recommended operating conditions …continued Symbol Parameter Conditions Min Typ Max Unit tr, tf input rise and fall times VCC = 2.0 V - - 1000 ns VCC = 4.5 V - 6.0 500 ns VCC = 6.0 V - - 400 ns ambient temperature −40 - +125 °C VCC supply voltage 4.5 5.0 5.5 V VI input voltage 0 - VCC V VO output voltage 0 - VCC V tr, tf input rise and fall times - 6.0 500 ns Tamb ambient temperature −40 - +125 °C Tamb Type 74HCT27 VCC = 4.5 V 9. Static characteristics Table 6. Static characteristics type 74HC27; 74HCT27 At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter 25 °C Conditions −40 °C to +85 °C −40 °C to +125 °C Unit Min Typ Max Min Max Min Max 74HC27 VIH VIL VOH VOL HIGH-level input voltage VCC = 2.0 V 1.5 1.2 - 1.5 - 1.5 - V VCC = 4.5 V 3.15 2.4 - 3.15 - 3.15 - V VCC = 6.0 V 4.2 3.2 - 4.2 - 4.2 - V LOW-level input voltage VCC = 2.0 V - 0.8 0.5 - 0.5 - 0.5 V VCC = 4.5 V - 2.1 1.35 - 1.35 - 1.35 V VCC = 6.0 V - 2.8 1.8 - 1.8 - 1.8 V HIGH-level VI = VIH or VIL output voltage IO = −20 µA; VCC = 2.0 V 1.9 2.0 - 1.9 - 1.9 - V IO = −20 µA; VCC = 4.5 V 4.4 4.5 - 4.4 - 4.4 - V IO = −20 µA; VCC = 6.0 V 5.9 6.0 - 5.9 - 5.9 - V IO = −4.0 mA; VCC = 4.5 V 3.98 4.32 - 3.84 - 3.7 - V IO = −5.2 mA; VCC = 6.0 V 5.48 5.81 - 5.34 - 5.2 - V LOW-level VI = VIH or VIL output voltage IO = 20 µA; VCC = 2.0 V - 0 0.1 - 0.1 - 0.1 V IO = 20 µA; VCC = 4.5 V - 0 0.1 - 0.1 - 0.1 V IO = 20 µA; VCC = 6.0 V - 0 0.1 - 0.1 - 0.1 V IO = 4.0 mA; VCC = 4.5 V - 0.15 0.26 - 0.33 - 0.4 V IO = 5.2 mA; VCC = 6.0 V - 0.16 0.26 - 0.33 - 0.4 V - - ±0.1 - ±1.0 - ±1.0 µA II input leakage current VI = VCC or GND; VCC = 6.0 V ICC supply current VI = VCC or GND; IO = 0 A; VCC = 6.0 V - - 2.0 - 20 - 40 µA CI input capacitance - 3.5 - - - - - pF 74HC_HCT27_3 Product data sheet © NXP B.V. 2008. All rights reserved. Rev. 03 — 7 January 2008 5 of 16 74HC27; 74HCT27 NXP Semiconductors Triple 3-input NOR gate Table 6. Static characteristics type 74HC27; 74HCT27 …continued At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter 25 °C Conditions −40 °C to +85 °C −40 °C to +125 °C Unit Min Typ Max Min Max Min Max 74HCT27 VIH HIGH-level input voltage VCC = 4.5 V to 5.5 V 2.0 1.6 - 2.0 - 2.0 - V VIL LOW-level input voltage VCC = 4.5 V to 5.5 V - 1.2 0.8 - 0.8 - 0.8 V VOH HIGH-level VI = VIH or VIL; VCC = 4.5 V output voltage IO = −20 µA 4.4 4.5 - 4.4 - 4.4 - V 3.98 4.32 - 3.84 - 3.7 - V IO = −4.0 mA VOL LOW-level VI = VIH or VIL; VCC = 4.5 V output voltage IO = 20 µA - 0 0.1 - 0.1 - 0.1 V IO = 4.0 mA - 0.16 0.26 - 0.33 - 0.4 V VI = VCC or GND; VCC = 5.5 V - - ±0.1 - ±1.0 - ±1.0 µA - - 2.0 - 20 - 40 µA - 150 540 - 675 - 735 µA - 3.5 - - - - - pF II input leakage current ICC supply current VI = VCC or GND; VCC = 5.5 V; IO = 0 A ∆ICC additional per input pin; supply current VI = VCC − 2.1 V; other inputs at VCC or GND; VCC = 4.5 V to 5.5 V; IO = 0 A nA, nB or nC inputs CI input capacitance 10. Dynamic characteristics Table 7. Dynamic characteristics type 74HC27; 74HCT27 GND = 0 V; for load circuit see Figure 7. Symbol Parameter 25 °C Conditions −40 °C to +125 °C Unit Min Typ Max Max (85 °C) Max (125 °C) - 28 90 115 135 VCC = 4.5 V - 10 18 23 27 ns VCC = 5.0 V; CL = 15 pF - 8 - - - ns - 8 15 20 23 ns VCC = 2.0 V - 19 75 95 110 ns VCC = 4.5 V - 7 15 19 22 ns VCC = 6.0 V - 6 13 16 19 ns 74HC27 tpd propagation delay nA, nB, nC to nY; see Figure 6 [1] VCC = 2.0 V VCC = 6.0 V tt transition time see Figure 6 [2] 74HC_HCT27_3 Product data sheet ns © NXP B.V. 2008. All rights reserved. Rev. 03 — 7 January 2008 6 of 16 74HC27; 74HCT27 NXP Semiconductors Triple 3-input NOR gate Table 7. Dynamic characteristics type 74HC27; 74HCT27 GND = 0 V; for load circuit see Figure 7. Symbol Parameter CPD 25 °C Conditions per package; VI = GND to VCC [3] propagation delay nA, nB, nC to nY; see Figure 6 [1] power dissipation capacitance −40 °C to +125 °C Unit Min Typ Max Max (85 °C) Max (125 °C) - 24 - - - pF 74HCT27 tpd transition time tt power dissipation capacitance CPD VCC = 4.5 V - 12 21 26 32 ns VCC = 5.0 V; CL = 15 pF - 10 - - - ns VCC = 4.5 V; see Figure 6 [2] - 7 15 19 22 ns per package; VI = GND to VCC − 1.5 V [3] - 30 - - - pF [1] tpd is the same as tPHL and tPLH. [2] tt is the same as tTHL and tTLH. [3] CPD is used to determine the dynamic power dissipation (PD in µW): PD = CPD × VCC2 × fi × N + ∑ (CL × VCC2 × fo) where: fi = input frequency in MHz; fo = output frequency in MHz; CL = output load capacitance in pF; VCC = supply voltage in V; N = number of inputs switching; ∑ (CL × VCC2 × fo) = sum of outputs. 11. Waveforms VI nA, nB, nC input VM GND tPHL VOH tPLH VY VM VX nY output VOL tTHL tTLH 001aag761 Measurement points are given in Table 8. VOL and VOH are typical voltage output drop that occur with the output load. Fig 6. Input (nA, nB, nC) to output (nY) propagation delays and output transition times Table 8. Measurement points Type Input Output VM VM VX VY 74HC27 0.5VCC 0.5VCC 0.1VCC 0.9VCC 74HCT27 1.3 V 1.3 V 0.1VCC 0.9VCC 74HC_HCT27_3 Product data sheet © NXP B.V. 2008. All rights reserved. Rev. 03 — 7 January 2008 7 of 16 74HC27; 74HCT27 NXP Semiconductors Triple 3-input NOR gate VI tW 90 % negative pulse VM 0V VI tf tr tr tf 90 % positive pulse 0V VM 10 % VM VM 10 % tW VCC VCC PULSE GENERATOR VI VO RL S1 open DUT RT CL 001aad983 Test data is given in Table 9. Definitions test circuit: RT = Termination resistance should be equal to output impedance Zo of the pulse generator. CL = Load capacitance including jig and probe capacitance. RL = Load resistance. S1 = Test selection switch Fig 7. Load circuit for measuring switching times Table 9. Test data Type Input Load S1 position VI tr, tf CL RL tPHL, tPLH 74HC27 VCC 6 ns 15 pF, 50 pF 1 kΩ open 74HCT27 3V 6 ns 15 pF, 50 pF 1 kΩ open 74HC_HCT27_3 Product data sheet © NXP B.V. 2008. All rights reserved. Rev. 03 — 7 January 2008 8 of 16 74HC27; 74HCT27 NXP Semiconductors Triple 3-input NOR gate 12. Package outline DIP14: plastic dual in-line package; 14 leads (300 mil) SOT27-1 ME seating plane D A2 A A1 L c e Z w M b1 (e 1) b MH 8 14 pin 1 index E 1 7 0 5 10 mm scale DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT A max. A1 min. A2 max. b b1 c D (1) E (1) e e1 L ME MH w Z (1) max. mm 4.2 0.51 3.2 1.73 1.13 0.53 0.38 0.36 0.23 19.50 18.55 6.48 6.20 2.54 7.62 3.60 3.05 8.25 7.80 10.0 8.3 0.254 2.2 inches 0.17 0.02 0.13 0.068 0.044 0.021 0.015 0.014 0.009 0.77 0.73 0.26 0.24 0.1 0.3 0.14 0.12 0.32 0.31 0.39 0.33 0.01 0.087 Note 1. Plastic or metal protrusions of 0.25 mm (0.01 inch) maximum per side are not included. REFERENCES OUTLINE VERSION IEC JEDEC JEITA SOT27-1 050G04 MO-001 SC-501-14 EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-13 Fig 8. Package outline SOT27-1 (DIP14) 74HC_HCT27_3 Product data sheet © NXP B.V. 2008. All rights reserved. Rev. 03 — 7 January 2008 9 of 16 74HC27; 74HCT27 NXP Semiconductors Triple 3-input NOR gate SO14: plastic small outline package; 14 leads; body width 3.9 mm SOT108-1 D E A X c y HE v M A Z 8 14 Q A2 A (A 3) A1 pin 1 index θ Lp 1 L 7 e detail X w M bp 0 2.5 5 mm scale DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (1) e HE L Lp Q v w y Z (1) mm 1.75 0.25 0.10 1.45 1.25 0.25 0.49 0.36 0.25 0.19 8.75 8.55 4.0 3.8 1.27 6.2 5.8 1.05 1.0 0.4 0.7 0.6 0.25 0.25 0.1 0.7 0.3 0.01 0.019 0.0100 0.35 0.014 0.0075 0.34 0.16 0.15 0.010 0.057 inches 0.069 0.004 0.049 0.05 0.244 0.039 0.041 0.228 0.016 0.028 0.024 0.01 0.01 0.028 0.004 0.012 θ o 8 o 0 Note 1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included. REFERENCES OUTLINE VERSION IEC JEDEC SOT108-1 076E06 MS-012 JEITA EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-19 Fig 9. Package outline SOT108-1 (SO14) 74HC_HCT27_3 Product data sheet © NXP B.V. 2008. All rights reserved. Rev. 03 — 7 January 2008 10 of 16 74HC27; 74HCT27 NXP Semiconductors Triple 3-input NOR gate SSOP14: plastic shrink small outline package; 14 leads; body width 5.3 mm D SOT337-1 E A X c y HE v M A Z 8 14 Q A2 A (A 3) A1 pin 1 index θ Lp L 7 1 detail X w M bp e 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (1) e HE L Lp Q v w y Z (1) θ mm 2 0.21 0.05 1.80 1.65 0.25 0.38 0.25 0.20 0.09 6.4 6.0 5.4 5.2 0.65 7.9 7.6 1.25 1.03 0.63 0.9 0.7 0.2 0.13 0.1 1.4 0.9 8 o 0 o Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT337-1 REFERENCES IEC JEDEC JEITA EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-19 MO-150 Fig 10. Package outline SOT337-1 (SSOP14) 74HC_HCT27_3 Product data sheet © NXP B.V. 2008. All rights reserved. Rev. 03 — 7 January 2008 11 of 16 74HC27; 74HCT27 NXP Semiconductors Triple 3-input NOR gate TSSOP14: plastic thin shrink small outline package; 14 leads; body width 4.4 mm SOT402-1 E D A X c y HE v M A Z 8 14 Q (A 3) A2 A A1 pin 1 index θ Lp L 1 7 e detail X w M bp 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (2) e HE L Lp Q v w y Z (1) θ mm 1.1 0.15 0.05 0.95 0.80 0.25 0.30 0.19 0.2 0.1 5.1 4.9 4.5 4.3 0.65 6.6 6.2 1 0.75 0.50 0.4 0.3 0.2 0.13 0.1 0.72 0.38 8 o 0 o Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT402-1 REFERENCES IEC JEDEC JEITA EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-18 MO-153 Fig 11. Package outline SOT402-1 (TSSOP14) 74HC_HCT27_3 Product data sheet © NXP B.V. 2008. All rights reserved. Rev. 03 — 7 January 2008 12 of 16 74HC27; 74HCT27 NXP Semiconductors Triple 3-input NOR gate DHVQFN14: plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads; SOT762-1 14 terminals; body 2.5 x 3 x 0.85 mm A B D A A1 E c detail X terminal 1 index area terminal 1 index area C e1 e 2 6 y y1 C v M C A B w M C b L 1 7 Eh e 14 8 13 9 Dh X 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT mm A(1) max. A1 b 1 0.05 0.00 0.30 0.18 c D (1) Dh E (1) Eh 0.2 3.1 2.9 1.65 1.35 2.6 2.4 1.15 0.85 e 0.5 e1 L v w y y1 2 0.5 0.3 0.1 0.05 0.05 0.1 Note 1. Plastic or metal protrusions of 0.075 mm maximum per side are not included. REFERENCES OUTLINE VERSION IEC JEDEC JEITA SOT762-1 --- MO-241 --- EUROPEAN PROJECTION ISSUE DATE 02-10-17 03-01-27 Fig 12. Package outline SOT762-1 (DHVQFN14) 74HC_HCT27_3 Product data sheet © NXP B.V. 2008. All rights reserved. Rev. 03 — 7 January 2008 13 of 16 74HC27; 74HCT27 NXP Semiconductors Triple 3-input NOR gate 13. Abbreviations Table 10. Abbreviations Acronym Description CMOS Complementary Metal Oxide Semiconductor DUT Device Under Test ESD ElectroStatic Discharge HBM Human Body Model MM Machine Model TTL Transistor-Transistor Logic 14. Revision history Table 11. Revision history Document ID Release date Data sheet status Change notice Supersedes 74HC_HCT27_3 20080107 Product data sheet - Modifications: 74HC_HCT27_CNV_2 The format of this data sheet has been redesigned to comply with the new identity guidelines of NXP Semiconductors. • • Legal texts have been adapted to the new company name where appropriate. Added type number 74HC27BQ and 74HCT27BQ (DHVQFN14 package) 19970828 Product specification 74HC_HCT27_3 Product data sheet 74HC_HCT27_CNV_2 • - - © NXP B.V. 2008. All rights reserved. Rev. 03 — 7 January 2008 14 of 16 74HC27; 74HCT27 NXP Semiconductors Triple 3-input NOR gate 15. Legal information 15.1 Data sheet status Document status[1][2] Product status[3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification. [1] Please consult the most recently issued document before initiating or completing a design. [2] The term ‘short data sheet’ is explained in section “Definitions”. [3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com. 15.2 Definitions Draft — The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet — A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. 15.3 Disclaimers General — Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use — NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk. Applications — Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Limiting values — Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) may cause permanent damage to the device. Limiting values are stress ratings only and operation of the device at these or any other conditions above those given in the Characteristics sections of this document is not implied. Exposure to limiting values for extended periods may affect device reliability. Terms and conditions of sale — NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, including those pertaining to warranty, intellectual property rights infringement and limitation of liability, unless explicitly otherwise agreed to in writing by NXP Semiconductors. In case of any inconsistency or conflict between information in this document and such terms and conditions, the latter will prevail. No offer to sell or license — Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. 15.4 Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. 16. Contact information For additional information, please visit: http://www.nxp.com For sales office addresses, send an email to: [email protected] 74HC_HCT27_3 Product data sheet © NXP B.V. 2008. All rights reserved. Rev. 03 — 7 January 2008 15 of 16 74HC27; 74HCT27 NXP Semiconductors Triple 3-input NOR gate 17. Contents 1 2 3 4 5 5.1 5.2 6 7 8 9 10 11 12 13 14 15 15.1 15.2 15.3 15.4 16 17 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Ordering information . . . . . . . . . . . . . . . . . . . . . 1 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2 Pinning information . . . . . . . . . . . . . . . . . . . . . . 3 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3 Functional description . . . . . . . . . . . . . . . . . . . 4 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 4 Recommended operating conditions. . . . . . . . 4 Static characteristics. . . . . . . . . . . . . . . . . . . . . 5 Dynamic characteristics . . . . . . . . . . . . . . . . . . 6 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Package outline . . . . . . . . . . . . . . . . . . . . . . . . . 9 Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Revision history . . . . . . . . . . . . . . . . . . . . . . . . 14 Legal information. . . . . . . . . . . . . . . . . . . . . . . 15 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 15 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Contact information. . . . . . . . . . . . . . . . . . . . . 15 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. © NXP B.V. 2008. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: [email protected] Date of release: 7 January 2008 Document identifier: 74HC_HCT27_3