INTEGRATED CIRCUITS 74ALS573B/74ALS574A Latch flip–flop Product specification IC05 Data Handbook 1991 Feb 08 Philips Semiconductors Product specification Latch/flip-flop 74ALS573B 74ALS574A 74ALS573B/74ALS574A Octal transparent latch (3-State) Octal D flip-flop (3-State) It is an 8-bit edge triggered register coupled to eight 3-State output buffers. The two sections of the device are controlled independently by clock (CP) and output enable (OE) control gates. FEATURES • 74ALS573B is broadside pinout version of 74ALS373 • 74ALS574A is broadside pinout version of 74ALS374 • Inputs and outputs on opposite side of package allow easy The register is fully edge triggered. The state of the D input, one setup time before the Low-to-High clock transition is transferred to the corresponding flip-flop’s Q output. interface to microprocessors • Useful as an input or output port for microprocessors • 3-State outputs for bus interfacing • Common output enable • 74ALS563A and 74ALS564A are inverting version of 74ALS573B The active-Low output enable (OE) controls all eight 3-State buffers independent of the latch operation. When OE is Low, latched or transparent data appears at the output. When OE is High, the outputs are in high impedance “off” state, which means they will neither drive nor load the bus. and 74ALS574A respectively TYPICAL PROPAGATION DELAY TYPICAL SUPPLY CURRENT (TOTAL) 74ALS573B 5.0ns 12mA 74ALS574A 6.0ns 15mA TYPE DESCRIPTION The 74ALS573B is an octal transparent latch coupled to eight 3-State output devices. The two sections of the device are controlled independently by enable (E) and output enable (OE) control gates. The 74ALS573B is functionally identical to the 74ALS373 but has a broadside pinout configuration to facilitate PC board layout and allow easy interface with microprocessors. ORDERING INFORMATION ORDER CODE The data on the D inputs is transferred to the latch outputs when the enable (E) input is High. The latch remains transparent to the data input while E is High, and stores the data that is present one setup time before the High-to-Low enable transition. The 74ALS574A is functionally identical to the 74ALS374 but has a broadside pinout configuration to facilitate PC board layout and allow easy interface with microprocessors. DESCRIPTION COMMERCIAL RANGE VCC = 5V ±10%, Tamb = 0°C to +70°C DRAWING NUMBER 20-pin plastic DIP 74ALS573BN, 74ALS574AN SOT146-1 20-pin plastic SOL 74ALS573BD, 74ALS574AD SOT163-1 20-pin plastic SSOP Type II 74ALS573BDB, 74ALS574ADB SOT339-1 INPUT AND OUTPUT LOADING AND FAN-OUT TABLE 74ALS (U.L.) HIGH/LOW LOAD VALUE HIGH/LOW Data inputs 1.0/1.0 20µA/0.2mA Latch enable input 1.0/1.0 20µA/0.1mA Output Enable input (active-Low) 1.0/1.0 20µA/0.1mA Clock pulse input (active rising edge) 1.0/2.0 20µA/0.2mA Data outputs 130/240 2.6mA/24mA PINS D0 – D7 E (74ALS573B) OE CP (74ALS574A) Q0 – Q7 DESCRIPTION NOTE: One (1.0) ALS unit load is defined as: 20µA in the High state and 0.1mA in the Low state. 1991 Feb 08 2 853–1307 01670 Philips Semiconductors Product specification Latch/flip-flop 74ALS573B/74ALS574A PIN CONFIGURATION – 74ALS573B PIN CONFIGURATION – 74ALS574A OE 1 20 VCC OE 1 20 VCC D0 2 19 Q0 D0 2 19 Q0 D1 3 18 Q1 D1 3 18 Q1 D2 4 17 Q2 D2 4 17 Q2 D3 5 16 Q3 D3 5 16 Q3 D4 6 15 Q4 D4 6 15 Q4 D5 7 14 Q5 D5 7 14 Q5 D6 8 13 Q6 D6 8 13 Q6 D7 9 12 Q7 D7 9 12 Q7 11 E 11 CP GND 10 GND 10 SF01073 SF01074 LOGIC SYMBOL – 74ALS573B 11 1 LOGIC SYMBOL – 74ALS574A 2 3 4 5 6 7 8 9 D0 D1 D2 D3 D4 D5 D6 D7 E OE Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 19 18 17 16 15 14 13 12 VCC=Pin 20 GND=Pin 10 IEC/IEEE SYMBOL – 74ALS573B 11 1 OE 4 5 6 7 8 9 D0 D1 D2 D3 D4 D5 D6 D7 Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 19 18 17 16 15 14 13 12 SF01076 IEC/IEEE SYMBOL – 74ALS574A 1 EN1 11 EN2 EN1 C2 19 2 3 18 3 18 4 17 4 17 5 16 5 16 6 15 6 15 7 14 7 14 8 13 8 13 9 12 9 12 2 2D 1 SF01077 1991 Feb 08 CP 3 VCC=Pin 20 GND=Pin 10 SF01075 1 11 2 2D 1 19 SF01078 3 Philips Semiconductors Product specification Latch/flip-flop 74ALS573B/74ALS574A LOGIC DIAGRAM – 74ALS573B D1 3 D0 2 D E E OE D2 4 D E Q D3 5 D E Q D4 6 D E Q D5 7 D E Q D6 8 D E Q D7 9 D E Q D E Q Q 11 1 19 18 Q0 VCC = Pin 20 GND = Pin 10 17 Q1 16 Q2 15 Q3 14 Q4 13 Q5 12 Q6 Q7 SC00109 FUNCTION TABLE – 74ALS573B INPUTS H = h = L = l = NC= X = Z = ↓ = E Dn OUTPUTS REGISTER INTERNAL OE L H L L L L H H H H L ↓ l L L L ↓ h H H L L X NC NC OPERATING MODE Q0 – Q7 H L X NC Z H H Dn Dn Z Enable and read register Latch and read register Hold Disable outputs High-voltage level High state must be present one setup time before the High-to-Low enable transition Low-voltage level Low state must be present one setup time before the High-to-Low enable transition No change Don’t care High impedance “off” state High-to-Low enable transition LOGIC DIAGRAM – 74ALS574A D1 3 D0 2 D CP Q D CP Q CP OE 1991 Feb 08 D3 5 D CP Q D4 6 D CP Q D5 7 D CP Q D6 8 D CP Q D7 9 D CP Q D CP Q 11 1 19 VCC = Pin 20 GND = Pin 10 D2 4 Q0 18 Q1 17 16 Q2 Q3 4 15 Q4 14 Q5 13 Q6 12 Q7 SC00110 Philips Semiconductors Product specification Latch/flip-flop 74ALS573B/74ALS574A FUNCTION TABLE – 74ALS574A INPUTS H = h = L = l = NC= X = Z = ↑ = ↑ = INTERNAL OUTPUTS REGISTER OE CP Dn L ↑ l L L L ↑ h H H OPERATING MODE Q0 – Q7 L ↑ X NC NC H ↑ X NC Z H ↑ Dn Dn Z Latch and read register Hold Disable outputs High-voltage level High state must be present one setup time before the Low-to-High clock transition Low-voltage level Low state must be present one setup time before the Low-to-High clock transition No change Don’t care High impedance “off” state Low-to-High clock transition Not Low-to-High clock transition ABSOLUTE MAXIMUM RATINGS (Operation beyond the limit set forth in this table may impair the useful life of the device. Unless otherwise noted these limits are over the operating free-air temperature range.) PARAMETER SYMBOL RATING UNIT VCC Supply voltage –0.5 to +7.0 V VIN Input voltage –0.5 to +7.0 V IIN Input current –30 to +5 mA VOUT Voltage applied to output in High output state –0.5 to VCC V IOUT Current applied to output in Low output state 48 mA Tamb Operating free-air temperature range 0 to +70 °C Tstg Storage temperature range –65 to +150 °C RECOMMENDED OPERATING CONDITIONS LIMITS SYMBOL PARAMETER UNIT MIN NOM MAX 5.0 5.5 VCC Supply voltage 4.5 VIH High-level input voltage 2.0 VIL Low-level input voltage 0.8 V IIK Input clamp current –18 mA IOH High-level output current –2.6 mA IOL Low-level output current 24 mA +70 °C Tamb 1991 Feb 08 Operating free-air temperature range 0 5 V V Philips Semiconductors Product specification Latch/flip-flop 74ALS573B/74ALS574A DC ELECTRICAL CHARACTERISTICS (Over recommended operating free-air temperature range unless otherwise noted.) SYMBOL LIMITS TEST CONDITIONS1 PARAMETER MIN TYP2 UNIT MAX VCC = ±10%,, VIL = MAX,, VIH = MIN IOH = –0.4mA VCC – 2 IOH = MAX 2.4 VCC = MIN,, VIL = MAX,, VIH = MIN IOL = 12mA 0.25 0.40 V IOL = 24mA 0.35 0.50 V –0.73 –1.2 V VCC = MAX, VI = 7.0V 0.1 mA VCC = MAX, VI = 2.7V 20 µA 74ALS573B VCC = MAX, VI = 0.4V –0.1 mA 74ALS574A VCC = MAX, VI = 0.4V –0.2 mA VOH O High level output voltage High-level VOL O Low level output voltage Low-level VIK Input clamp voltage VCC = MIN, II = IIK II Input current at minimum input voltage IIH High-level input current IIL Low level input current Low-level V 3.2 V IOZH Off-state output current, High-level voltage applied VCC = MAX, VI = 2.7V 20 µA IOZL Off-state output current, Low-level voltage applied VCC = MAX, VI = 0.4V –20 µA Output current3 VCC = MAX, VO = 2.25V –112 mA 7 12 mA 13 21 mA 15 24 mA 10 16 mA 17 27 mA 18 28 mA IO ICCH 74ALS573B ICC ICCL VCC = MAX ICCZ Supply current (total) ICCH 74ALS574A ICCL VCC = MAX ICCZ –30 NOTES: 1. For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions for the applicable type. 2. All typical values are at VCC = 5V, Tamb = 25°C. 3. The output conditions have been chosen to produce a current that closely approximates one half of the true short-circuit output current, IOS. 1991 Feb 08 6 Philips Semiconductors Product specification Latch/flip-flop 74ALS573B/74ALS574A AC ELECTRICAL CHARACTERISTICS LIMITS SYMBOL PARAMETER TEST CONDITION Tamb = 0°C to +70°C VCC = +5.0V ± 10% CL = 50pF, RL = 500Ω MIN MAX UNIT tPLH tPHL Propagation delay Dn to Qn Waveform 3 2.0 2.0 10.0 10.0 ns tPLH tPHL Propagation delay E to Qn Waveform 2 4.0 4.0 12.0 12.0 ns tPZH tPZL Output enable time to High or Low level Waveform 6 Waveform 7 2.0 4.0 9.0 11.0 ns tPHZ tPLZ Output disable time from High or Low level Waveform 6 Waveform 7 1.0 2.0 9.0 11.0 ns fMAX Maximum clock frequency Waveform 1 45 tPLH tPHL Propagation delay CP to Qn Waveform 1 3.0 4.0 12.0 12.0 ns Waveform 6 Waveform 7 2.0 4.0 9.0 11.0 ns Waveform 6 Waveform 7 1.0 2.0 9.0 11.0 ns 74ALS573B 74ALS574A tPZH tPZL Output enable time to High or Low level tPHZ tPLZ Output disable time from High or Low level MHz AC SETUP CHARACTERISTICS LIMITS SYMBOL PARAMETER TEST CONDITION Tamb = 0°C to +70°C VCC = +5.0V ± 10% CL = 50pF, RL = 500Ω MIN tsu(H) tsu(L) Setup time, High or Low Dn to E th(H) th(L) Hold time, High or Low Dn to E tw(H) E Pulse width, High tsu(H) tsu(L) Setup time, High or Low Dn to CP th(H) th(L) Hold time, High or Low Dn to CP tw(H) tw(L) CP Pulse width, High or Low 1991 Feb 08 74ALS573B 74ALS574A 7 UNIT MAX Waveform 4 6.0 6.0 ns Waveform 4 6.0 6.0 ns Waveform 1 10.0 ns Waveform 5 6.0 6.0 ns Waveform 5 1.0 1.0 ns Waveform 5 8.0 12.0 ns Philips Semiconductors Product specification Latch/flip-flop 74ALS573B/74ALS574A AC WAVEFORMS For all waveforms, VM = 1.3V. The shaded areas indicate when the input is permitted to change for predictable output performance. 1/fmax CP V M tw(H) VM E VM VM VM VM tw(H) tPLH tw(L) tPHL VM Qn tPHL tPLH Qn VM VM VM SF00258 SF00259 Waveform 1. Propagation Delay for Clock Input to Output, Clock Pulse Widths, and Maximum Clock Frequency Dn VM Waveform 2. Propagation Delay for Enable to Output and Enable Pulse Width VM tPHL tPLH Qn VM VM SF00260 Waveform 3. Propagation Delay for Data to Output Dn VM tsu(H) E VM VM tsu(L) th(H) Dn VM th(L) tsu(H) CP VM VM VM VM VM tsu(L) th(H) VM VM th(L) VM SF00261 SF00262 Waveform 4. Data Setup Time and Hold Times OE VM Waveform 5. Data Setup Time and Hold Times OE VM tPZH tPHZ VOH -0.3V VM VM tPZL tPLZ 3.5V Qn Qn VM VM 0V VOL +0.3V SC00099 SC00100 Waveform 6. 3-State Output Enable Time to High Level and Output Disable Time from High Level Waveform 7. 3-State Output Enable Time to Low Level and Output Disable Time from Low Level 1991 Feb 08 8 Philips Semiconductors Product specification Latch/flip-flop 74ALS573B/74ALS574A TEST CIRCUIT AND WAVEFORMS VCC 7.0V VIN VOUT PULSE GENERATOR tw 90% NEGATIVE PULSE 10% RL CL RL AMP (V) VM VM D.U.T. RT 90% 10% tTHL (tff) tTLH (tr ) tTLH (tr ) tTHL (tf ) 0.3V AMP (V) 90% Test Circuit for 3-State Outputs POSITIVE PULSE VM VM 10% 10% tw SWITCH POSITION TEST SWITCH closed tPLZ, tPZL All other 90% 0.3V Input Pulse Definition open INPUT PULSE REQUIREMENTS Family Amplitude VM DEFINITIONS: RL = Load resistor; see AC electrical characteristics for value. CL = Load capacitance includes jig and probe capacitance; see AC electrical characteristics for value. RT = Termination resistance should be equal to ZOUT of pulse generators. 74ALS 3.5V 1.3V Rep.Rate tw tTLH tTHL 1MHz 500ns 2.0ns 2.0ns SC00072 1991 Feb 08 9 Philips Semiconductors Product specification Latch/flip–flop 74ALS573B/74ALS574A DIP20: plastic dual in-line package; 20 leads (300 mil) 1991 Feb 08 10 SOT146-1 Philips Semiconductors Product specification Latch/flip–flop 74ALS573B/74ALS574A SO20: plastic small outline package; 20 leads; body width 7.5 mm 1991 Feb 08 11 SOT163-1 Philips Semiconductors Product specification Latch/flip–flop 74ALS573B/74ALS574A SSOP20: plastic shrink small outline package; 20 leads; body width 5.3 mm 1991 Feb 08 12 SOT339-1 Philips Semiconductors Product specification Latch/flip–flop 74ALS573B/74ALS574A DEFINITIONS Data Sheet Identification Product Status Definition Objective Specification Formative or in Design This data sheet contains the design target or goal specifications for product development. Specifications may change in any manner without notice. Preliminary Specification Preproduction Product This data sheet contains preliminary data, and supplementary data will be published at a later date. Philips Semiconductors reserves the right to make changes at any time without notice in order to improve design and supply the best possible product. Product Specification Full Production This data sheet contains Final Specifications. Philips Semiconductors reserves the right to make changes at any time without notice, in order to improve design and supply the best possible product. Philips Semiconductors and Philips Electronics North America Corporation reserve the right to make changes, without notice, in the products, including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified. Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. LIFE SUPPORT APPLICATIONS Philips Semiconductors and Philips Electronics North America Corporation Products are not designed for use in life support appliances, devices, or systems where malfunction of a Philips Semiconductors and Philips Electronics North America Corporation Product can reasonably be expected to result in a personal injury. Philips Semiconductors and Philips Electronics North America Corporation customers using or selling Philips Semiconductors and Philips Electronics North America Corporation Products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors and Philips Electronics North America Corporation for any damages resulting from such improper use or sale. Copyright Philips Electronics North America Corporation 1997 All rights reserved. Printed in U.S.A. Philips Semiconductors 811 East Arques Avenue P.O. Box 3409 Sunnyvale, California 94088–3409 Telephone 800-234-7381 1991 Feb 08 13