74AHCU04 Hex inverter Rev. 03 — 14 November 2007 Product data sheet 1. General description The 74AHCU04 is high-speed Si-gate CMOS devices and is pin compatible with low power Schottky TTL (LSTTL). It is specified in compliance with JEDEC standard No. 7A. The 74AHCU04 is a general purpose hex inverter. Each of the six inverters is a single stage. 2. Features ■ ■ ■ ■ Low power dissipation Balanced propagation delays Inputs accepts voltages higher than VCC ESD protection: ◆ HBM JESD22-A114E: exceeds 2000 V ◆ MM JESD22-A115-A: exceeds 200 V ◆ CDM JESD22-C101C: exceeds 1000 V ■ Multiple package options ■ Specified from −40 °C to +125 °C 3. Ordering information Table 1. Ordering information Type number Package Temperature range Name Description Version 74AHCU04D −40 °C to +125 °C SO14 plastic small outline package; 14 leads; body width 3.9 mm SOT108-1 74AHCU04PW −40 °C to +125 °C TSSOP14 plastic thin shrink small outline package; 14 leads; body width 4.4 mm 74AHCU04BQ −40 °C to +125 °C DHVQFN14 plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads; 14 terminals; body 2.5 × 3 × 0.85 mm SOT402-1 SOT762-1 74AHCU04 NXP Semiconductors Hex inverter 4. Functional diagram 1 1 1A 1Y 2 3 2A 2Y 4 3 5 5 3A 3Y 6 9 4A 4Y 8 11 5A 5Y 10 13 6A 6Y 12 9 11 13 1 2 1 4 1 6 1 8 1 10 1 12 A Y mna045 mna343 mna342 Fig 1. Logic symbol Fig 2. IEC logic symbol Fig 3. Logic diagram (one inverter) 1 1A terminal 1 index area 1Y 2 14 VCC 5. Pinning information 13 6A 1A 1 14 VCC 2A 3 1Y 2 13 6A 2Y 4 04 11 5A 2A 3 12 6Y 3A 5 4 GND(1) 10 5Y 2Y 3Y 6 10 5Y 3Y 6 9 4A GND 7 8 4Y 9 8 5 4Y 3A 7 11 5A GND 04 12 6Y 4A 001aac442 Transparent top view 001aac441 (1) The die substrate is attached to the exposed die pad using conductive die attach material. It can not be used as a supply pin or input. Fig 4. Pin configuration SO14 and TSSOP14 Fig 5. Pin configuration DHVQFN14 5.1 Pin description Table 2. Pin description Symbol Pin Description 1A 1 data input 1Y 2 data output 2A 3 data input 2Y 4 data output 74AHCU04_3 Product data sheet © NXP B.V. 2007. All rights reserved. Rev. 03 — 14 November 2007 2 of 14 74AHCU04 NXP Semiconductors Hex inverter Table 2. Pin description …continued Symbol Pin Description 3A 5 data input 3Y 6 data output GND 7 ground (0 V) 4Y 8 data output 4A 9 data input 5Y 10 data output 5A 11 data input 6Y 12 data output 6A 13 data input VCC 14 supply voltage 6. Functional description Table 3. Function table H = HIGH voltage level; L = LOW voltage level Input Output nA nY L H H L 7. Limiting values Table 4. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol Parameter VCC supply voltage IIK input clamping current Conditions VI < −0.5 V [1] VI input voltage IOK output clamping current VO < −0.5 V or VO > VCC + 0.5 V −0.5 V < VO < VCC + 0.5 V Min Max Unit −0.5 +7.0 V −20 - mA −0.5 +7.0 V - ±20 mA IO output current - ±25 mA ICC supply current - 75 mA IGND ground current −75 - mA Tstg storage temperature −65 +150 °C - 500 mW total power dissipation Ptot Tamb = −40 °C to +125 °C [2] [1] The input and output voltage ratings may be exceeded if the input and output current ratings are observed. [2] For SO14 packages: above 70 °C the value of Ptot derates linearly with 8 mW/K. For TSSOP14 packages: above 60 °C the value of Ptot derates linearly with 5.5 mW/K. For DHVQFN14 packages: above 60 °C the value of Ptot derates linearly with 4.5 mW/K. 74AHCU04_3 Product data sheet © NXP B.V. 2007. All rights reserved. Rev. 03 — 14 November 2007 3 of 14 74AHCU04 NXP Semiconductors Hex inverter 8. Recommended operating conditions Table 5. Recommended operating conditions Voltages are referenced to GND (ground = 0 V). Symbol Parameter Conditions Min Typ Max Unit 2.0 5.0 5.5 V VCC supply voltage VI input voltage 0 - 5.5 V VO output voltage 0 - VCC V Tamb ambient temperature −40 +25 +125 °C ∆t/∆V input transition rise and fall rate VCC = 3.3 V ± 0.3 V - - 100 ns/V VCC = 5.0 V ± 0.5 V - - 20 ns/V 9. Static characteristics Table 6. Static characteristics Voltages are referenced to GND (ground = 0 V). Symbol VIH VIL VOH VOL Parameter HIGH-level input voltage LOW-level input voltage 25 °C Conditions −40 °C to +85 °C −40 °C to +125 °C Unit Min Typ Max Min Max Min Max VCC = 2.0 V 1.7 - - 1.7 - 1.7 - V VCC = 3.0 V 2.4 - - 2.4 - 2.4 - V VCC = 5.5 V 4.4 - - 4.4 - 4.4 - V VCC = 2.0 V - - 0.3 - 0.3 - 0.3 V VCC = 3.0 V - - 0.6 - 0.6 - 0.6 V VCC = 5.5 V - - 1.1 - 1.1 - 1.1 V HIGH-level VI = VIH or VIL output voltage IO = −50 µA; VCC = 2.0 V 1.8 2.0 - 1.8 - 1.8 - V IO = −50 µA; VCC = 3.0 V 2.7 3.0 - 2.7 - 2.7 - V IO = −50 µA; VCC = 4.5 V 4.0 4.5 - 4.0 - 4.0 - V IO = −4.0 mA; VCC = 3.0 V 2.58 - - 2.48 - 2.4 - V IO = −8.0 mA; VCC = 4.5 V 3.94 - - 3.8 - 3.7 - V LOW-level VI = VIH or VIL output voltage IO = 50 µA; VCC = 2.0 V - 0 0.2 - 0.2 - 0.2 V IO = 50 µA; VCC = 3.0 V - 0 0.3 - 0.3 - 0.3 V IO = 50 µA; VCC = 4.5 V - 0 0.5 - 0.5 - 0.5 V IO = 4.0 mA; VCC = 3.0 V - - 0.36 - 0.44 - 0.55 V IO = 8.0 mA; VCC = 4.5 V - - 0.36 - 0.44 - 0.55 V - - 0.1 - 1.0 - 2.0 µA supply current VI = VCC or GND; IO = 0 A; VCC = 5.5 V - - 2.0 - 20 - 40 µA input capacitance - 3 10 - 10 - 10 pF II input leakage current ICC CI VI = 5.5 V or GND; VCC = 0 V to 5.5 V 74AHCU04_3 Product data sheet © NXP B.V. 2007. All rights reserved. Rev. 03 — 14 November 2007 4 of 14 74AHCU04 NXP Semiconductors Hex inverter 10. Dynamic characteristics Table 7. Dynamic characteristics GND = 0 V; For test circuit see Figure 7. Symbol Parameter propagation delay tpd 25 °C Conditions nA to nY; see Figure 6 [1] VCC = 3.0 V to 3.6 V [2] CL = 15 pF CL = 50 pF CL = 15 pF CL = 50 pF power dissipation capacitance Min Typ Max Min Max Min Max - 3.0 7.1 1.0 8.5 1.0 9.0 ns - 3.4 10.6 1.0 12.0 1.0 13.5 ns - 2.4 5.5 1.0 6.5 1.0 7.0 ns - 3.5 7.0 1.0 8.0 1.0 9.0 ns - 9.1 - - - - - pF [3] VCC = 4.5 V to 5.5 V CPD −40 °C to +85 °C −40 °C to +125 °C Unit [4] CL = 50 pF; fi = 1 MHz; VI = GND to VCC [1] tpd is the same as tPLH and tPHL. [2] Typical values are measured at VCC = 3.3 V. [3] Typical values are measured at VCC = 5.0 V. [4] CPD is used to determine the dynamic power dissipation (PD in µW). PD = CPD × VCC2 × fi × N + ∑(CL × VCC2 × fo) where: fi = input frequency in MHz; fo = output frequency in MHz; CL = output load capacitance in pF; VCC = supply voltage in V; N = number of inputs switching; ∑(CL × VCC2 × fo) = sum of outputs. 11. Waveforms VI VM nA input VM VCC GND t PHL t PLH VOH VM nY output VOL PULSE GENERATOR VI VO DUT CL 50 pF RT VM mna344 VM = 0.5 × VCC; VI = GND to VCC. mna034 Test data is given in Table 7. Definitions for test circuit: CL = Load capacitance including jig and probe capacitance. RT = Termination resistance should be equal to output impedance Zo of the pulse generator. Fig 6. The input (nA) to output (nY) propagation delay times Fig 7. Load circuit for switching times 74AHCU04_3 Product data sheet © NXP B.V. 2007. All rights reserved. Rev. 03 — 14 November 2007 5 of 14 74AHCU04 NXP Semiconductors Hex inverter 12. Typical transfer characteristics mna353 2 VO VO (V) 700 ICC (µA) mna352 4 6 VO (V) ICC (mA) VO 1.5 500 3 1 300 2 2 0.5 100 1 0 4 ICC ICC 0 0 0 0.5 1 1.5 V (V) i 2 −100 0 0 1 Tamb = 25 °C. Tamb = 25 °C. Fig 8. VCC = 2.0 V; IO = 0 A Fig 9. VCC = 3.0 V; IO = 0 A mna351 8 VO (V) 2 3 Vi (V) −2 30 ICC (mA) 6 20 4 10 Rbias = 560 kΩ VCC ICC 0 2 0.47 µF VO 0 0 2 Tamb = 25 °C. 4 Vi (V) 6 −10 input VI (f = 1 kHz) output 100 µF A IO GND mna050 ∆I g fs = --------o∆V i fi = 1 kHz at VO is constant Fig 10. VCC = 5.5 V; IO = 0 A Fig 11. Test set-up for measuring forward transconductance 74AHCU04_3 Product data sheet © NXP B.V. 2007. All rights reserved. Rev. 03 — 14 November 2007 6 of 14 74AHCU04 NXP Semiconductors Hex inverter mna355 40 g fs (mA/V) 30 20 10 0 0 2 4 VCC (V) 6 Tamb = 25 °C. Fig 12. Typical forward transconductance as a function of the supply voltage 13. Application information Some applications are: • Linear amplifier (see Figure 13) • In crystal oscillator design (see Figure 14) Remark: All values given are typical unless otherwise specified. R2 R1 VCC 1 µF R2 R1 U04 U04 C1 ZL C2 out mna052 mna053 Maximum Vo(p-p) = VCC − 1.5 V centered at 0.5 × VCC. C1 = 47 pF (typical) G ol G v = – --------------------------------------R1 1 + ------- ( 1 + G ol ) R2 R1 = 1 MΩ to 10 MΩ (typical C2 = 33 pF (typical) R2 optimum value depends on the frequency and required stability against changes in VCC or average minimum ICC (ICC is typically 5 mA at VCC = 5 V and fi = 10 MHz). Gol = open loop gain Gv = voltage gain R1 ≥ 3 kΩ, R2 ≤ 1 MΩ ZL > 10 kΩ; Gol = 12 (typical) Typical unity gain bandwidth product is 5 MHz. Fig 13. Used as a linear amplifier Fig 14. Crystal oscillator configuration 74AHCU04_3 Product data sheet © NXP B.V. 2007. All rights reserved. Rev. 03 — 14 November 2007 7 of 14 74AHCU04 NXP Semiconductors Hex inverter Table 8. External components for resonator (f < 1 MHz) All values given are typical and must be used as an initial set-up. Frequency R1 R2 C1 C2 10 kHz to 15.9 kHz 22 MΩ 220 kΩ 56 pF 20 pF 16 kHz to 24.9 kHz 22 MΩ 220 kΩ 56 pF 10 pF 25 kHz to 54.9 kHz 22 MΩ 100 kΩ 56 pF 10 pF 55 kHz to 129.9 kHz 22 MΩ 100 kΩ 47 pF 5 pF 130 kHz to 199.9 kHz 22 MΩ 47 kΩ 47 pF 5 pF 200 kHz to 349.9 kHz 10 MΩ 47 kΩ 47 pF 5 pF 350 kHz to 600 kHz 10 MΩ 47 kΩ 47 pF 5 pF Table 9. Optimum value for R2 Frequency R2 Optimum for 3 kHz 2.0 kΩ minimum required ICC 8.0 kΩ minimum influence due to change in VCC 1.0 kΩ minimum required ICC 6 kHz 10 kHz 14 kHz >14 kHz 4.7 kΩ minimum influence by VCC 0.5 kΩ minimum required ICC 2.0 kΩ minimum influence by VCC 0.5 kΩ minimum required ICC 1.0 kΩ minimum influence by VCC - replace R2 by C3 with a typical value of 35 pF 74AHCU04_3 Product data sheet © NXP B.V. 2007. All rights reserved. Rev. 03 — 14 November 2007 8 of 14 74AHCU04 NXP Semiconductors Hex inverter 14. Package outline SO14: plastic small outline package; 14 leads; body width 3.9 mm SOT108-1 D E A X c y HE v M A Z 8 14 Q A2 A (A 3) A1 pin 1 index θ Lp 1 L 7 e detail X w M bp 0 2.5 5 mm scale DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (1) e HE L Lp Q v w y Z (1) mm 1.75 0.25 0.10 1.45 1.25 0.25 0.49 0.36 0.25 0.19 8.75 8.55 4.0 3.8 1.27 6.2 5.8 1.05 1.0 0.4 0.7 0.6 0.25 0.25 0.1 0.7 0.3 0.01 0.019 0.0100 0.35 0.014 0.0075 0.34 0.16 0.15 0.010 0.057 inches 0.069 0.004 0.049 0.05 0.244 0.039 0.041 0.228 0.016 0.028 0.024 0.01 0.01 0.028 0.004 0.012 θ o 8 o 0 Note 1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included. REFERENCES OUTLINE VERSION IEC JEDEC SOT108-1 076E06 MS-012 JEITA EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-19 Fig 15. Package outline SOT108-1 (SO14) 74AHCU04_3 Product data sheet © NXP B.V. 2007. All rights reserved. Rev. 03 — 14 November 2007 9 of 14 74AHCU04 NXP Semiconductors Hex inverter TSSOP14: plastic thin shrink small outline package; 14 leads; body width 4.4 mm SOT402-1 E D A X c y HE v M A Z 8 14 Q (A 3) A2 A A1 pin 1 index θ Lp L 1 7 e detail X w M bp 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (2) e HE L Lp Q v w y Z (1) θ mm 1.1 0.15 0.05 0.95 0.80 0.25 0.30 0.19 0.2 0.1 5.1 4.9 4.5 4.3 0.65 6.6 6.2 1 0.75 0.50 0.4 0.3 0.2 0.13 0.1 0.72 0.38 8 o 0 o Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT402-1 REFERENCES IEC JEDEC JEITA MO-153 EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-18 Fig 16. Package outline SOT402-1 (TSSOP14) 74AHCU04_3 Product data sheet © NXP B.V. 2007. All rights reserved. Rev. 03 — 14 November 2007 10 of 14 74AHCU04 NXP Semiconductors Hex inverter DHVQFN14: plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads; SOT762-1 14 terminals; body 2.5 x 3 x 0.85 mm A B D A A1 E c detail X terminal 1 index area terminal 1 index area C e1 e 2 6 y y1 C v M C A B w M C b L 1 7 Eh e 14 8 13 9 Dh X 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT mm A(1) max. A1 b 1 0.05 0.00 0.30 0.18 c D (1) Dh E (1) Eh 0.2 3.1 2.9 1.65 1.35 2.6 2.4 1.15 0.85 e 0.5 e1 L v w y y1 2 0.5 0.3 0.1 0.05 0.05 0.1 Note 1. Plastic or metal protrusions of 0.075 mm maximum per side are not included. REFERENCES OUTLINE VERSION IEC JEDEC JEITA SOT762-1 --- MO-241 --- EUROPEAN PROJECTION ISSUE DATE 02-10-17 03-01-27 Fig 17. Package outline SOT762-1 (DHVQFN14) 74AHCU04_3 Product data sheet © NXP B.V. 2007. All rights reserved. Rev. 03 — 14 November 2007 11 of 14 74AHCU04 NXP Semiconductors Hex inverter 15. Abbreviations Table 10. Abbreviations Acronym Description CMOS Complementary Metal Oxide Semiconductor LSTTL Low-power Schottky Transistor-Transistor Logic ESD ElectroStatic Discharge HBM Human Body Model MM Machine Model CDM Charge Device Model TTL Transistor-Transistor Logic 16. Revision history Table 11. Revision history Document ID Release date Data sheet status Change notice Supersedes 74AHCU04_3 20071114 Product data sheet - 74AHCU04_2 Modifications: • The format of this data sheet has been redesigned to comply with the new identity guidelines of NXP Semiconductors. • • • • Legal texts have been adapted to the new company name where appropriate. Section 3: DHVQFN14 package added. Section 8: derating values added for DHVQFN14 package. Section 14: outline drawing added for DHVQFN14 package. 74AHCU04_2 19990927 Product specification - 74AHCU04_1 74AHCU04_1 19990226 Product specification - - 74AHCU04_3 Product data sheet © NXP B.V. 2007. All rights reserved. Rev. 03 — 14 November 2007 12 of 14 74AHCU04 NXP Semiconductors Hex inverter 17. Legal information 17.1 Data sheet status Document status[1][2] Product status[3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification. [1] Please consult the most recently issued document before initiating or completing a design. [2] The term ‘short data sheet’ is explained in section “Definitions”. [3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com. 17.2 Definitions Draft — The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet — A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. 17.3 Disclaimers General — Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use — NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk. Applications — Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Limiting values — Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) may cause permanent damage to the device. Limiting values are stress ratings only and operation of the device at these or any other conditions above those given in the Characteristics sections of this document is not implied. Exposure to limiting values for extended periods may affect device reliability. Terms and conditions of sale — NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, including those pertaining to warranty, intellectual property rights infringement and limitation of liability, unless explicitly otherwise agreed to in writing by NXP Semiconductors. In case of any inconsistency or conflict between information in this document and such terms and conditions, the latter will prevail. No offer to sell or license — Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. 17.4 Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. 18. Contact information For additional information, please visit: http://www.nxp.com For sales office addresses, send an email to: [email protected] 74AHCU04_3 Product data sheet © NXP B.V. 2007. All rights reserved. Rev. 03 — 14 November 2007 13 of 14 74AHCU04 NXP Semiconductors Hex inverter 19. Contents 1 2 3 4 5 5.1 6 7 8 9 10 11 12 13 14 15 16 17 17.1 17.2 17.3 17.4 18 19 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Ordering information . . . . . . . . . . . . . . . . . . . . . 1 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2 Pinning information . . . . . . . . . . . . . . . . . . . . . . 2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 2 Functional description . . . . . . . . . . . . . . . . . . . 3 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 3 Recommended operating conditions. . . . . . . . 4 Static characteristics. . . . . . . . . . . . . . . . . . . . . 4 Dynamic characteristics . . . . . . . . . . . . . . . . . . 5 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Typical transfer characteristics . . . . . . . . . . . . 6 Application information. . . . . . . . . . . . . . . . . . . 7 Package outline . . . . . . . . . . . . . . . . . . . . . . . . . 9 Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Revision history . . . . . . . . . . . . . . . . . . . . . . . . 12 Legal information. . . . . . . . . . . . . . . . . . . . . . . 13 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 13 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Contact information. . . . . . . . . . . . . . . . . . . . . 13 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. © NXP B.V. 2007. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: [email protected] Date of release: 14 November 2007 Document identifier: 74AHCU04_3