PHILIPS BS208

DISCRETE SEMICONDUCTORS
DATA SHEET
BS208
P-channel enhancement mode
vertical D-MOS transistor
Product specification
File under Discrete Semiconductors, SC13b
April 1995
Philips Semiconductors
Product specification
P-channel enhancement mode vertical
D-MOS transistor
BS208
FEATURES
• Direct interface to C-MOS
• High-speed switching
handbook, halfpage
• No secondary breakdown.
1
d
2
3
DESCRIPTION
g
P-channel enhancement mode
vertical D-MOS transistor in a TO-92
envelope. Intended for use in relay,
high-speed and line transformer
drivers.
MAM149
s
Fig.1 Simplified outline and symbol.
PINNING - TO-92
PIN
DESCRIPTION
1
source
2
gate
3
drain
QUICK REFERENCE DATA
SYMBOL
PARAMETER
CONDITIONS
MIN.
−
TYP.
−
MAX.
−200
UNIT
VDS
drain-source voltage (DC)
VGSO
gate-source voltage (DC)
open drain
−
−
±20
V
 Yfs 
forward transfer admittance
ID = −200 mA; VDS = −25 V
100
200
−
mS
ID
drain current (DC)
−
−
−0.2
A
RDS(on)
drain-source on-state resistance VGS = −10 V; ID = −200 mA
−
10
14
Ω
Ptot
total power dissipation
−
−
0.83
W
April 1995
Tamb = 25 °C
2
V
Philips Semiconductors
Product specification
P-channel enhancement mode vertical
D-MOS transistor
BS208
LIMITING VALUES
In accordance with the Absolute Maximum System (IEC 134)
SYMBOL
PARAMETER
CONDITIONS
MIN.
MAX.
UNIT
−VDS
drain-source voltage
−
200
V
±VGSO
gate-source voltage
open drain
−
20
V
−ID
drain current
DC
−
−IDM
drain current
peak value
−
0.6
A
Ptot
total power dissipation
Tamb = 25 °C
−
0.83
W
Tstg
storage temperature range
Tj
junction temperature
0.2
A
−65
+150
°C
−
150
°C
THERMAL RESISTANCE
SYMBOL
PARAMETER
Rthj-a
MAX.
from junction to ambient
handbook,
150
MDA690
1
Ptot
(W)
0.8
0.6
0.4
0.2
0
0
50
100
150
200
Tamb (°C)
Fig.2 Power derating curve.
April 1995
3
UNIT
K/W
Philips Semiconductors
Product specification
P-channel enhancement mode vertical
D-MOS transistor
BS208
CHARACTERISTICS
Tj = 25 °C unless otherwise specified.
SYMBOL
PARAMETER
CONDITIONS
−V(BR)DSS
drain-source breakdown
voltage
−VGS = 0
−ID = 10 µA
−IDSS
drain-source leakage current
−IDSS
MIN.
TYP.
MAX.
UNIT
200
−
-
V
−VDS = 130 V
VGS = 0
−
−
1
µA
drain-source leakage current
−VDS = 70 V
−VGS = 0.2 V
−
−
25
µA
−IGSS
gate-source leakage current
−VGS = 20 V
VDS = 0
−
−
100
nA
−VGS(th)
gate-source threshold
voltage
VGS = VDS
−ID = 1 mA
0.8
−
RDS(on)
drain-source on-resistance
−VGS = 10 V
−ID = 200 mA
−
−
14
Ω
 Yfs 
transfer admittance
−VDS = 25 V
−ID = 200 mA
100
200
−
mS
Ciss
input capacitances
note 1
−
55
90
pF
Coss
output capacitance
note 1
−
20
30
pF
2.8
V
Crss
feedback capacitance
note 1
−
5
15
pF
ton
turn-on time
note 2
−
5
10
ns
toff
turn-off time
note 2
−
20
30
ns
Notes
1. Measured at f = 1 MHz; −VDS = 25 V; VGS = 0.
2. −VGS = 0 to 10 V; −ID = 250 mA; −VDD = 50 V.
VDD = −50 V
handbook, halfpage
handbook, halfpage
10 %
INPUT
90 %
10 %
0V
−10 V
ID
OUTPUT
50 Ω
90 %
MBB689
ton
toff
MBB690
Fig.3 Switching times test circuit.
April 1995
Fig.4 Input and output waveforms.
4
Philips Semiconductors
Product specification
P-channel enhancement mode vertical
D-MOS transistor
MDA706
−1
ID
(A)
−0.8
handbook, halfpage
ID
(A)
−0.8
−6 V
−0.6
MDA707
−1
VGS = −10 V
handbook, halfpage
BS208
−5 V
−0.6
−0.4
−0.4
−4 V
−0.2
−0.2
−3 V
0
−5
0
−10
−15
0
−20
−25
VDS (V)
Fig.5 Typical output characteristics; Tj = 25 °C.
−103
handbook, halfpage
Fig.6
MDA708
−4
−6
−8
−10
VGS (V)
Typical transfer characteristics;
VDS = −10 V; Tj = 25 °C.
MDA709
160
VGS = −10 V
ID
(mA)
−2
0
handbook, halfpage
−5 V
C
(pF)
−4 V
120
−102
80
Ciss
40
Coss
Crss
−10
0
8
Fig.7
April 1995
12
16
20
24
28
RDSon (Ω)
0
Typical on-resistance as a function of drain
current; Tj = 25 °C.
Fig.8
5
−5
−10
−15
−20
−25
VDS (V)
Typical capacitances as a function of
drain-source voltage; VGS = 0; f = 1 MHz;
Tj = 25 °C.
Philips Semiconductors
Product specification
P-channel enhancement mode vertical
D-MOS transistor
MDA710
2.5
BS208
MDA711
1.1
handbook, halfpage
handbook, halfpage
k
k
2
1
1.5
0.9
1
0.8
0.5
0
−50
Fig.9
0
50
100
Tj (°C)
0.7
−50
150
Temperature coefficient of drain-source
on-resistance;
R DS ( on ) at T j
k = ---------------------------------------------;
R DS ( on ) at 25 °C
50
100
Tj (°C)
150
Fig.10 Temperature coefficient of gate-source
threshold voltage;
V GS ( th ) at T j
k = -------------------------------------------;
V GS ( th ) at 25 °C
typical VGS(th) at 1 mA.
typical RDS(on) at 200 mA/10 V.
April 1995
0
6
Philips Semiconductors
Product specification
P-channel enhancement mode vertical
D-MOS transistor
BS208
PACKAGE OUTLINES
Plastic single-ended leaded (through hole) package; 3 leads
SOT54
c
E
d
A
L
b
1
e1
2
D
e
3
b1
L1
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
UNIT
A
b
b1
c
D
d
E
e
e1
L
L1(1)
mm
5.2
5.0
0.48
0.40
0.66
0.56
0.45
0.40
4.8
4.4
1.7
1.4
4.2
3.6
2.54
1.27
14.5
12.7
2.5
Note
1. Terminal dimensions within this zone are uncontrolled to allow for flow of plastic and terminal irregularities.
OUTLINE
VERSION
SOT54
April 1995
REFERENCES
IEC
JEDEC
EIAJ
TO-92
SC-43
7
EUROPEAN
PROJECTION
ISSUE DATE
97-02-28
Philips Semiconductors
Product specification
P-channel enhancement mode vertical
D-MOS transistor
BS208
DEFINITIONS
Data sheet status
Objective specification
This data sheet contains target or goal specifications for product development.
Preliminary specification
This data sheet contains preliminary data; supplementary data may be published later.
Product specification
This data sheet contains final product specifications.
Application information
Where application information is given, it is advisory and does not form part of the specification.
LIFE SUPPORT APPLICATIONS
These products are not designed for use in life support appliances, devices, or systems where malfunction of these
products can reasonably be expected to result in personal injury. Philips customers using or selling these products for
use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such
improper use or sale.
April 1995
8
Philips Semiconductors
Product specification
P-channel enhancement mode vertical
D-MOS transistor
NOTES
April 1995
9
BS208
Philips Semiconductors
Product specification
P-channel enhancement mode vertical
D-MOS transistor
NOTES
April 1995
10
BS208
Philips Semiconductors
Product specification
P-channel enhancement mode vertical
D-MOS transistor
NOTES
April 1995
11
BS208
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© Philips Electronics N.V. 1997
SCA54
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Printed in The Netherlands
137107/00/01/pp12
Date of release: April 1995
Document order number:
9397 750 02457