INTEGRATED CIRCUITS PCA9546 4-channel I2C switch with reset Product data sheet Supersedes data of 2002 Feb 19 2004 Sep 30 Philips Semiconductors Product data sheet 4-channel I2C switch with reset PCA9546 DESCRIPTION The PCA9546 is a quad bi-directional translating switch controlled by the I2C-bus. The SCL/SDA upstream pair fans out to four downstream pairs, or channels. Any individual SCx/SDx channel or combination of channels can be selected, determined by the contents of the programmable Control Register. An active-LOW reset input allows the PCA9546 to recover from a situation where one of the downstream I2C-buses is stuck in a LOW state. Pulling the RESET pin LOW resets the I2C state machine and causes all the channels to be deselected as does the internal power on reset function. FEATURES • 1-of-4 bi-directional translating switches • I2C interface logic; compatible with SMBus standards • Active LOW Reset Input • 3 address pins allowing up to 8 devices on the I2C-bus • Channel selection via I2C-bus, in any combination • Power–up with all switch channels deselected • Low RdsON switches • Allows voltage level translation between 1.8 V, 2.5 V, 3.3 V and The pass gates of the switches are constructed such that the VDD pin can be used to limit the maximum high voltage which will be passed by the PCA9546. This allows the use of different bus voltages on each pair, so that 1.8 V, 2.5 V, or 3.3 V parts can communicate with 5 V parts without any additional protection. External pull-up resistors pull the bus up to the desired voltage level for each channel. All I/O pins are 5 V tolerant. 5 V buses • No glitch on power-up • Supports hot insertion • Low stand-by current • Operating power supply voltage range of 2.3 V to 5.5 V • 5 V tolerant Inputs • 0 kHz to 400 kHz clock frequency • ESD protection exceeds 2000 V HBM per JESD22-A114, 150 V MM per JESD22-A115 and 1000 V per JESD22-C101 • Latchup testing is done to JESDEC Standard JESD78 which exceeds 100 mA • Packages offered: SO16, TSSOP16 ORDERING INFORMATION PACKAGES TEMPERATURE RANGE ORDER CODE DRAWING NUMBER 16-Pin Plastic SO 16-Pin Plastic TSSOP –40 °C to +85 °C PCA9546D SOT109-1 –40 °C to +85 °C PCA9546PW SOT403-1 Standard packing quantities and other packaging data are available at www.standardproducts.philips.com/packaging. 2004 Sep 30 2 Philips Semiconductors Product data sheet 4-channel I2C switch with reset PCA9546 PIN CONFIGURATION — SO, TSSOP PIN DESCRIPTION SO, TSSOP PIN NUMBER SYMBOL 1 A0 Address input 0 2 A1 Address input 1 3 RESET 12 SC3 4 SD0 Serial data 0 SD1 6 11 SD3 5 SC0 Serial clock 0 SC1 7 10 SC2 6 SD1 Serial data 1 VSS 8 SD2 7 SC1 Serial clock 1 8 VSS Supply ground 9 SD2 Serial data 2 10 SC2 Serial clock 2 11 SD3 Serial data 3 12 SC3 Serial clock 3 A0 1 16 VDD 2 15 SDA A1 RESET 3 SD0 4 SC0 5 14 SCL 13 A2 9 SW00913 Figure 1. Pin configuration — SO, TSSOP 2004 Sep 30 3 FUNCTION Active LOW reset input 13 A2 Address input 2 14 SCL Serial clock line 15 SDA Serial data line 16 VDD Supply voltage Philips Semiconductors Product data sheet 4-channel I2C switch with reset PCA9546 BLOCK DIAGRAM PCA9546 SC0 SC1 SC2 SC3 SD0 SD1 SD2 SD3 SWITCH CONTROL LOGIC VSS VDD RESET RESET CIRCUIT A0 SCL SDA INPUT FILTER I2C-BUS CONTROL A1 A2 SW00914 Figure 2. Block diagram 2004 Sep 30 4 Philips Semiconductors Product data sheet 4-channel I2C switch with reset PCA9546 DEVICE ADDRESSING CONTROL REGISTER DEFINITION Following a START condition the bus master must output the address of the slave it is accessing. The address of the PCA9546 is shown in Figure 3. To conserve power, no internal pull-up resistors are incorporated on the hardware selectable address pins and they must be pulled HIGH or LOW. One or several SCx/SDx downstream pair, or channel, is selected by the contents of the control register. This register is written after the PCA9546 has been addressed. The 2 LSBs of the control byte are used to determine which channel is to be selected. When a channel is selected, the channel will become active after a stop condition has been placed on the I2C-bus. This ensures that all SCx/SDx lines will be in a HIGH state when the channel is made active, so that no false conditions are generated at the time of connection. 1 1 1 0 FIXED A2 A1 A0 R/W HARDWARE SELECTABLE Table 1. Control Register; Write — Channel Selection/ Read — Channel Status SW00915 Figure 3. Slave address D7 The last bit of the slave address defines the operation to be performed. When set to logic 1, a read is selected while a logic 0 selects a write operation. X D6 X D5 X D4 X B3 X B2 X CONTROL REGISTER X X X X X X 1 Channel 0 enabled 5 4 3 2 1 0 X X B3 B2 B1 B0 X 0 X X 0 X X X X X X X X 1 0 X CHANNEL CHANNEL CHANNEL CHANNEL 0 1 2 3 0 X 0 X 0 X 0 SW01026 X X COMMAND Channel 0 disabled 1 CHANNEL SELECTION BITS (READ/WRITE) 6 B0 0 Following the successful acknowledgement of the slave address, the bus master will send a byte to the PCA9546, which will be stored in the control register. If multiple bytes are received by the PCA9546, it will save the last byte received. This register can be written and read via the I2C-bus. 7 B1 X Channel 1 disabled Channel 1 enabled Channel 2 disabled Channel 2 enabled Channel 3 disabled 1 Channel 3 enabled 0 No channel selected; power-up/reset default state 0 0 0 NOTE: Several channels can be enabled at the same time. Ex: B3 = 0, B2 = 1, B1 = 1, B0 = 0, means that channel 0 and 3 are disabled and channel 1 and 2 are enabled. Care should be taken not to exceed the maximum bus capacity. Figure 4. Control register RESET INPUT The RESET input is an active-LOW signal which may be used to recover from a bus fault condition. By asserting this signal LOW for a minimum of tWL, the PCA9546 will reset its registers and I2C state machine and will deselect all channels. The RESET input must be connected to VDD through a pull-up resistor. POWER-ON RESET When power is applied to VDD, an internal Power On Reset holds the PCA9546 in a reset state until VDD has reached VPOR. At this point, the reset condition is released and the PCA9546 registers and I2C state machine are initialized to their default states, all zeroes causing all the channels to be deselected. 2004 Sep 30 5 Philips Semiconductors Product data sheet 4-channel I2C switch with reset PCA9546 Figure 5 shows the voltage characteristics of the pass gate transistors (note that the PCA9546 is only tested at the points specified in the DC Characteristics section of this datasheet). In order for the PCA9546 to act as a voltage translator, the Vpass voltage should be equal to, or lower than the lowest bus voltage. For example, if the main bus was running at 5 V, and the downstream buses were 3.3 V and 2.7 V, then Vpass should be equal to or below 2.7 V to effectively clamp the downstream bus voltages. Looking at Figure 5, we see that Vpass (max.) will be at 2.7 V when the PCA9546 supply voltage is 3.5 V or lower so the PCA9546 supply voltage could be set to 3.3 V. Pull-up resistors can then be used to bring the bus voltages to their appropriate levels (see Figure 12). VOLTAGE TRANSLATION The pass gate transistors of the PCA9546 are constructed such that the VDD voltage can be used to limit the maximum voltage that will be passed from one I2C-bus to another. Vpass vs. VDD 5.0 4.5 MAXIMUM 4.0 TYPICAL 3.5 More Information can be found in Application Note AN262 PCA954X family of I 2C/SMBus multiplexers and switches. Vpass 3.0 2.5 2.0 MINIMUM 1.5 1.0 2.0 2.5 3.0 3.5 4.0 4.5 VDD 5.0 5.5 SW00820 Figure 5. Vpass voltage vs. VDD 2004 Sep 30 6 Philips Semiconductors Product data sheet 4-channel I2C switch with reset PCA9546 CHARACTERISTICS OF THE I2C-BUS The I2C-bus is for 2-way, 2-line communication between different ICs or modules. The two lines are a serial data line (SDA) and a serial clock line (SCL). Both lines must be connected to a positive supply via a pull-up resistor when connected to the output stages of a device. Data transfer may be initiated only when the bus is not busy. Start and stop conditions Both data and clock lines remain HIGH when the bus is not busy. A HIGH-to-LOW transition of the data line, while the clock is HIGH is defined as the start condition (S). A LOW-to-HIGH transition of the data line while the clock is HIGH is defined as the stop condition (P) (see Figure 7). Bit transfer System configuration One data bit is transferred during each clock pulse. The data on the SDA line must remain stable during the HIGH period of the clock pulse as changes in the data line at this time will be interpreted as control signals (see Figure 6). A device generating a message is a ‘transmitter’, a device receiving is the ‘receiver’. The device that controls the message is the ‘master’ and the devices which are controlled by the master are the ‘slaves’ (see Figure 8). SDA SCL data line stable; data valid change of data allowed SW00363 Figure 6. Bit transfer SDA SDA SCL SCL S P START condition STOP condition SW00365 Figure 7. Definition of start and stop conditions SDA SCL MASTER TRANSMITTER/ RECEIVER SLAVE RECEIVER SLAVE TRANSMITTER/ RECEIVER MASTER TRANSMITTER MASTER TRANSMITTER/ RECEIVER I2C MULTIPLEXER SLAVE SW00366 Figure 8. System configuration 2004 Sep 30 7 Philips Semiconductors Product data sheet 4-channel I2C switch with reset PCA9546 Acknowledge The number of data bytes transferred between the start and the stop conditions from transmitter to receiver is not limited. Each byte of eight bits is followed by one acknowledge bit. The acknowledge bit is a HIGH level put on the bus by the transmitter whereas the master generates an extra acknowledge related clock pulse. A slave receiver which is addressed must generate an acknowledge after the reception of each byte. Also a master must generate an acknowledge after the reception of each byte that has been clocked out of the slave transmitter. The device that acknowledges has to pull down the SDA line during the acknowledge clock pulse, so that the SDA line is stable LOW during the HIGH period of the acknowledge related clock pulse, set-up and hold times must be taken into account. A master receiver must signal an end of data to the transmitter by not generating an acknowledge on the last byte that has been clocked out of the slave. In this event, the transmitter must leave the data line HIGH to enable the master to generate a stop condition. DATA OUTPUT BY TRANSMITTER not acknowledge DATA OUTPUT BY RECEIVER acknowledge SCL FROM MASTER 1 2 8 9 S clock pulse for acknowledgement START condition SW00368 Figure 9. Acknowledgement on the SLAVE ADDRESS SDA 1 S 1 1 0 A2 A1 I2C-bus CONTROL REGISTER A0 start condition 0 X A R/W X X B3 X B2 acknowledge from slave B1 A B0 P acknowledge from slave SW00917 Figure 10. WRITE control register SLAVE ADDRESS SDA S 1 1 start condition 1 0 A2 A1 CONTROL REGISTER A0 1 R/W X A X X X B3 acknowledge from slave B2 last byte B1 B0 NA no acknowledge from master P stop condition SW00918 Figure 11. READ control register 2004 Sep 30 8 Philips Semiconductors Product data sheet 4-channel I2C switch with reset PCA9546 TYPICAL APPLICATION VDD = 2.7 – 5.5 V VDD = 3.3 V V = 2.7 – 5.5 V SDA SDA SD0 SCL SCL SC0 CHANNEL 0 V = 2.7 – 5.5 V RESET I2C/SMBus MASTER SD1 CHANNEL 1 SC1 V = 2.7 – 5.5 V SD2 CHANNEL 2 SC2 V = 2.7 – 5.5 V A2 A1 SD3 A0 CHANNEL 3 SC3 VSS PCA9546 SW00919 Figure 12. Typical application 2004 Sep 30 9 Philips Semiconductors Product data sheet 4-channel I2C switch with reset PCA9546 ABSOLUTE MAXIMUM RATINGS1, 2 In accordance with the Absolute Maximum Rating System (IEC 134).Voltages are referenced to GND (ground = 0 V). RATING UNIT DC supply voltage –0.5 to +7.0 V VI DC input voltage –0.5 to +7.0 V II DC input current ±20 mA SYMBOL VDD PARAMETER CONDITIONS IO DC output current ±25 mA IDD Supply current ±100 mA ISS Supply current ±100 mA Ptot total power dissipation 400 mW Tstg Storage temperature range –60 to +150 °C Tamb Operating ambient temperature –40 to +85 °C NOTES: 1. Stresses beyond those listed may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. 2. The performance capability of a high-performance integrated circuit in conjunction with its thermal environment can create junction temperatures which are detrimental to reliability. The maximum junction temperature of this integrated circuit should not exceed 150 °C. DC CHARACTERISTICS VDD = 2.3 V to 3.6 V; VSS = 0 V; Tamb = –40 °C to +85 °C; unless otherwise specified. (See page 11 for VDD = 3.6 V to 5.5 V) SYMBOL PARAMETER TEST CONDITIONS LIMITS MIN TYP MAX UNIT Supply VDD Supply voltage IDD Supply current Istb Standby current VPOR Power-on reset voltage 2.3 — 3.6 V Operating mode; VDD = 3.6 V; no load; VI = VDD or VSS; fSCL = 100 kHz — 40 100 µA Standby mode; VDD = 3.6 V; no load; VI = VDD or VSS — 20 100 µA no load; VI = VDD or VSS — 1.6 2.1 V Input SCL; input/output SDA VIL LOW-level input voltage –0.5 — 0.3VDD V VIH HIGH-level input voltage 0.7VDD — 6 V VOL = 0.4 V 3 — — VOL = 0.6 V 6 — — VI = VDD or VSS –1 — +1 µA VI = VSS — 12 13 pF V IO OL LOW level output current LOW-level IL Leakage current Ci Input capacitance mA Select inputs A0 to A2 / RESET VIL LOW-level input voltage –0.5 — +0.3VDD VIH HIGH-level input voltage 0.7VDD — VDD + 0.5 V ILI Input leakage current pin at VDD or VSS –1 — +1 µA Ci Input capacitance VI = VSS — 1.6 3 pF VCC = 3.67 V; VO = 0.4 V; IO = 15 mA 5 20 30 VCC = 2.3 V to 2.7 V; VO = 0.4V; IO = 10 mA 7 26 55 Pass Gate RON O VPass IL Cio 2004 Sep 30 Switch resistance Switch output voltage Leakage current Input/output capacitance Ω Vswin = VDD = 3.3 V; Iswout = –100 µA — 2.2 — Vswin = VDD = 3.0 V to 3.6 V; Iswout = –100 µA 1.6 — 2.8 Vswin = VDD = 2.5 V; Iswout = –100 µA — 1.5 — Vswin = VDD = 2.3 V to 2.7 V; Iswout = –100 µA 1.1 — 2.0 VI = VDD or VSS –1 — +1 µA VI = VSS — 3 5 pF 10 V Philips Semiconductors Product data sheet 4-channel I2C switch with reset PCA9546 DC CHARACTERISTICS VDD = 3.6 V to 5.5 V; VSS = 0 V; Tamb = –40 °C to +85 °C; unless otherwise specified. (See page 10 for VDD = 2.3 V to 3.6 V) SYMBOL PARAMETER TEST CONDITIONS LIMITS MIN TYP MAX UNIT Supply VDD Supply voltage IDD Supply current Istb Standby current VPOR Power-on reset voltage 3.6 — 5.5 V Operating mode; VDD = 5.5 V; no load; VI = VDD or VSS; fSCL = 100 kHz — 570 600 µA Standby mode; VDD = 5.5 V; no load; VI = VDD or VSS — 250 300 µA no load; VI = VDD or VSS — 1.7 2.1 V V Input SCL; input/output SDA VIL LOW-level input voltage –0.5 — 0.3VDD VIH HIGH-level input voltage 0.7VDD — 6 V 3 — — mA VOL = 0.4 V IOL O LOW level output current LOW-level VOL = 0.6 V 6 — — mA IIL LOW-level input current VI = VSS –10 — +10 µA IIH HIGH-level input current VI = VDD — — 100 µA Ci Input capacitance VI = VSS — 12 13 pF V Select inputs A0 to A2 / RESET VIL LOW-level input voltage –0.5 — +0.3VDD VIH HIGH-level input voltage 0.7VDD — VDD + 0.5 V ILI Input leakage current pin at VDD or VSS –1 — +50 µA Ci Input capacitance VI = VSS — 2 3 pF RON Switch resistance VCC = 4.5 V to 5.5 V; VO = 0.4 V; IO = 15 mA 4 11 24 Ω VPass Switch output voltage V Pass Gate IL Cio 2004 Sep 30 Leakage current Input/output capacitance Vswin = VDD = 5.0 V; Iswout = –100 µA — 3.5 — Vswin = VDD = 4.5 V to 5.5 V; Iswout = –100 µA 2.6 — 4.5 V VI = VDD or VSS –10 — +100 µA VI = VSS — 3 5 pF 11 Philips Semiconductors Product data sheet 4-channel I2C switch with reset PCA9546 AC CHARACTERISTICS SYMBOL STANDARD-MODE I2C-BUS PARAMETER FAST-MODE I2C-BUS UNIT MIN MAX MIN MAX Propagation delay from SDA to SDn or SCL to SCn — 0.31 — 0.31 ns fSCL SCL clock frequency 0 100 0 400 kHz tBUF Bus free time between a STOP and START condition 4.7 — 1.3 — µs Hold time (repeated) START condition After this period, the first clock pulse is generated 4.0 — 0.6 — µs tLOW LOW period of the SCL clock 4.7 — 1.3 — µs tHIGH HIGH period of the SCL clock 4.0 — 0.6 — µs tpd tHD;STA tSU;STA Set-up time for a repeated START condition 4.7 — 0.6 — µs tSU;STO Set-up time for STOP condition 4.0 — 0.6 — µs tHD;DAT Data hold time 02 3.45 02 0.9 µs tSU;DAT Data set-up time ns 250 — 100 — tR Rise time of both SDA and SCL signals — 1000 20 + 0.1Cb3 300 ns tF Fall time of both SDA and SCL signals — 300 20 + 0.1Cb3 300 µs Cb Capacitive load for each bus line — 400 — 400 µs tSP Pulse width of spikes which must be suppressed by the input filter — 50 — 50 ns tVD:DATL Data valid (HL) — 1 — 1 µs tVD:DATH Data valid (LH) — 0.6 — 0.6 µs tVD:ACK Data valid Acknowledge — 1 — 1 µs RESET tWL(rst) trst Pulse width low reset Reset time (SDA clear) tREC:STA Recovery to Start 4 — 4 — ns 500 — 500 — ns 0 — 0 — ns NOTES: 1. Pass gate propagation delay is calculated from the 20 Ω typical RON and the 15 pF load capacitance. 2. A device must internally provide a hold time of at least 300 ns for the SDA signal (referred to the VIH(min) of the SCL signal) in order to bridge the undefined region of the falling edge of SCL. 3. Cb = total capacitance of one bus line in pF. SDA tBUF tLOW tR tF tHD;STA tSP SCL tHD;STA P S tSU;STA tHD;DAT tHIGH tSU;DAT Sr tSU;STO P SU00645 Figure 13. Definition of timing on the 2004 Sep 30 12 I2C-bus Philips Semiconductors Product data sheet 4-channel I2C switch with reset PCA9546 SO16: plastic small outline package; 16 leads; body width 3.9 mm 2004 Sep 30 13 SOT109-1 Philips Semiconductors Product data sheet 4-channel I2C switch with reset PCA9546 TSSOP16: plastic thin shrink small outline package; 16 leads; body width 4.4 mm 2004 Sep 30 14 SOT403-1 Philips Semiconductors Product data sheet 4-channel I2C switch with reset PCA9546 HVQFN16: plastic thermal enhanced very thin quad flat package; no leads; 16 terminals; body 4 x 4 x 0.85 mm 2004 Sep 30 15 SOT629-1 Philips Semiconductors Product data sheet 4-channel I2C switch with reset PCA9546 REVISION HISTORY Rev Date Description _2 20040930 Product data sheet (9397 750 14123). Supersedes data of 2002 Feb 19 (9397 750 09459). Modifications: • Table 1, “Control register; Write—Channel Selection / Read—Channel Status”: add ‘No channel selected; power-up/reset default state’ row to bottom of table. _1 2004 Sep 30 20020219 Product data (9397 750 09459). ECN 853-2317 27757 of 19 February 2002. 16 Philips Semiconductors Product data sheet 4-channel I2C switch with reset PCA9546 Purchase of Philips I2C components conveys a license under the Philips’ I2C patent to use the components in the I2C system provided the system conforms to the I2C specifications defined by Philips. This specification can be ordered using the code 9398 393 40011. Data sheet status Level Data sheet status [1] Product status [2] [3] Definitions I Objective data sheet Development This data sheet contains data from the objective specification for product development. Philips Semiconductors reserves the right to change the specification in any manner without notice. II Preliminary data sheet Qualification This data sheet contains data from the preliminary specification. Supplementary data will be published at a later date. Philips Semiconductors reserves the right to change the specification without notice, in order to improve the design and supply the best possible product. III Product data sheet Production This data sheet contains data from the product specification. Philips Semiconductors reserves the right to make changes at any time in order to improve the design, manufacturing and supply. Relevant changes will be communicated via a Customer Product/Process Change Notification (CPCN). [1] Please consult the most recently issued data sheet before initiating or completing a design. [2] The product status of the device(s) described in this data sheet may have changed since this data sheet was published. The latest information is available on the Internet at URL http://www.semiconductors.philips.com. [3] For data sheets describing multiple type numbers, the highest-level product status determines the data sheet status. Definitions Short-form specification — The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook. Limiting values definition — Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 60134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information — Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Disclaimers Life support — These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application. Right to make changes — Philips Semiconductors reserves the right to make changes in the products—including circuits, standard cells, and/or software—described or contained herein in order to improve design and/or performance. When the product is in full production (status ‘Production’), relevant changes will be communicated via a Customer Product/Process Change Notification (CPCN). Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified. Koninklijke Philips Electronics N.V. 2004 All rights reserved. Published in the U.S.A. Contact information For additional information please visit http://www.semiconductors.philips.com. Fax: +31 40 27 24825 Date of release: 09-04 For sales offices addresses send e-mail to: [email protected]. Document number: 2004 Sep 30 17 9397 750 14123