INTEGRATED CIRCUITS FBL2031 9-bit BTL 3.3V latched/registered/pass-thru Futurebus+ transceiver Product specification Supersedes data of 1998 Sep 04 2000 Apr 18 Philips Semiconductors Product specification 9-bit BTL 3.3V latched/registered/pass-thru Futurebus+ transceiver FBL2031 • Glitch-free power up/power down operation • Low ICC current • Tight output skew • Supports live insertion • Pins for the optional JTAG boundary scan function are provided • High density packaging in plastic Quad Flatpack • 5V compatible I/O on A-port FEATURES • Latched, registered or straight through in either A to B or B to A path • Drives heavily loaded backplanes with equivalent load impedances down to 10Ω. • High drive 100mA BTL open collector drivers on B-port • Allows incident wave switching in heavily loaded backplane buses • Reduced BTL voltage swing produces less noise and reduces power consumption • Built-in precision band-gap reference provides accurate receiver thresholds and improved noise immunity DESCRIPTION • Compatible with IEEE Futurebus+ or proprietary BTL backplanes • Each BTL driver has a dedicated Bus GND for a signal return • Controlled output ramp and multiple GND pins minimize ground The FBL2031 is a 9-bit latched/registered transceiver featuring a latched, registered or pass-thru mode in either the A-to-B or B-to-A direction. The FBL2031 is intended to provide the electrical interface to a high performance wired-OR bus. bounce QUICK REFERENCE DATA SYMBOL TYPICAL UNIT tPLH tPHL Propagation delay An to Bn 2.7 ns tPLH tPHL Propagation delay Bn to An 4.4 4.2 ns CO Output capacitance (B0 – Bn only) IOL Output current (B0 – Bn only) ICC PARAMETER Supply current 6 pF 100 mA AIn to Bn (outputs Low or High) 11 Bn to AOn (outputs Low) 22 Bn to AOn (outputs High) 18 mA ORDERING INFORMATION PACKAGE VCC = 3.3V±10%; Tamb = –40°C to +85°C DWG No. 52-pin Plastic Quad Flat Pack (PQFP) FBL2031BB SOT379-1 2000 Apr 18 2 853-2118 23499 Philips Semiconductors Product specification 9-bit BTL 3.3V latched/registered/pass-thru Futurebus+ transceiver FBL2031 B0 BUS GND TMS (option) VCC TCK (option) OEB1 OEA OEB0 BIAS V A0 VCC A1 LOGIC GND PIN CONFIGURATION 52 51 50 49 48 47 46 45 44 43 42 41 40 LOGIC GND 1 39 BUS GND A2 2 38 B1 LOGIC GND 3 37 BUS GND 36 B2 A3 4 LOGIC GND 5 9-Bit latched/registered transceiver 35 BUS GND A4 6 FBL2031 34 B3 LOGIC GND 7 33 BUS GND A5 8 32 B4 LOGIC GND 9 31 BUS GND A6 10 30 B5 LOGIC GND 11 29 BUS GND A7 12 28 B6 LOGIC GND 13 27 BUS GND 52-lead PQFP B7 B8 BUS GND VCC TDI (option) TDO (option) SEL0 LCAB BG GND LCBA 16 17 18 19 20 21 22 23 24 25 26 BG VCC A8 SEL1 14 15 SG00087 PIN DESCRIPTION SYMBOL PIN NUMBER TYPE NAME AND FUNCTION A0 – A8 50, 52, 2, 4, 6, 8, 10, 12, 14 I/O BiCMOS data inputs/3-State outputs (TTL) B0 – B8 40, 38, 36, 34, 32, 30, 28, 26, 24 I/O Data inputs/Open Collector outputs, High current drive (BTL) OEB0 46 Input Enables the B outputs when High OEB1 45 Input Enables the B outputs when Low OEA 47 Input Enables the A outputs when High BUS GND 25, 27, 29, 31, 33, 35, 37, 39, 41 GND Bus ground (0V) LOGIC GND 51, 1, 3, 5, 7, 9, 11, 13 GND Logic ground (0V) VCC 23, 43, 49 Power Positive supply voltage BIAS V 48 Power Live insertion pre-bias pin BG VCC 17 Power Band Gap threshold voltage reference BG GND 19 GND Band Gap threshold voltage reference ground SEL0 20 Input Mode select SEL1 15 Input Mode select LCAB 18 Input A to B clock/latch enable (transparent latch when Low) LCBA 16 Input B to A clock/latch enable (transparent latch when Low) TMS 42 Input Test Mode Select (optional, if not implemented then no connect) TCK 44 Input Test Clock (optional, if not implemented then no connect) TDI 22 Input Test Data In (optional, if not implemented then no connect) TDO 21 Output 2000 Apr 18 Test Data Out (optional, if not implemented then shorted to TDI) 3 Philips Semiconductors Product specification 9-bit BTL 3.3V latched/registered/pass-thru Futurebus+ transceiver FBL2031 drivers. BTL also provides incident wave switching, a necessity for high performance backplanes. DESCRIPTION The TTL-level side (A port) has a common I/O. The common I/O, open collector B port operates at BTL signal levels. The logic element for data flow in each direction is controlled by two mode select inputs (SEL0 and SEL1). A “00” configures latches in both directions. A “10” configures thru mode in both directions. A “01” configures register mode in both directions. A “11” configures register mode in the A-to-B direction and latch mode in the B-to-A direction. Output clamps are provided on the BTL outputs to further reduce switching noise. The “VOH” clamp reduces inductive ringing effects during a Low-to-High transition. The “VOH” clamp is always active. The other clamp, the “trapped reflection” clamp, clamps out ringing below the BTL 0.5V VOL level. This clamp remains active for approximately 100ns after a High-to-Low transition. The 3-State A port is enabled by asserting a High level on OEA. The B port has two output enables, OEB0 and OEB1. Only when OEB0 is High and OEB1 is Low is the output enabled. To support live insertion, OEB0 is held Low during power on/off cycles to insure glitch- free B port drivers. Proper bias for B port drivers during live insertion is provided by the BIAS V pin when at a 3.3V level while VCC is Low. The BIAS V pin is a low current input which will reverse-bias the BTL driver series Schottky diode, and also bias the B port output pins to a voltage between 1.62V and 2.1V. This bias function is in accordance with IEEE BTL Standard 1194.1. If live insertion is not a requirement, the BIAS V pin should be tied to a VCC pin. When either OEB0 is Low or OEB1 is High, the B port is inactive and is pulled to the level of the pull-up voltage. New data can be entered in the register and latched modes or can be retained while the associated outputs are in 3-State (A port) or inactive (B port). The LOGIC GND and BUS GND pins are isolated inside the package to minimize noise coupling between the BTL and TTL sides. These pins should be tied to a common ground external to the package. The B-port drivers are Low-capacitance open collectors with controlled ramp and are designed to sink 100mA. Precision band gap references on the B-port insure very good noise margins by limiting the switching threshold to a narrow region centered at 1.55V. Each BTL driver has an associated BUS GND pin that acts as a signal return path and these BUS GND pins are internally isolated from each other. In the event of a ground return fault, a “hard” signal failure occurs instead of a pattern dependent error that may be infrequent and impossible to troubleshoot. When configured in the buffer mode, the inverse of the input data appears at the output port. In the register mode, data is stored on the rising edge of the appropriate clock input (LCAB or LCBA). In the latch mode, clock pins serve as transparent-Low latch enables. Regardless of the mode, data is inverted from input to output. The B-port interfaces to “Backplane Transceiver Logic” (see the IEEE 1194.1 BTL standard). BTL features low power consumption by reducing voltage swing (1V p-p, between 1V and 2V) and reduced capacitive loading by placing an internal series diode on the As with any high power device, thermal considerations are critical. It is recommended that airflow (300Ifpm) and/or thermal mounting be used to ensure proper junction temperature. PACKAGE THERMAL CHARACTERISTICS PARAMETER 2000 Apr 18 CONDITION 52-PIN PLASTIC QFP θja Still air 80°C/W θja 300 Linear feet per minute air flow 58°C/W θjc Thermally mounted on one side to heat sink 20°C/W 4 Philips Semiconductors Product specification 9-bit BTL 3.3V latched/registered/pass-thru Futurebus+ transceiver FBL2031 FUNCTION TABLE MODE An to Bn thru mode An to Bn transparent latch An to Bn latch and read Bn outputs latched and read (preconditioned latch) An to Bn register Bn to An thru mode Bn to An transparent latch Bn to An latch and read An outputs latched and read (preconditioned latch) Bn to An register Disable Bn outputs Disable An outputs INPUTS OUTPUTS An Bn* OEB0 OEB1 OEA LCAB LCBA SEL0 SEL1 An Bn L — H L L X X H L input H** H — H L L X X H L input L L — H L L L X L L input H** H — H L L L X L L input L l — H L L ↑ X L L input H** h — H L L ↑ X L L input L X — H L X H X L L X latched data l — H L L ↑ X X H input H** h — H L L ↑ X X H input L — L Disable H X X H L H input — H Disable H X X H L L input — L Disable H X L L L H input — H Disable H X L L L L input — L Disable H X L H H H input — H Disable H X L H H L input — l Disable H X ↑ L L H input — h Disable H X ↑ L L L input — l Disable H X ↑ H H H input — h Disable H X ↑ H H L input X — X X X H X H L L latched data — X X X H X H H H latched data X — l Disable H X ↑ L H H input Disable — h H X ↑ L H L input X X L X X X X X X X H** X X X H X X X X X X H** X X X X L X X X X Z X FUNCTION SELECT TABLE MODE SELECTED SEL0 Thru mode H L Register mode (An to Bn) X H Latch mode (An to Bn) L L Register mode (Bn to An) L H L L H H Latch mode (Bn to An) NOTES: H = High voltage level L = Low voltage level l = Low voltage level one set-up time prior to the Low-to-High LCXX transition h = High voltage level one set-up time prior to the Low-to-High LCXX transition X = Don’t care 2000 Apr 18 SEL1 Z — ↑ H** Bn* High-impedance (OFF) state Input not externally driven Low-to-High transition Goes to level of pull-up voltage Precaution should be taken to ensure B inputs do not float. If they do, they are equal to Low state. Disable = OEB0 is Low or OEB1 is High. 5 = = = = = Philips Semiconductors Product specification 9-bit BTL 3.3V latched/registered/pass-thru Futurebus+ transceiver FBL2031 LOGIC DIAGRAM OEB0 OEB1 OEA 46 45 47 D Q E D A8 14 Q MUX 24 MUX Q Q A ⇐ B D DD E Q Q D Clk E D A7 12 Q 26 MUX A ⇒ B Clk 30 MUX Q A ⇐ B 8 Q D 2 D E 6 4 Q 32 D Clk 36 D Q 38 B1 MUX A ⇒ B 52 MUX Q A ⇐ B D D E Q Q D Clk E D Q 40 MUX Clk A0 B0 A ⇒ B 50 MUX Q D Q D A ⇐ B 2000 Apr 18 BTL 34 E Clk A1 B7 28 10 TTL B8 A ⇒ B Clk LCAB 18 SEL0 20 Decode SEL1 15 In LCBA 16 TMS TCK TDI TDO 42 44 22 21 E Clk Out LOGIC GND BUS GND BIAS V VCC BG VCC BG GND (JTAG Boundary Scan pins) 6 = = = = = = 1, 3, 5, 7, 9, 11, 13, 51 25, 27, 29, 31, 33, 35, 37, 39, 41 48 23, 43, 49 17 19 SG00061 Philips Semiconductors Product specification 9-bit BTL 3.3V latched/registered/pass-thru Futurebus+ transceiver FBL2031 ABSOLUTE MAXIMUM RATINGS Operation beyond the limits set forth in this table may impair the useful life of the device. Unless otherwise noted these limits are over the operating free-air temperature range. SYMBOL PARAMETER VCC Supply voltage VIN Input voltage IIN Input current VOUT RATING UNIT –0.5 to +4.6 V AI0 – AI6, OEB0, OEBn, OEAn –0.5 to +7.0 V B0 – B8 –0.5 to +3.5 VIN t 0 –50 Voltage applied to output in High output state IOUT O Current applied to output in Low output state/High output state TSTG Storage temperature AO0 – AO8 B0 – B8 –0.5 to +7.0 V 64, –64 mA 200 –65 to +150 °C COMMERCIAL LIMITS VCC = 3.3V±10%; Tamb = –40 to +85°C UNIT RECOMMENDED OPERATING CONDITIONS SYMBOL PARAMETER VCC Supply voltage VIH High level input voltage High-level VIL Low level input voltage Low-level IIK Input clamp current IOH High-level output current IOL O Low level output current Low-level COB Output capacitance on B port Tamb Operating free-air temperature range MIN TYP MAX 3.0 3.3 3.6 Except B0–B8 2.0 B0 – B8 1.62 V V 1.55 Except B0–B8 0.8 B0 – B8 1.47 V –18 mA AO0 – AO8 –32 mA AO0 – AO8 +32 mA B0 – B8 100 6 0 7 pF +70 °C LIVE INSERTION SPECIFICATIONS SYMBOL LIMITS PARAMETER Voltage difference between the Bias voltage and VCC after the PCB is plugged in. TYP MAX – – 0.5 V 1.2 mA VBIASV Bias pin voltage IBIASV S Bias pin ((IBIASV) input DC current VCC = 0 V, Bias V = 3.6V VBn Bus voltage during prebias B0 – B8 = 0V, Bias V = 3.3V ILM Fall current during prebias B0 – B8 = 2V, Bias V = 1.3 to 2.5V IHM Rise current during prebias B0 – B8 = 1V, Bias V = 3 to 3.6V IBnPEAK Peak bus current during insertion VCC = 0 to 3.3V, B0 – B8 = 0 to 2.0V, Bias V = 2.7 to 3.6V, OEB0 = 0.8V, tr = 2ns 10 IOL O OFF Power up current VCC = 0 to 3.3V, OEB0 = 0.8V 100 VCC = 0 to 1.2V, OEB0 = 0 to 5V 100 tGR 2000 Apr 18 Input glitch rejection VCC = 3.3V, Bias V = 3.6V VCC = 3.3V 1.62 10 µA 2.1 V 1 µA µA –1 1.0 7 UNIT MIN 1.35 mA µA ns Philips Semiconductors Product specification 9-bit BTL 3.3V latched/registered/pass-thru Futurebus+ transceiver FBL2031 DC ELECTRICAL CHARACTERISTICS Over recommended operating free-air temperature range unless otherwise noted. SYMBOL PARAMETER IOH High level output current B0 – B8 IOFF O Power off output current Power-off B0 – B8 VOH High-level Hi hl l output t t voltage AO0 – AO83 TEST CONDITIONS1 VOL O VIK II IIH Low level output voltage Low-level B0 – B8 Input clamp voltage Input leakage g current High-level input current VCC = 0V, VIL = MAX, VOH = 1.9V 100 VCC = 0V, VIL = MAX, VOH = 1.9V @ 85°C 300 µA µA VCC–0.2 V 2.4 V VCC = MIN; IOH = -32mA 2.0 V VCC = MIN; IOL = 16mA 0.4 V VCC = MIN; IOL = 32mA 0.5 V VCC = MIN, IOL = 4mA VCC = MIN, IOL = 100mA 0.5 0.75 VCC = MIN, II = IIK = –18mA 1.0 1.20 –0.85 –1.2 V V ±1.0 Control pins VCC = 3.6V; VI = VCC or GND Control/ AI0 – AI8 VCC = 0V or 3.6V; VI = 5.5V 10 AI0 – AI8 VCC = 3.6V; VI = VCC 1 Note 4 VCC = 3.6V; VI = 0V –5 VCC = MAX, VI = 1.9V 100 B0 – B8 UNIT VCC = MIN; IOH = -8mA VCC = MAX, VI = 3.5V, note 5 100 VCC = MAX, VI = 3.75V @ –40°C 100 µA µ µA mA –100 µA VCC = MAX, VO =3V 5 µA VCC = MAX, VO = 0.5V –5 µA 18 32 mA VCC = MAX, outputs Low 22 37 mA VCC = MAX, outputs High 11 16 mA ICCL A to B VCC = MAX, outputs Low 11 16 mA ICCZ VCC = MAX 18 32 mA Low-level input current B0 – B8 VCC = MAX, VI = 0.75V IOZH Off-state output current AO0 – AO8 IOZL Off-state output current AO0 – AO8 ICCH B to A VCC = MAX, outputs High ICCL B to A ICCH A to B Supply current (total) MAX 100 IIL ICC TYP2 VCC = MAX, VIL = MAX, VOH = 1.9V VCC = MIN to MAX AO0 – AO83 LIMITS MIN NOTES: 1. For conditions shown as MIN or MAX, use the appropriate value specified under recommended operation conditions for the applicable type. 2. All typical values are at VCC = 3.3V, TA = 25°C. 3. Due to test equipment limitations, actual test conditions are VIH = 1.8V and VIL = 1.3V for the B side. 4. Unused pins are at VCC or GND. 5. For B port input voltage between 3 and 5 volt; IIH will be greater than 100mA but the part will continue to function normally (clamping circuit is active). This is not a tested condition. 2000 Apr 18 8 Philips Semiconductors Product specification 9-bit BTL 3.3V latched/registered/pass-thru Futurebus+ transceiver FBL2031 AC ELECTRICAL CHARACTERISTICS B TO A SPECIFICATIONS SYMBOL PARAMETER Tamb = +25°C, VCC = 3.3V, TEST CONDITION MIN TYP Tamb = –40 to +85°C, VCC = 3.3V±10%, MAX MIN MAX UNIT fMAX Maximum clock frequency Waveform 4 120 150 tPLH tPHL Propagation delay (thru mode) Bn to An Waveform 1, 2 2.8 3.0 4.3 4.5 5.9 6.0 2.2 2.6 6.8 7.3 MHz ns tPLH tPHL Propagation delay (transparent latch) Bn to An Waveform 1, 2 2.8 3.4 4.9 5.0 7.0 6.6 1.8 2.8 8.4 7.8 ns tPLH tPHL Propagation delay LCBA to An (latch) Waveform 1, 2 7.7 7.5 10.2 10.1 13.0 12.9 6.1 6.1 15.6 15.4 ns tPLH tPHL Propagation delay LCBA to An (register) Waveform 1, 2 2.7 3.0 4.2 4.5 5.7 6.1 2.1 2.4 6.7 6.9 ns tPLH tPHL Propagation delay SEL0 or SEL1 to An (inverting) Waveform 1, 2 2.9 1.9 5.8 5.8 9.1 10.4 2.2 1.2 10.5 11.6 ns tPLH tPHL Propagation delay SEL0 or SEL1 to An (non-inverting) Waveform 1, 2 2.0 2.8 5.9 5.6 10.3 8.8 1.4 2.2 12.3 10.0 ns tPZH tPHZ Output enable time from High or Low OEA to An Waveform 5, 6 3.0 4.0 4.4 5.6 5.7 7.3 2.6 3.2 6.6 8.3 ns tPZL tPLZ Output disable time to High or Low OEA to An Waveform 5, 6 2.6 1.4 4.0 2.6 5.4 3.7 2.1 1.0 6.0 4.4 ns tTLH tTHL Output transition time, An Port 10% to 90%, 90% to 10% Test Circuit and Waveforms 0.2 0.1 2.0 1.2 ns tSK(o) Output to output skew for multiple channels1 Waveform 3 0.5 1.0 1.5 ns tSK(p) Pulse skew2 tPHL – tPLH MAX Waveform 2 0.5 1.0 1.5 ns NOTES: 1. tPNactual – tPMactual for any data input to output path compared to any other data input to output path where N and M are either LH or HL. Skew times are valid only under same test conditions (temperature, VCC, loading, etc.). tSK (0) compares tPLH on a given path to tPLH on any other path or compares tPHL on a given path to tPHL on any other path. 2. tSK(p) is used to quantify duty cycle characteristics. In essence it compares the input signal duty cycle to the corresponding output signal duty cycle (50MHz input frequency and 50% duty cycle, tested on data paths only). 2000 Apr 18 9 Philips Semiconductors Product specification 9-bit BTL 3.3V latched/registered/pass-thru Futurebus+ transceiver FBL2031 AC ELECTRICAL CHARACTERISTICS A TO B SYMBOL PARAMETER 9 Ω LOAD SPECIFICATIONS Tamb = +25°C, VCC = 3.3V, TEST CONDITION Tamb = –40 to +85°C, VCC = 3.3V±10%, MIN TYP MAX MIN MAX UNIT tPLH tPHL Propagation delay (thru latch) An to Bn Waveform 1, 2 1.4 1.3 2.6 2.5 3.8 3.8 1.0 1.0 4.9 4.2 ns tPLH tPHL Propagation delay (transparent latch) An to Bn Waveform 1, 2 1.7 2.0 2.9 3.5 4.2 5.0 1.0 1.5 5.4 5.7 ns tPLH tPHL Propagation delay LCAB to Bn (latch) Waveform 1, 2 8.8 8.4 11.6 11.0 14.5 13.7 6.7 6.7 17.9 16.6 ns tPLH tPHL Propagation delay LCAB to Bn (register) Waveform 1, 2 2.3 2.5 3.6 4.0 5.0 5.4 1.4 1.9 6.2 6.4 ns tPLH tPHL Propagation delay SEL0 or SEL1 to Bn (inverting) Waveform 1, 2 2.3 1.3 3.8 4.8 5.5 8.8 1.2 1.0 7.0 9.6 ns tPLH tPHL Propagation delay SEL0 or SEL1 to Bn (non-inverting) Waveform 1, 2 2.0 2.6 4.4 4.3 7.2 6.1 1.1 1.7 8.5 7.6 ns tPLH tPHL OEBn to Bn Waveform 1, 2 1.2 1.9 2.9 3.3 4.8 4.7 1.0 1.2 5.8 6.4 ns tTLH tTHL Output transition time, Bn Port (1.3V to 1.8V) Test Circuit and Waveforms 1.2 0.4 3.0 1.5 ns tSK(o) Output to output skew for multiple channels1 Waveform 3 0.4 1.0 2.0 ns tSK(p) Pulse skew2 tPHL – tPLH MAX Waveform 2 0.3 1.0 1.5 ns NOTES: 1. tPNactual – tPMactual for any data input to output path compared to any other data input to output path where N and M are either LH or HL. Skew times are valid only under same test conditions (temperature, VCC, loading, etc.). tSK (0) compares tPLH on a given path to tPLH on any other path or compares tPHL on a given path to tPHL on any other path. 2. tSK(p) is used to quantify duty cycle characteristics. In essence it compares the input signal duty cycle to the corresponding output signal duty cycle (50MHz input frequency and 50% duty cycle, tested on data paths only). 2000 Apr 18 10 Philips Semiconductors Product specification 9-bit BTL 3.3V latched/registered/pass-thru Futurebus+ transceiver FBL2031 AC ELECTRICAL CHARACTERISTICS A TO B SYMBOL PARAMETER 16.5 Ω LOAD SPECIFICATIONS Tamb = +25°C, VCC = 3.3V, TEST CONDITION Tamb = –40 to +85°C, VCC = 3.3V±10%, MIN TYP MAX MIN MAX UNIT tPLH tPHL Propagation delay (thru latch) An to Bn Waveform 1, 2 1.4 1.2 2.7 2.4 3.9 3.6 1.0 1.0 5.0 4.0 ns tPLH tPHL Propagation delay (transparent latch) An to Bn Waveform 1, 2 1.8 2.0 3.0 3.2 4.2 4.7 1.0 1.4 5.6 5.5 ns tPLH tPHL Propagation delay LCAB to Bn (latch) Waveform 1, 2 8.6 8.0 11.4 10.6 14.2 13.3 6.5 6.4 17.5 16.1 ns tPLH tPHL Propagation delay LCAB to Bn (register) Waveform 1, 2 2.2 2.3 3.5 3.7 4.8 5.1 1.2 1.7 6.1 5.9 ns tPLH tPHL Propagation delay SEL0 or SEL1 to Bn (inverting) Waveform 1, 2 2.6 1.4 4.5 4.4 6.7 7.7 1.5 1.1 8.1 8.4 ns tPLH tPHL Propagation delay SEL0 or SEL1 to Bn (non-inverting) Waveform 1, 2 2.2 2.3 4.5 4.0 6.9 5.8 1.4 1.5 8.2 6.9 ns tPLH tPHL OEB0 to Bn Waveform 1, 2 1.8 1.7 3.1 2.9 4.4 4.2 1.0 1.0 5.8 6.0 ns tTLH tTHL Output transition time, Bn Port (1.3V to 1.8V) Test Circuit and Waveforms 1.2 0.4 3.0 1.5 ns tSK(o) Output to output skew for multiple channels1 Waveform 3 0.5 1.0 2.0 ns tSK(p) Pulse skew2 tPHL – tPLH MAX Waveform 2 0.5 1.0 1.5 ns NOTES: 1. tPNactual – tPMactual for any data input to output path compared to any other data input to output path where N and M are either LH or HL. Skew times are valid only under same test conditions (temperature, VCC, loading, etc.). tSK (0) compares tPLH on a given path to tPLH on any other path or compares tPHL on a given path to tPHL on any other path. 2. tSK(p) is used to quantify duty cycle characteristics. In essence it compares the input signal duty cycle to the corresponding output signal duty cycle (50MHz input frequency and 50% duty cycle, tested on data paths only). 2000 Apr 18 11 Philips Semiconductors Product specification 9-bit BTL 3.3V latched/registered/pass-thru Futurebus+ transceiver FBL2031 AC SETUP REQUIREMENTS (Commercial) LIMITS SYMBOL TEST CONDITION PARAMETER Setup time An to LCAB th(H) th(L) UNIT CL = 50pF (A side) / CD = 30pF (B side) RL = 500Ω (A side) / RU = 16.5Ω (B side) MIN ts(H) ts(L) Tamb = –40 to +85°C, VCC = 3.3V±10%, Tamb = +25°C, VCC = 3.3V, TYP MIN Waveform 4 1.3 1.3 1.5 1.5 ns Hold time An to LCAB Waveform 4 1.0 1.0 1.0 1.0 ns ts(H) ts(L) Setup time Bn to LCBA Waveform 4 5.0 4.0 6.0 4.5 ns th(H) th(L) Hold time Bn to LCBA Waveform 4 0.0 0.0 0.0 0.0 ns tw(H) tw(L) Pulse width, High or Low LCAB or LCBA Waveform 4 3.0 3.0 3.0 3.0 ns AC WAVEFORMS VM Input Output tPLH tw (output) VM VM Waveform 2. Propagation Delay for Data or Output Enable to Output ÍÍÍÍÍÍ ÍÍ ÍÍÍÍÍÍ ÍÍ An, Bn VM VM ts tSK(o) An, Bn VM tw (input) tPHL VM Waveform 1. Propagation Delay for Data or Output Enable to Output An, Bn VM tPHL VM Output Input VM tPLH LCAB, LCBA VM th VM ts tw(L) tw(H) th VM 1/fMAX Waveform 3. Output to Output Skew OEA VM VM tPZH An Waveform 4. Setup and Hold Times, Pulse Widths and Maximum Frequency OEA tPHZ VM VOH -0.3V VM tPZL OV An Waveform 5. 3-State Output Enable Time to High Level and Output Disable Time from High Level tPLZ VM VOL +0.3V Waveform 6. 3-State Output Enable Time to Low Level and Output Disable Time from Low Level NOTE: VM = 1.55V for Bn, VM = 1.5V for all others. The shaded areas indicate when the input is permitted to change for predictable output performance. 2000 Apr 18 VM 12 SG00062 Philips Semiconductors Product specification 9-bit BTL 3.3V latched/registered/pass-thru Futurebus+ transceiver FBL2031 TEST CIRCUIT AND WAVEFORMS VCC VIN RL VOUT PULSE GENERATOR tW 90% 7.0V NEGATIVE PULSE VM VM 10% D.U.T. RT CL AMP (V) 90% RL 10% LOW V tTHL (tf) tTLH (tr) tTLH (tr) tTHL (tf) AMP (V) 90% 90% POSITIVE PULSE Test Circuit for 3-State Outputs on A Port LOW V VM = 1.55V for Bn, VM = 1.5V for all others. Input Pulse Definitions SWITCH tPLZ, tPZL All other closed open VCC BIAS V VIN 2.0V (for RU = 9 Ω) 2.1V (for RU = 16.5 Ω) VOUT PULSE GENERATOR RU D.U.T. RT Test Circuit for Outputs on B Port 2000 Apr 18 10% tW SWITCH POSITION TEST VM VM 10% CD INPUT PULSE REQUIREMENTS Family FB+ Amplitude Low V Rep. Rate A Port 3.0V 0.0V 1MHz 500ns 2.5ns 2.5ns B Port 2.0V 1.0V 1MHz 500ns 2.0ns 2.0ns tW tTLH tTHL DEFINITIONS: RL = Load Resistor; see AC CHARACTERISTICS for value. CL = Load capacitance includes jig and probe capacitance; see AC CHARACTERISTICS for value. RT = Termination resistance should be equal to ZOUT of pulse generators. CD = Load capacitance includes jig and probe capacitance; see AC CHARACTERISTICS for value. RU = Pull up resistor; see AC CHARACTERISTICS for value. SG00063 13 Philips Semiconductors Product specification 9-bit BTL 3.3V latched/registered/pass-thru Futurebus+ transceiver QFP52: plastic quad flat package; 52 leads (lead length 1.6 mm); body 10 x 10 x 2.0 mm 2000 Apr 18 14 FBL2031 SOT379-1 Philips Semiconductors Product specification 9-bit BTL 3.3V latched/registered/pass-thru Futurebus+ transceiver NOTES 2000 Apr 18 15 FBL2031 Philips Semiconductors Product specification 9-bit BTL 3.3V latched/registered/pass-thru Futurebus+ transceiver FBL2031 Data sheet status Data sheet status Product status Definition [1] Objective specification Development This data sheet contains the design target or goal specifications for product development. Specification may change in any manner without notice. Preliminary specification Qualification This data sheet contains preliminary data, and supplementary data will be published at a later date. Philips Semiconductors reserves the right to make changes at any time without notice in order to improve design and supply the best possible product. Product specification Production This data sheet contains final specifications. Philips Semiconductors reserves the right to make changes at any time without notice in order to improve design and supply the best possible product. [1] Please consult the most recently issued datasheet before initiating or completing a design. Definitions Short-form specification — The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook. Limiting values definition — Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information — Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Disclaimers Life support — These products are not designed for use in life support appliances, devices or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application. Right to make changes — Philips Semiconductors reserves the right to make changes, without notice, in the products, including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified. Copyright Philips Electronics North America Corporation 2000 All rights reserved. Printed in U.S.A. Philips Semiconductors 811 East Arques Avenue P.O. Box 3409 Sunnyvale, California 94088–3409 Telephone 800-234-7381 Date of release: 04-00 Document order number: 2000 Apr 18 16 9397 750 07089