SAA7144HL Quadruple video input processor Rev. 01 — 21 April 2005 Product data sheet 1. General description The SAA7144HL is a combination of four stand alone multistandard video decoders. The SAA7144HL is a pure 3.3 V (5 V tolerant inputs and I/Os) CMOS circuit and a highly integrated circuit for video surveillance applications. All four video decoders are based on the principle of line-locked clock decoding and are able to decode the color of PAL, SECAM and NTSC signals into “CCIR 601” compatible color component values. The SAA7144HL accepts as analog inputs in total eight CVBS sources from TV or VTR (two selectable CVBS sources for each of the four decoders). Each of the four video decoders (A, B, C, D) contains an analog preprocessing circuit including source selection for two CVBS sources, anti-aliasing filter and Analog-to-Digital Converter (ADC), an automatic clamp and gain control, a Clock Generation Circuit (CGC), a digital multistandard decoder (PAL, NTSC and SECAM), a Brightness Contrast Saturation (BCS) control circuit, a multistandard text slicer see Figure 1 and a 27 MHz VBI data bypass. The integrated high performance multistandard data slicer supports several VBI data standards: • Teletext [WST (World Standard Teletext), CCST (Chinese teletext)] (625 lines) • Teletext [US-WST, NABTS (North American Broadcast Text System) and MOJI (Japanese teletext)] (525 lines) • • • • • Closed caption [Europe, US (line 21)] Wide Screen Signalling (WSS) Video Programming Signal (VPS) Time codes (VITC EBU/SMPTE) HIGH-speed VBI data bypass for Intercast™ application. The circuit is I2C-bus controlled via two I2C-bus interfaces where two video decoders share one I2C-bus interface on different I2C-bus slave addresses. Each of the four video decoders of the SAA7144HL uses a register mapping which is compatible to the SAA7113H register mapping. SAA7144HL Philips Semiconductors Quadruple video input processor 2. Features 2.1 General ■ Four stand alone video decoder instances (A, B, C, D) with two selectable CVBS video inputs each and digital video outputs ■ Programming register mapping identical to SAA7113H ■ Small package (LQFP128) ■ Requires only one crystal (24.576 MHz) for all standards shared by all video decoder instances ■ CMOS 3.3 V device with 5 V tolerant digital inputs and I/O ports ■ All four decoder instances are I2C-bus controlled. Two decoder instances share one I2C-bus interface (full read-back ability by an external controller, bit rate up to 400 kbit/s). 2.2 Features of each of the four video decoder instances A, B, C and D ■ Two analog CVBS inputs with internal analog source selectors ■ One analog preprocessing channel in differential CMOS style with built-in analog anti-aliasing filter ■ Fully programmable static gain or automatic gain control for the selected CVBS channel ■ Switchable white peak control ■ Line-locked system clock frequencies ■ Digital PLL for horizontal sync processing and clock generation, horizontal and vertical sync detection ■ Automatic detection of 50 Hz and 60 Hz field frequency and automatic switching between PAL and NTSC standards ■ Luminance and chrominance signal processing for PAL BGHI, PAL N, combination PAL N, PAL M, NTSC M, NTSC N, NTSC 4.43, NTSC Japan and SECAM ■ User programmable luminance peaking or aperture correction ■ Cross-color reduction for NTSC by chrominance comb filtering ■ PAL delay line for correcting PAL phase errors ■ Brightness Contrast Saturation (BCS) and hue control on-chip ■ Multistandard VBI data slicer decoding World Standard Teletext (WST), North American Broadcast Text System (NABTS), closed caption, Wide Screen Signalling (WSS), Video Programming System (VPS), Vertical Interval Time Code (VITC) variants (EBU/SMPTE), etc. ■ Standard ITU-R BT 656 Y-CB-CR 4 : 2 : 2 format (8-bit) on VPO output bus ■ Enhanced ITU-R BT 656 output format on VPO output bus containing: ◆ Active video ◆ Decoded VBI data ■ Boundary scan test circuit complies with the “IEEE Std. 1149.b1 - 1994”. 3. Applications ■ Surveillance application. 9397 750 14454 Product data sheet © Koninklijke Philips Electronics N.V. 2005. All rights reserved. Rev. 01 — 21 April 2005 2 of 64 SAA7144HL Philips Semiconductors Quadruple video input processor 4. Quick reference data Table 1: Quick reference data Symbol Parameter VDDD Conditions Min Typ Max Unit digital supply voltage 3.0 3.3 3.6 V VDDA analog supply voltage 3.1 3.3 3.5 V Tamb ambient temperature 0 25 70 °C PA+D analog and digital power dissipation - 1.1 - W 5. Ordering information Table 2: Ordering information Type number SAA7144HL Package Name Description Version LQFP128 plastic low profile quad flat package; 128 leads; body 14 × 20 × 1.4 mm SOT425-1 9397 750 14454 Product data sheet © Koninklijke Philips Electronics N.V. 2005. All rights reserved. Rev. 01 — 21 April 2005 3 of 64 SAA7144HL Philips Semiconductors Quadruple video input processor 6. Block diagram VIDEO DECODER A ANALOG PROCESSING MULTISTANDARD TEXT SLICER OUTPUT AND AI11_A AI1D_A AI12_A AGND_A ANALOG-TODIGITAL CONVERSION AD1 CONTROL ANALOG PROCESSING CONTROL VPO[7:0]_A FORMATTER VBI DATA BYPASS UPSAMPLING FILTER BYPASS UV Y CHROMINANCE CVBS CIRCUIT AND BCS SAA7144HL CLOCKS CVBS Y LUMINANCE CIRCUIT Y CLOCK GENERATION CIRCUIT I2C-BUS CONTROL I2C-BUS INTERFACE SYNCHRONIZATION CIRCUIT LFCO POWER-ON CONTROL I2C-BUS INTERFACE SYNCHRONIZATION CIRCUIT LFCO POWER-ON CONTROL LLC_A SCL_AB SDA_AB I2C-BUS CONTROL AGND_B ANALOG PROCESSING CONTROL LLC_B Y CVBS AD1 ANALOG-TODIGITAL CONVERSION Y UV CHROMINANCE CIRCUIT AND BCS CVBS BYPASS VBI DATA BYPASS UPSAMPLING FILTER AND ANALOG PROCESSING Y CLOCKS CONTROL AI12_B AI1D_B AI11_B LUMINANCE CIRCUIT CLOCK GENERATION CIRCUIT MULTISTANDARD TEXT SLICER VIDEO DECODER B VIDEO DECODER C ANALOG PROCESSING MULTISTANDARD TEXT SLICER OUTPUT AND AI11_C AI1D_C AI12_C AGND_C CONTROL ANALOG PROCESSING CONTROL I2C-BUS CONTROL I2C-BUS INTERFACE TEST CONTROL BLOCK FOR BOUNDARY SCAN TEST AND SCAN TEST TDI TCK TMS TRST_N TDO FORMATTER VBI DATA BYPASS UPSAMPLING FILTER ANALOG-TODIGITAL CONVERSION AD1 VPO[7:0]_B OUTPUT FORMATTER VPO[7:0]_C BYPASS UV Y CHROMINANCE CVBS CIRCUIT AND BCS CLOCKS CVBS Y LUMINANCE CIRCUIT Y CLOCK GENERATION CIRCUIT LLC_C SYNCHRONIZATION CIRCUIT LFCO POWER-ON CONTROL SYNCHRONIZATION CIRCUIT LFCO POWER-ON CONTROL SCL_CD SDA_CD I2C-BUS INTERFACE I2C-BUS CONTROL AGND_D ANALOG PROCESSING CONTROL LLC_D Y CVBS CVBS AD1 ANALOG-TODIGITAL CONVERSION CLOCK GENERATION CIRCUIT Y CLOCKS CONTROL AI12_D AI1D_D AI11_D LUMINANCE CIRCUIT CHROMINANCE CIRCUIT AND BCS Y UV BYPASS VBI DATA BYPASS UPSAMPLING FILTER AND OUTPUT ANALOG PROCESSING FORMATTER VPO[7:0]_D MULTISTANDARD TEXT SLICER VIDEO DECODER D 001aab304 Fig 1. Block diagram of SAA7144HL. 9397 750 14454 Product data sheet © Koninklijke Philips Electronics N.V. 2005. All rights reserved. Rev. 01 — 21 April 2005 4 of 64 SAA7144HL Philips Semiconductors Quadruple video input processor 7. Pinning information 103 128 7.1 Pinning 102 1 SAA7144HL 64 65 39 38 001aab305 Fig 2. Pin configuration for LQFP128. 7.2 Pin description Table 3: Pin description Symbol Pin Description VSSA1(DECA) 1 analog ground for analog supply of the Analog-to-Digital Converter (ADC) of video decoder A VDDA1(DECA) 2 analog supply voltage for the ADC (3.3 V) of video decoder A AI11_A 3 analog input 11 of video decoder A AI12_A 4 analog input 12 of video decoder A AI1D_A 5 differential analog input for AI11 and AI12 of video decoder A; see Figure 28 AGND_A 6 analog ground reference for video decoder A DNC1 7 do not connect; leave open VDDA0(DECA) 8 analog supply voltage for the internal Clock Generation Circuit (CGC) of video decoder A VSSA0(DECA) 9 analog ground for the internal CGC of video decoder A VSSA1(DECB) 10 analog ground for analog supply of the ADC of video decoder B VDDA1(DECB) 11 analog supply voltage for the ADC (3.3 V) of video decoder B AI11_B 12 analog input 11 of video decoder B AI12_B 13 analog input 12 of video decoder B AI1D_B 14 differential analog input for AI11 and AI12 of video decoder B; see Figure 28 AGND_B 15 analog ground reference for video decoder B DNC2 16 do not connect; leave open DNC3 17 do not connect; leave open VDDA0(DECB) 18 analog supply voltage for the internal CGC of video decoder B 9397 750 14454 Product data sheet © Koninklijke Philips Electronics N.V. 2005. All rights reserved. Rev. 01 — 21 April 2005 5 of 64 SAA7144HL Philips Semiconductors Quadruple video input processor Table 3: Pin description …continued Symbol Pin Description VSSA0(DECB) 19 analog ground for the internal CGC of video decoder B VSSA1(DECC) 20 analog ground for analog supply of the ADC of video decoder C VDDA1(DECC) 21 analog supply voltage for the ADC (3.3 V) of video decoder C DNC4 22 do not connect; leave open AI11_C 23 analog input 11 of video decoder C AI12_C 24 analog input 12 of video decoder C AI1D_C 25 differential analog input for AI11 and AI12 of video decoder C; see Figure 28 AGND_C 26 analog ground reference for video decoder C DNC5 27 do not connect; leave open VDDA0(DECC) 28 analog supply voltage for the internal CGC of video decoder C VSSA0(DECC) 29 analog ground for the internal CGC of video decoder C VSSA1(DECD) 30 analog ground for analog supply of the ADC of video decoder D VDDA1(DECD) 31 analog supply voltage for the ADC (3.3 V) of video decoder D AI11_D 32 analog input 11 of video decoder D AI12_D 33 analog input 12 of video decoder D AI1D_D 34 differential analog input for AI11 and AI12 of video decoder D; see Figure 28 AGND_D 35 analog ground reference for video decoder D DNC6 36 do not connect; leave open VDDA0(DECD) 37 analog supply voltage for the internal CGC of video decoder D VSSA0(DECD) 38 analog ground for the internal CGC of video decoder D DNC7 39 do not connect; leave open DNC8 40 do not connect; leave open DNC9 41 do not connect; leave open DNC10 42 do not connect; leave open DNC11 43 do not connect; leave open DNC12 44 do not connect; leave open DNC13 45 do not connect; leave open SCL_AB 46 serial clock input (I2C-bus) for instances A and B SDA_AB 47 serial data input/output (I2C-bus) for instances A and B SCL_CD 48 serial clock input (I2C-bus) for instances C and D SDA_CD 49 serial data input/output (I2C-bus) for instances C and D LLC_D 50 line-locked clock output (27 MHz) of video decoder D VPO7_D 51 digital video output bus signal VPO7 of video decoder D VPO6_D 52 digital video output bus signal VPO6 of video decoder D VPO5_D 53 digital video output bus signal VPO5 of video decoder D VDDDE 54 supply for digital pad ring (3.3 V) VSSDE 55 ground for digital pad ring VPO4_D 56 digital video output bus signal VPO4 of video decoder D VPO3_D 57 digital video output bus signal VPO3 of video decoder D 9397 750 14454 Product data sheet © Koninklijke Philips Electronics N.V. 2005. All rights reserved. Rev. 01 — 21 April 2005 6 of 64 SAA7144HL Philips Semiconductors Quadruple video input processor Table 3: Pin description …continued Symbol Pin Description VSSDI 58 ground for digital core VDDDI 59 supply for digital core (3.3 V) VPO2_D 60 digital video output bus signal VPO2 of video decoder D VPO1_D 61 digital video output bus signal VPO1 of video decoder D VPO0_D 62 digital video output bus signal VPO0 of video decoder D LLC_C 63 line-locked clock output (27 MHz) of video decoder C VPO7_C 64 digital video output bus signal VPO7 of video decoder C VPO6_C 65 digital video output bus signal VPO6 of video decoder C DNC14 66 do not connect; leave open VPO5_C 67 digital video output bus signal VPO5 of video decoder C VPO4_C 68 digital video output bus signal VPO4 of video decoder C VDDDE 69 supply for digital pad ring (3.3 V) VSSDE 70 ground for digital pad ring VPO3_C 71 digital video output bus signal VPO3 of video decoder C VPO2_C 72 digital video output bus signal VPO2 of video decoder C VSSDI 73 ground for digital core VDDDI 74 supply for digital core (3.3 V) DNC15 75 do not connect; leave open DNC16 76 do not connect; leave open VPO1_C 77 digital video output bus signal VPO1 of video decoder C DNC17 78 do not connect; leave open VPO0_C 79 digital video output bus signal VPO0 of video decoder C VSSDA 80 oscillator supply ground XTALO 81 oscillator output DNC18 82 do not connect; leave open DNC19 83 do not connect; leave open XTALI 84 oscillator input VDDDA 85 oscillator supply voltage (3.3 V) LLC_B 86 line-locked clock output (27 MHz) of video decoder B VPO7_B 87 digital video output bus signal VPO7 of video decoder B DNC20 88 do not connect; leave open VPO6_B 89 digital video output bus signal VPO6 of video decoder B DNC21 90 do not connect; leave open VSSDI 91 ground for digital core DNC22 92 do not connect; leave open VDDDI 93 supply for digital core (3.3 V) VPO5_B 94 digital video output bus signal VPO5 of video decoder B VPO4_B 95 digital video output bus signal VPO4 of video decoder B VDDDE 96 supply for digital pad ring (3.3 V) VSSDE 97 ground for digital pad ring DNC23 98 do not connect; leave open 9397 750 14454 Product data sheet © Koninklijke Philips Electronics N.V. 2005. All rights reserved. Rev. 01 — 21 April 2005 7 of 64 SAA7144HL Philips Semiconductors Quadruple video input processor Table 3: Pin description …continued Symbol Pin Description VPO3_B 99 digital video output bus signal VPO3 of video decoder B VPO2_B 100 digital video output bus signal VPO2 of video decoder B VPO1_B 101 digital video output bus signal VPO1 of video decoder B DNC24 102 do not connect; leave open VPO0_B 103 digital video output bus signal VPO0 of video decoder B LLC_A 104 line-locked clock output (27 MHz) of video decoder A VPO7_A 105 digital video output bus signal VPO7 of video decoder A VPO6_A 106 digital video output bus signal VPO6 of video decoder A VPO5_A 107 digital video output bus signal VPO5 of video decoder A VSSDI 108 ground for digital core VDDDI 109 supply for digital core (3.3 V) VPO4_A 110 digital video output bus signal VPO4 of video decoder A VDDDE 111 supply for digital pad ring (3.3 V) VSSDE 112 ground for digital pad ring VPO3_A 113 digital video output bus signal VPO3 of video decoder A VPO2_A 114 digital video output bus signal VPO2 of video decoder A VPO1_A 115 digital video output bus signal VPO1 of video decoder A VPO0_A 116 digital video output bus signal VPO0 of video decoder A TDI 117 test data input for boundary scan test [1] TDO 118 test data output for boundary scan test [1] TMS 119 test mode select input for boundary scan test or scan test [1] TCK 120 test clock for boundary scan test [1] TRST_N 121 test reset input (active LOW), for boundary scan test [1] [2] [3] DNC25 122 do not connect; leave open DNC26 123 do not connect; leave open DNC27 124 do not connect; leave open DNC28 125 do not connect; leave open DNC29 126 do not connect; leave open DNC30 127 do not connect; leave open DNC31 128 do not connect; leave open [1] In accordance with the “IEEE1149.1” standard the pads TDI, TMS, TCK and TRST_N are input pads with an internal pull-up transistor and TDO is a 3-state output pad. [2] For board design without boundary scan implementation connect the TRST_N pin to ground. [3] This pin provides easy initialization of the Boundary Scan Test (BST) circuit. TRST_N can be used to force the Test Access Port (TAP) controller to the TEST_LOGIC_RESET state (normal operation) at once. 8. Functional description The following functional descriptions are related to each of the four stand alone decoder cores (A, B, C and D). 9397 750 14454 Product data sheet © Koninklijke Philips Electronics N.V. 2005. All rights reserved. Rev. 01 — 21 April 2005 8 of 64 SAA7144HL Philips Semiconductors Quadruple video input processor 8.1 Analog input processing The analog input processing part consists of a source switch to select one out of two video inputs, clamp circuit, analog amplifier, anti-alias filter and video 9-bit CMOS ADC; see Figure 6. 8.2 Analog control circuits The anti-alias filters are adapted to the line-locked clock frequency via a filter control circuit. The characteristic is shown in Figure 3. During the vertical blanking period, gain and clamping control are frozen. mgd138 6 V 0 (dB) −6 −12 −18 −24 −30 −36 −42 0 2 4 6 8 10 12 14 f (MHz) Fig 3. Anti-alias filter. 8.2.1 Clamping The clamp control circuit controls the correct clamping of the analog input signals. The coupling capacitor is also used to store and filter the clamping voltage. An internal digital clamp comparator generates the information with respect to clamp-up or clamp-down. The clamping levels for the two ADC channels are fixed for luminance (120) and chrominance (256). Clamping time in normal use is set with the HCL pulse on the back porch of the video signal. 8.2.2 Gain control The gain control circuit receives (via the I2C-bus) the static gain levels for the analog amplifier or controls this amplifier automatically via a built-in Automatic Gain Control (AGC) as part of the Analog Input Control (AICO). The AGC (automatic gain control for luminance) is used to amplify a CVBS signal to the required signal amplitude, matched to the ADC input voltage range. The AGC active time is the sync bottom of the video signal. Signal (white) peak control limits the gain at signal overshoots. The flow charts (see Figure 7 and Figure 8) show more details of the AGC. The influence of supply voltage variation within the specified range is automatically eliminated by clamp and automatic gain control. 9397 750 14454 Product data sheet © Koninklijke Philips Electronics N.V. 2005. All rights reserved. Rev. 01 — 21 April 2005 9 of 64 SAA7144HL Philips Semiconductors Quadruple video input processor TV line analog line blanking +3 dB GAIN CLAMP 0 dB 60 −6 dB HCL 5 4 3 SOURCE SWITCH CLAMP CIRCUIT minimum Fig 5. Automatic gain range. ANALOG AMPLIFIER 9-bit DAC BYPASS SWITCH ANTI-ALIAS FILTER ADC FUSE[1:0] 9 1 9 8 MODE CONTROL 2 MODE[3:0] CLAMP CONTROL HCL GAIN CONTROL GLIMB HSY GLIMT WIPA SLTCA ANALOG CONTROL AGND_A 0 dB mhb325 Fig 4. Analog line with clamp (HCL) and gain range (HSY). VDDA0(DECA) VDDA1(DECA) range 9 dB mgl065 HSY VSSA0(DECA) VSSA1(DECA) maximum (1 V (p-p) 18/56 Ω) 1 AI1D_A AI12_A AI11_A controlled ADC input level analog input level 255 ANTI-ALIAS CONTROL HOLDG GAFIX WPOFF GUDL[1:0] GAI[18:10] HLNRS UPTCV VERTICAL BLANKING CONTROL VBSL VBLNK SVREF 6 CROSS MULTIPLEXER LUM CHR AD1BYP 001aab306 This is valid for decoder A, B, C and D. Here an example for decoder A is shown. Fig 6. Analog input processing using the SAA7144HL as differential front-end with 9-bit ADC (continued in Figure 10). 9397 750 14454 Product data sheet © Koninklijke Philips Electronics N.V. 2005. All rights reserved. Rev. 01 — 21 April 2005 10 of 64 SAA7144HL Philips Semiconductors Quadruple video input processor ANALOG INPUT gain AMPLIFIER 9 DAC ANTI-ALIAS FILTER ADC 8 1 NO ACTION LUMA/CHROMA DECODER 0 VBLK 1 HOLDG 1 0 0 X 1 0 0 <4 1 1 > 248 0 > 254 HSY 1 < 1 0 1 X=0 +1/F +1/L STOP 0 1 > 254 0 X=1 −1/LLC2 +1/LLC2 −1/LLC2 +/− 0 GAIN ACCUMULATOR (18 BITS) ACTUAL GAIN VALUE 9-BIT (AGV) [−6/+6 dB] 1 0 X 1 HSY 1 AGV 0 Y UPDATE 0 FGV GAIN VALUE 9-BIT 001aab307 X = system variable; Y = AGV – FGV > GUDL ; GUDL = gain update level (adjustable); VBLK = vertical blanking pulse; HSY = horizontal sync pulse; AGV = actual gain value; FGV = frozen gain value. Fig 7. Gain flow chart. 9397 750 14454 Product data sheet © Koninklijke Philips Electronics N.V. 2005. All rights reserved. Rev. 01 — 21 April 2005 11 of 64 SAA7144HL Philips Semiconductors Quadruple video input processor ANALOG INPUT ADC 1 NO BLANKING ACTIVE VBLK 0 <- CLAMP 1 1 < CLL + CLAMP GAIN -> 0 HCL 1 0 0 − CLAMP NO CLAMP + GAIN < SBOT HSY 1 0 1 − GAIN > WIPE fast − GAIN 0 slow + GAIN mgc647 WIPE = white peak level (254). SBOT = sync bottom level (1). CLL = clamp level [60 Y (128 C)]. HSY = horizontal sync pulse. HCL = horizontal clamp pulse. Fig 8. Clamp and gain flow. 8.3 Chrominance processing The 9-bit chrominance signal is fed to the multiplication inputs of a quadrature demodulator, where two subcarrier signals from the local oscillator DTO are applied (0° and 90° phase relationship to the demodulator axis). The frequency is dependent on the present color standard. The output signals of the multipliers are low-pass filtered (four programmable characteristics) to achieve the desired bandwidth for the color difference signals (PAL, NTSC) or the 0° and 90° FM signals (SECAM). The color difference signals are fed to the Brightness Contrast Saturation (BCS) block, which contains the following five functions: • AGC (automatic gain control for chrominance PAL and NTSC) • Chrominance amplitude matching (different gain factors for (R − Y) and (B − Y) to achieve CCIR-601 levels CR and CB for all standards) • Chrominance saturation control • Luminance contrast and brightness • Limiting Y-CB-CR to the values 1 (minimum) and 254 (maximum) to fulfil CCIR-601 requirements. 9397 750 14454 Product data sheet © Koninklijke Philips Electronics N.V. 2005. All rights reserved. Rev. 01 — 21 April 2005 12 of 64 SAA7144HL Philips Semiconductors Quadruple video input processor The SECAM processing contains the following blocks: • Baseband ‘bell’ filters to reconstruct the amplitude and phase equalized 0° and 90° FM signals • Phase demodulator and differentiator (FM-demodulation) • De-emphasis filter to compensate the pre-emphasized input signal, including frequency offset compensation (DB or DR white carrier values are subtracted from the signal, controlled by the SECAM switch signal). The burst processing block provides the feedback loop of the chrominance PLL and contains the following: • • • • • • • Burst gate accumulator Color identification and color killer Comparison nominal/actual burst amplitude (PAL/NTSC standards only) Loop filter chrominance gain control (PAL/NTSC standards only) Loop filter chrominance PLL (only active for PAL/NTSC standards) PAL/SECAM sequence detection, H/2-switch generation Increment generation for DTO with divider to generate stable subcarrier for non-standard signals. The chrominance comb filter block eliminates crosstalk between the chrominance channels in accordance with the PAL standard requirements. For NTSC color standards the chrominance comb filter can be used to eliminate crosstalk from luminance to chrominance (cross-color) for vertical structures. The comb filter can be switched off if desired. The embedded line delay is also used for SECAM recombination (cross-over switches). The resulting signals are fed to the variable Y-delay compensation and the output interface, which contains the VPO output formatter and the output control logic; see Figure 10. 9397 750 14454 Product data sheet © Koninklijke Philips Electronics N.V. 2005. All rights reserved. Rev. 01 — 21 April 2005 13 of 64 SAA7144HL Philips Semiconductors Quadruple video input processor mgd147 6 V 0 (dB) −6 (1) (2) (3) (4) −12 −18 −24 (4) (1) (3) (2) −30 −36 −42 −48 −54 0 0.54 1.08 1.62 2.16 2.7 f (MHz) Transfer characteristics of the chrominance low-pass dependent on CHBW[1:0] settings. (1) CHBW[1:0] = 00. (2) CHBW[1:0] = 01. (3) CHBW[1:0] = 10. (4) CHBW[1:0] = 11. Fig 9. Chrominance filter. 9397 750 14454 Product data sheet © Koninklijke Philips Electronics N.V. 2005. All rights reserved. Rev. 01 — 21 April 2005 14 of 64 xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx CHR Philips Semiconductors 9397 750 14454 Product data sheet LUM AD1BYP SECAM PROCESSING sequential CB-CR signals TRST_N TCK TDI TMS TDO 121 120 117 119 TEST CONTROL BLOCK QUADRATURE DEMODULATOR LOW-PASS 118 SUBCARRIER GENERATION RESET HUEC VDDA0(DECA) CHBW0 CHBW1 8 POWER-ON CONTROL SUBCARRIER INCREMENT GENERATION AND DIVIDER Rev. 01 — 21 April 2005 INCS 105, 106, 107, 110, 113, 114, 115, 116 Y PHASE DEMODULATOR CB-CR AMPLITUDE DETECTOR BURST GATE ACCUMULATOR LOOP FILTER CSTD[2:0] BRIGHTNESS, CONTRAST AND SATURATION CONTROL FCTC CODE CLOCK GAIN CBCONTROL CR AND Y-DELAY COMPENSATION BRIG CONT SATN YDEL[2:0] VPO7_A to VPO0_A COMB FILTERS SECAM RECOMBINATION DCCF fH/2 switch signal LUM OUTPUT FORMATTER AND INTERFACE OFTS[1:0] GPSW[1:0] OEYC VIPB VRLN COLO 001aab308 Y This is valid for decoder A, B, C and D. Here an example for decoder A is shown. SAA7144HL 15 of 64 © Koninklijke Philips Electronics N.V. 2005. All rights reserved. Quadruple video input processor Fig 10. Chrominance circuit, text slicer, VBI-bypass, output formatting, power and test control (continued from Figure 6 and continued in Figure 17). SAA7144HL Philips Semiconductors Quadruple video input processor 8.4 Luminance processing The 9-bit luminance signal, a digital CVBS format, is fed through a switchable prefilter. High frequency components are emphasized to compensate for loss. The following chrominance trap filter (f0 = 4.43 MHz or 3.58 MHz center frequency set according to the selected color standard) eliminates most of the color carrier signal. It can be bypassed via I2C-bus bit BYPS (subaddress 09h, bit 7). The high frequency components of the luminance signal can be peaked (control for sharpness improvement via I2C-bus subaddress 09h, see Table 33) in two band-pass filters with selectable transfer characteristic. This signal is then added to the original (unpeaked) signal. For the resulting frequency characteristics see Figure 11 to Figure 16. A switchable amplifier achieves common DC amplification, because the DC gains are different in both chrominance trap modes. The improved luminance signal is fed to the BCS control located in the chrominance processing block; see Figure 17. mgd139 18 VY (dB) (1) (2) (4) (3) 6 −6 (1) (2) (4) (3) −18 −30 0 2 4 6 8 fY (MHz) (1) 43h (2) 53h (3) 63h (4) 73h Fig 11. Luminance control SA 09h, 4.43 MHz trap, prefilter on, different aperture band-pass center frequencies. 9397 750 14454 Product data sheet © Koninklijke Philips Electronics N.V. 2005. All rights reserved. Rev. 01 — 21 April 2005 16 of 64 SAA7144HL Philips Semiconductors Quadruple video input processor mgd140 18 VY (dB) 6 (1) (2) (3) (4) −6 (4) (3) (2) (1) −18 −30 0 2 4 6 8 fY (MHz) (1) 40h (2) 41h (3) 42h (4) 43h Fig 12. Luminance control SA 09h, 4.43 MHz trap, prefilter on, different aperture factors. mgd141 18 VY (dB) 6 (1) (2) (4) (3) −6 (1) (2) (4) (3) −18 −30 0 2 4 6 8 fY (MHz) (1) 03h (2) 13h (3) 23h (4) 33h Fig 13. Luminance control SA 09h, 4.43 MHz trap, prefilter off, different aperture band-pass center frequencies. 9397 750 14454 Product data sheet © Koninklijke Philips Electronics N.V. 2005. All rights reserved. Rev. 01 — 21 April 2005 17 of 64 SAA7144HL Philips Semiconductors Quadruple video input processor mgd144 18 VY (dB) 6 (1) (2) (4) (3) −6 (1) (2) (4) (3) −18 −30 0 2 4 6 8 fY (MHz) (1) 43h (2) 53h (3) 63h (4) 73h Fig 14. Luminance control SA 09h, 3.58 MHz trap, prefilter on, different aperture band-pass center frequencies. mgd145 18 VY (dB) 6 (4) (3) (2) (1) (1) (2) (3) (4) −6 −18 −30 0 2 4 6 8 fY (MHz) (1) 40h (2) 41h (3) 42h (4) 43h Fig 15. Luminance control SA 09h, 3.58 MHz trap, prefilter on, different aperture factors. 9397 750 14454 Product data sheet © Koninklijke Philips Electronics N.V. 2005. All rights reserved. Rev. 01 — 21 April 2005 18 of 64 SAA7144HL Philips Semiconductors Quadruple video input processor mgd146 18 VY (dB) 6 (1) (2) (4) (3) −6 (1) (2) (4) (3) −18 −30 0 2 4 6 8 fY (MHz) (1) 03h (2) 13h (3) 23h (4) 33h Fig 16. Luminance control SA 09h, 3.58 MHz trap, prefilter off, different aperture band-pass center frequencies. 9397 750 14454 Product data sheet © Koninklijke Philips Electronics N.V. 2005. All rights reserved. Rev. 01 — 21 April 2005 19 of 64 SAA7144HL Philips Semiconductors Quadruple video input processor LUM Y LUMINANCE CIRCUIT VARIABLE BAND-PASS FILTER CHROMINANCE TRAP PREFILTER PREF BYPS VBLB WEIGHTING AND ADDING STAGE BPSS[1:0] PREF PREFILTER SYNC APER[1:0] VBLB MATCHING AMPLIFIER CLOCK CIRCUIT MACROVISION DETECTOR SYNC SLICER COPRO VBLB CLOCKS PHASE DETECTOR FINE SYNCHRONIZATION CIRCUIT I2 C-BUS CONTROL VNOI[1:0] HTC[1:0] FIDT I2 C-BUS INTERFACE 46 VERTICAL PROCESSOR AUFD HSB[7:0] HSS[7:0] FSEL HLCK COUNTER LINE-LOCKED CLOCK GENERATOR PHASE DETECTOR COARSE HPLL HTC[1:0] 104 CLOCK GENERATION CIRCUIT 85 DAC DISCRETE TIME OSCILLATOR CRYSTAL CLOCK GENERATOR 84 80 LLC_A VDDDA VSSDA HTC[1:0] LOOP FILTER 81 XTALI XTALO 47 001aab309 SCL_AB SDA_AB This is valid for decoder A, B, C and D. Here an example for decoder A is shown. Fig 17. Luminance and sync processing (continued from Figure 10). 8.5 Synchronization The prefiltered luminance signal is fed to the synchronization stage. Its bandwidth is further reduced to 1 MHz in a low-pass filter. The sync pulses are sliced and fed to the phase detectors where they are compared with the sub-divided clock frequency. The resulting output signal is applied to the loop filter to accumulate all phase deviations. Internal signals (e.g. HCL and HSY) are generated in accordance with analog front-end requirements. The loop filter signal drives an oscillator to generate the line frequency control signal LFCO; see Figure 18. The detection of ‘pseudo syncs’ as part of the Macrovision® copy protection standard is also achieved within the synchronization circuit. The result is reported as flag COPRO within the decoder status byte at subaddress 1Fh. 9397 750 14454 Product data sheet © Koninklijke Philips Electronics N.V. 2005. All rights reserved. Rev. 01 — 21 April 2005 20 of 64 SAA7144HL Philips Semiconductors Quadruple video input processor 8.6 Clock generation circuit The internal CGC generates all clock signals required for the video input processor. The internal signal LFCO is a digital-to-analog converted signal provided by the horizontal PLL. It is the multiple of the line frequency: 6.75 MHz = 429 × fH (50 Hz), or 6.75 MHz = 432 × fH (60 Hz). The LFCO signal is multiplied by a factor of 2 and 4 in the internal PLL circuit (including phase detector, loop filtering, VCO and frequency divider) to obtain the output clock signals. The rectangular output clocks have a 50 % duty factor. Table 4: Clock frequencies Clock Frequency (MHz) XTAL 24.576 LLC 27 LLC2 (internal) 13.5 LLC4 (internal) 6.75 LLC8 (virtual) 3.375 LFCO BAND PASS FC = LLC/4 ZERO CROSS DETECTION PHASE DETECTION LOOP FILTER OSCILLATOR LLC DIVIDER 1/2 DIVIDER 1/2 LLC2 mhb330 Fig 18. Block diagram of clock generation circuit. 8.7 Power-on reset A missing clock, insufficient digital or analog VDDA0 supply voltages will start the reset sequence; all outputs are forced to 3-state; see Figure 19. After sufficient power supply voltage, the outputs LLC and SDA return from 3-state to active. 9397 750 14454 Product data sheet © Koninklijke Philips Electronics N.V. 2005. All rights reserved. Rev. 01 — 21 April 2005 21 of 64 SAA7144HL Philips Semiconductors Quadruple video input processor POC VDDA0 ANALOG POC VDD DIGITAL POC LOGIC POC DELAY LLC CLOCK PLL RES_N RESINT CLK0 supply XTALO LLCINT RESINT LLC RES_N (internal reset) some ms 20 µs to 200 µs PLL-delay < 1 ms 896 LLC digital delay 128 LLC 001aab312 POC = Power-on control. XTALO = crystal oscillator output. LLCINT = internal system clock. RESINT = internal reset. LLC = line-locked clock output. RES_N = delayed internal reset. Fig 19. Power-on control circuit. Table 5: Power-on control sequence Internal power-on control sequence Pin output status Remarks Directly after power-on asynchronous reset VPO7 to VPO0, SDA and LLC are in high-impedance state direct switching to high-impedance for 20 ms to 200 ms Synchronous reset sequence LLC and SDA become active; VPO7 to VPO0, are held in high-impedance state internal reset sequence Status after power-on control sequence VPO7 to VPO0, are held in high-impedance state after power-on (reset sequence) a complete I2C-bus transmission is required 9397 750 14454 Product data sheet © Koninklijke Philips Electronics N.V. 2005. All rights reserved. Rev. 01 — 21 April 2005 22 of 64 SAA7144HL Philips Semiconductors Quadruple video input processor 8.8 Multistandard VBI data slicer The multistandard data slicer is a Vertical Blanking Interval (VBI) and Full Field (FF) video data acquisition block. In combination with software modules the slicer acquires most existing formats of broadcast VBI and FF data. The implementation and programming model is in accordance with the VBI data slicer built into the multimedia video data acquisition circuit SAA5284. The circuitry recovers the actual clock phase during the clock run-in period, slices the data bits with the selected data rate, and groups them into bytes. The clock frequency, signal source, field frequency and accepted error count must be defined via the I2C-bus in subaddress 40h, bits 7 to 4. Several standards can be selected per VBI line. The supported VBI data standards are described in Table 6. The programming of the desired standards is done via I2C-bus subaddresses 41h to 57h (LCR2[7:0] to LCR24[7:0]); see detailed description in Section 8.10. To adjust the slicers processing to the signals source, there are offsets in horizontal and vertical direction available via the I2C-bus in subaddresses 5Bh (bits 2 to 0), 59h (HOFF10 to HOFF0) and 5Bh (bit 4), 5Ah (VOFF8 to VOFF0). The formatting of the decoded VBI data is done within the output interface to the VPO-bus. For a detailed description of the sliced data format see Table 20. Table 6: Supported VBI standards Standard type Data rate (Mbit/s) Framing code FC window Hamming check Teletext EuroWST, CCST 6.9375 27h WST625 European closed caption 0.500 001 CC625 VPS 5 always 9951h VPS Wide screen signalling 5 bits 1E3C1Fh WSS US teletext (WST) 5.7272 27h WST525 US closed caption (line 21) 0.503 001 CC525 Teletext 6.9375 programmable general text optional VITC/EBU time codes 1.8125 (Europe) programmable VITC625 VITC/SMPTE time codes (USA) 1.7898 programmable VITC625 US NABTS 5.7272 programmable NABTS MOJI (Japanese) 5.7272 programmable (A7h) Japtext Japanese format switch (L20/22) 5 programmable always optional 8.9 VBI-raw data bypass For a 27 MHz VBI-raw data bypass the digitized CVBS signal is upsampled after analog-to-digital conversion. Suppressing of the back folded CVBS frequency components after upsampling is achieved by an interpolation filter; see Figure 20. 9397 750 14454 Product data sheet © Koninklijke Philips Electronics N.V. 2005. All rights reserved. Rev. 01 — 21 April 2005 23 of 64 SAA7144HL Philips Semiconductors Quadruple video input processor mgg067 6 V 0 (dB) −6 −12 −18 −24 −30 −36 −42 −48 −54 0 2 4 6 8 10 12 14 f (MHz) Fig 20. Interpolation filter for the upsampled CVBS signal. 8.10 Digital output port The 8-bit VPO-bus can carry 16 data types in three different formats, selectable by the control registers LCR2 to LCR24 (see also Section 9, subaddresses 41h to 57h). OEYC (output enable Y-CB-CR) bit (subaddress 11h, bit 3) in I2C-bus register needs to be set to logic 1 to enable the VPO-bus. Table 7: VPO-bus data formats and types [1] Data type number Data format Data type Name Number of valid bytes sent per line 0 sliced teletext EuroWST, CCST WST625 88 1 sliced European closed caption CC625 8 2 sliced VPS VPS 56 3 sliced wide screen signalling bits WSS 32 4 sliced US teletext (WST) WST525 72 5 sliced US closed caption (line 21) CC525 8 6 Y-CB-CR 4 : 2 : 2 video component signal, VBI region test line 1440 7 raw oversampled CVBS data Intercast™ programmable 8 sliced teletext general text 88 9 sliced VITC/EBU time codes (Europe) VITC625 26 10 sliced VITC/SMPTE time codes (USA) VITC625 26 11 reserved reserved - - 12 sliced US NABTS NABTS 72 13 sliced MOJI (Japanese) Japtext 74 14 sliced Japanese format switch (L20/22) JFS 56 15 Y-CB-CR 4 : 2 : 2 video component signal, active video region active video 1440 [1] The number of valid bytes per line can be less for the sliced data format if standard not recognized (wrong standard or poor input signal). 9397 750 14454 Product data sheet © Koninklijke Philips Electronics N.V. 2005. All rights reserved. Rev. 01 — 21 April 2005 24 of 64 SAA7144HL Philips Semiconductors Quadruple video input processor For each LCR value from 2 to 23 the data type can be programmed individually. LCR2 to LCR23 refer to line numbers. The selection in LCR24 values is valid for the rest of the corresponding field. The upper nibble contains the value for field 1 (odd), the lower nibble for field 2 (even). The relationship between LCR values and line numbers can be adjusted via VOFF8 to VOFF0 (located in subaddresses 5Bh, bit 4 and 5Ah, bits 7 to 0). The recommended values are 07h for 50 Hz sources and 0Ah for 60 Hz sources, to accommodate line number conventions as used for PAL, SECAM and NTSC standards; see Table 11 to Table 14. Some details about data types: • Active video (data type 15) component Y-CB-CR 4 : 2 : 2 signal, 720 active pixels per line. Format and nominal levels are given in Figure 21 and Table 16. • Test line (data type 6), is similar to decoded Y-CB-CR data as in active video, with two exceptions: – vertical filter (chrominance comb filter for NTSC standards, PAL-phase-error correction) within the chrominance processing is disabled – peaking and chrominance trap are bypassed within the luminance processing, if I2C-bus bit VBLB is set. This data type is defined for future enhancements; it could be activated for lines containing standard test signals within the vertical blanking period; currently the most sources do not contain test lines. This data type is available only in lines with VREF = 0, see I2C-bus detail section, Table 41. Format and nominal levels are given in Figure 21 and Table 16. • Raw samples (data type 7) oversampled CVBS-signal for Intercast™ applications; the data rate is 27 MHz. The horizontal range is programmable via HSB7 to HSB0, HSS7 to HSS0 and HDEL1 to HDEL0; see Section 9.3.6, Section 9.3.7 and Section 9.3.16 and Table 30, Table 31 and Table 40. Format and nominal levels are given in Figure 22 and Table 18. • Sliced data (various standards, data types 0 to 5 and 8 to 14). The format is given in Table 20. The data type selections by LCR are overruled by setting VIPB (subaddress 11h bit 1) to logic 1. This setting is mainly intended for device production tests. The VPO-bus carries the upper or lower 8 bits of the ADC depending on the ADLSB (subaddress 13h bit 7) setting. The output configuration is done via MODE3 to MODE0 settings (subaddress 02h bits 3 to 0; see Table 27). The SAV/EAV timing reference codes define start and end of valid data regions. 9397 750 14454 Product data sheet © Koninklijke Philips Electronics N.V. 2005. All rights reserved. Rev. 01 — 21 April 2005 25 of 64 SAA7144HL Philips Semiconductors Quadruple video input processor Table 8: SAV/EAV format Bit Symbol 7 6 Description logic 1 F field bit 1st field: F = 0 2nd field: F = 1 for vertical timing see Table 9 and Table 10 5 V vertical blanking bit VBI: V = 1 active video: V = 0 for vertical timing see Table 9 and Table 10 4 H H = 0 in SAV; H = 1 in EAV 3 to 0 P[3:0] reserved; evaluation not recommended (protection bits according to ITU-R BT 656) The generation of the H-bit and consequently the timing of SAV/EAV corresponds to the selected data format. H = 0 during active data region. For all data formats excluding data type 7 (raw data), the length of the active data region is 1440 LLC. For the Y-CB-CR 4 : 2 : 2 formats (data types 15 and 6) every clock cycle within this range contains valid data; see Table 16. The sliced data stream (various standards, data types 0 to 5 and 8 to 14; see Table 20) contains also invalid cycles marked as 00h. The length of the raw data region (data type 7) is programmable via HSB7 to HSB0 and HSS7 to HSS0 (subaddresses 06h and 07h; see Figure 22). During horizontal blanking period between EAV and SAV the ITU-blanking code sequence ‘-80-10-80-10-...’ is transmitted. The position of the F-bit is constant according to ITU-R BT 656; see Table 9 and Table 10. The V-bit can be generated in four different ways (see Table 9 and Table 10) controlled via OFTS1 and OFTS0 (subaddress 10h, bits 7 and 6), VRLN (subaddress 10h, bit 3) and LCR2 to LCR24 (subaddresses 41h to 57h). F and V bits change synchronously with the EAV code. 9397 750 14454 Product data sheet © Koninklijke Philips Electronics N.V. 2005. All rights reserved. Rev. 01 — 21 April 2005 26 of 64 SAA7144HL Philips Semiconductors Quadruple video input processor Table 9: 525 lines/60 Hz vertical timing Line number F V (ITU-R BT 656) OFTS1 = 0; OFTS1 = 0; OFTS0 = 1 OFTS0 = 0 VRLN = 0 VRLN = 1 (ITU-R BT 656) 1 to 3 1 1 1 1 4 to 19 0 1 1 1 20 0 0 1 1 21 0 0 1 0 22 to 261 0 0 0 0 262 0 0 1 0 263 0 0 1 1 264 and 265 0 1 1 1 266 to 282 1 1 1 1 283 1 0 1 1 284 1 0 1 0 285 to 524 1 0 0 0 525 1 0 1 0 Table 10: according to selected data type via LCR2 to LCR24 (subaddresses 41h to 57h): data types 0 to 14: V = 1; data type 15: V = 0 625 lines/50 Hz vertical timing Line number F V (ITU-R BT 656) OFTS1 = 0; OFTS1 = 0; OFTS0 = 1 OFTS0 = 0 VRLN = 0 VRLN = 1 (ITU-R BT 656) 1 to 22 0 1 1 1 23 0 0 1 0 24 to 309 0 0 0 0 310 0 0 1 0 311 and 312 0 1 1 1 313 to 335 1 1 1 1 336 1 0 1 0 337 to 622 1 0 0 0 623 1 0 1 0 624 and 625 1 1 1 1 9397 750 14454 Product data sheet OFTS1 = 1; OFTS0 = 0 OFTS1 = 1; OFTS0 = 0 according to selected data type via LCR2 to LCR24 (subaddresses 41h to 57h): data types 0 to 14: V = 1; data type 15: V = 0 © Koninklijke Philips Electronics N.V. 2005. All rights reserved. Rev. 01 — 21 April 2005 27 of 64 xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx Philips Semiconductors 9397 750 14454 Product data sheet Table 11: Relationship of LCR to line numbers in 525 lines/60 Hz systems (part 1) Vertical line offset VOFF8 to VOFF0 = 00Ah; horizontal pixel offset HOFF10 to HOFF0 = 354h, FOFF = 1, FISET = 1 Line number (1st field) 519 520 521 522 523 524 525 1 active video Line number (2nd field) 257 258 259 260 261 262 263 active video 2 4 5 6 7 8 9 serration pulses equalization pulses 264 267 270 265 266 equalization pulses LCR (VOFF = 00Ah; HOFF = 354h; 24 FOFF = 1; FISET = 1) Table 12: 3 equalization pulses 2 268 269 serration pulses 3 4 5 271 272 equalization pulses 6 7 8 9 Relationship of LCR to line numbers in 525 lines/60 Hz systems (part 2) Vertical line offset VOFF8 to VOFF0 = 00Ah; horizontal pixel offset HOFF10 to HOFF0 = 354h, FOFF = 1, FISET = 1 Line number (1st field) 10 11 12 13 14 15 16 17 18 19 20 21 nominal VBI-lines F1 Line number (2nd field) 273 274 275 276 277 278 279 280 281 282 283 284 Rev. 01 — 21 April 2005 nominal VBI-lines F2 LCR (VOFF = 00Ah; HOFF = 354h; 10 FOFF = 1; FISET = 1) Table 13: 11 12 22 23 active video 285 286 active video 13 14 15 16 17 18 19 20 21 22 23 Relationship of LCR to line numbers in 625 lines/50 Hz systems (part 1) Vertical line offset VOFF8 to VOFF0 = 007h; horizontal pixel offset HOFF10 to HOFF0 = 354h, FOFF = 1, FISET = 0 Line number (1st field) 621 622 623 active video Line number (2nd field) 309 24 310 311 312 equalization pulses 313 1 2 3 serration pulses 314 315 serration pulses 4 5 equalization pulses 316 317 318 equalization pulses 2 3 4 5 SAA7144HL 28 of 64 © Koninklijke Philips Electronics N.V. 2005. All rights reserved. LCR (VOFF = 007h; HOFF = 354h; FOFF = 1; FISET = 0) 625 Quadruple video input processor active video 624 equalization pulses xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx Philips Semiconductors 9397 750 14454 Product data sheet Table 14: Relationship of LCR to line numbers in 625 lines/50 Hz systems (part 2) Vertical line offset VOFF8 to VOFF0 = 007h; horizontal pixel offset HOFF10 to HOFF0 = 354h, FOFF = 1, FISET = 0 Line number (1st field) 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 nominal VBI-lines F1 Line number (2nd field) 319 320 321 322 323 324 325 326 327 328 329 330 331 332 333 334 335 10 11 12 13 14 15 16 17 18 19 20 21 22 nominal VBI-lines F2 LCR (VOFF = 007h; HOFF = 354h; 6 FOFF = 1; FISET = 0) Table 15: 7 8 9 24 25 active video 336 337 338 active video 23 24 Location of related programming registers Rev. 01 — 21 April 2005 Name Subaddress bits VOFF[8:0] 5Bh[4] and 5Ah[7:0] HOFF[10:0] 5Bh[2:0] and 59h[7:0] FOFF 5Bh[7] FISET 40h[7] SAA7144HL Quadruple video input processor 29 of 64 © Koninklijke Philips Electronics N.V. 2005. All rights reserved. SAA7144HL Philips Semiconductors Quadruple video input processor +255 +235 +128 white LUMINANCE 100 % +255 +240 blue 100 % +255 +240 red 100 % +212 blue 75 % +212 red 75 % +128 colorless +128 colorless CB-COMPONENT +16 0 black CR-COMPONENT +44 yellow 75 % +44 cyan 75 % +16 0 yellow 100 % +16 0 cyan 100 % 001aac241 001aac480 001aac481 Equations for modification to the Y-CB-CR levels via BCS control I2C-bus bytes BRIG, CONT and SATN. Luminance: CONT Y OUT = Int ---------------- × ( Y – 128 ) + BRIG 71 Chrominance: SATN UV OUT = Int --------------- × ( C R ,C B – 128 ) + 128 64 It should be noted that the resulting levels are limited to 1 to 254 in accordance with ITU-R BT 601/656 standard. a. Y output range. b. CB output range. c. CR output range. Fig 21. Y-CB-CR 4 : 2 : 2 levels on the 8-bit VPO-bus (data types 6 and 15). +255 +255 +209 white +199 LUMINANCE +71 +60 white LUMINANCE black black shoulder +60 SYNC 1 black shoulder = black SYNC sync bottom 1 sync bottom 001aac245 001aac244 VBI data levels are not dependent on BCS settings. a. For sources containing 7.5 IRE black level offset (e.g. NTSC M). b. For sources not containing black level offset. Fig 22. Raw data levels on the 8-bit VPO-bus (data type 8). 9397 750 14454 Product data sheet © Koninklijke Philips Electronics N.V. 2005. All rights reserved. Rev. 01 — 21 April 2005 30 of 64 SAA7144HL Philips Semiconductors Quadruple video input processor Table 16: Blanking period Y-CB-CR data format on the 8-bit VPO-bus (data types 6 and 15) Timing reference code ... 80 10 FF 00 00 SAV Table 17: 720 pixels Y-CB-CR 4 : 2 : 2 data CB0 Y0 CR0 Y1 CB2 Y2 ... CR718 Y719 Explanation SAV start of active video range; see Table 8 to Table 10 CBn U (B − Y) color difference component, pixel number n = 0, 2, 4 to 718 Yn Y (luminance) component, pixel number n = 0, 1, 2, 3 to 719 CRn V (R − Y) color difference component, pixel number n = 0, 2, 4 to 718 EAV end of active video range; see Table 8 to Table 10 Blanking period FF 00 00 EAV 80 10 ... Timing reference code Blanking period FF 00 00 EAV 80 10 ... Raw data format on the 8-bit VPO-bus (data type 8) Timing reference code ... 80 10 FF 00 00 SAV Table 19: Blanking period Explanation to Table 16 Name Table 18: Timing reference code Oversampled CVBS samples Y0 Y1 Y2 Y3 Y4 Y5 ... Yn − 1 Yn Explanation to Table 18 Name Explanation SAV start of raw sample range; see Table 8 to Table 10 Yi oversampled raw sample stream (CVBS signal), n = 0, 1, 2, 3 to n; n is programmable via HSB and HSS; see Section 9.3.6 and Section 9.3.7 EAV end of raw sample range; see Table 8 to Table 10 Table 20: Blanking period Sliced data format on the 8-bit VPO-bus (data types 0 to 5 and 8 to 14) Timing reference code Internal header Sliced data Timing reference code Blanking period ... 80 10 FF 00 00 SAV SDID DC IDI1 IDI2 DLN1 DHN1 ... DLNn DHNn FF 00 00 EAV 80 10 ... Table 21: Explanation to Table 20 Name Explanation SAV start of active data; see Table 8 to Table 10 SDID sliced data identification: NEP [1], EP [2], SDID5 to SDID0, freely programmable via I2C-bus subaddress 5Eh[5:0], e.g. to be used as source identifier DC Dword count: NEP [1], EP [2], DC5 to DC0; DC is inserted for software compatibility with old encoder devices, but does not represent any relevant information for SAA7144HL applications. DC describes the number of succeeding 32-bit words: DC = 1⁄4(C + n), where C = 2 (the two data identification bytes IDI1 and IDI2) and n = number of decoded bytes according to the chosen text standard. As the sliced data are transmitted nibble wise, the maximum number of bytes transmitted (NBT) starting at IDI1 results to: NBS = (DC × 8) − 2 DC can vary between 1 and 11, depending on the selected data type. Note that the number of bytes actually transmitted can be less than NBT for two reasons: 1. result of DC would result to a non-integer value (DC is always rounded up) 2. standard not recognized (wrong standard or poor input signal) IDI1 internal data identification 1: OP [3], FID (field 1 = 0, field 2 = 1), LineNumber8 to LineNumber3 9397 750 14454 Product data sheet © Koninklijke Philips Electronics N.V. 2005. All rights reserved. Rev. 01 — 21 April 2005 31 of 64 SAA7144HL Philips Semiconductors Quadruple video input processor Explanation to Table 20 …continued Table 21: Name Explanation IDI2 internal data identification 2: OP [3], LineNumber2 to LineNumber0, DataType3 to DataType0; see Table 7 DLNn sliced data LOW nibble, format: NEP [1], EP [2], bits 3 to 0, 1, 1 DLHn sliced data HIGH nibble, format: NEP [1], EP [2], bits 7 to 4, 1, 1 EAV end of active data; see Table 8 to Table 10 [1] Inverted EP (bit 7); for EP see Table note 2. [2] Even parity (bit 6) of bits 5 to 0. [3] Odd parity (bit 7) of bits 6 to 0. 9. I2C-bus description 9.1 I2C-bus format S SLAVE ADDRESS W ACK-s SUBADDRESS ACK-s ACK-s DATA data transferred (n bytes + acknowledge) P mhb339 Fig 23. Write procedure. S SLAVE ADDRESS W ACK-s SUBADDRESS ACK-s Sr SLAVE ADDRESS R ACK-s DATA ACK-m data transferred (n bytes + acknowledge) P mhb340 Fig 24. Read procedure (combined format). 9397 750 14454 Product data sheet © Koninklijke Philips Electronics N.V. 2005. All rights reserved. Rev. 01 — 21 April 2005 32 of 64 SAA7144HL Philips Semiconductors Quadruple video input processor Table 22: Description of I2C-bus format [1] Code Description S START condition Sr repeated START condition Slave address W 0100 1010 (= 4Ah) for decoder cores B and D 0100 1000 (= 48h) for decoder cores A and C Slave address R 0100 1011 (= 4Bh) for decoder cores B and D 0100 1001 (= 49h) for decoder cores A and C ACK-s acknowledge generated by the slave ACK-m acknowledge generated by the master Subaddress subaddress byte; see Table 24 Data data byte; see Table 24 and Table note 2 P STOP condition X = LSB slave address read/write control bit; X = 0, order to write (the circuit is slave receiver); X = 1, order to read (the circuit is slave transmitter) [1] The SAA7144HL supports the fast mode I2C-bus specification extension (data rate up to 400 kbit/s). [2] If more than one byte DATA is transmitted the subaddress pointer is automatically incremented. 9.2 I2C-bus register description Table 23: Register subaddresses map Subaddress Description Access Reference 00h chip version read only Section 9.3.1 01h to 04h front-end part read and write Section 9.3.2 to Section 9.3.5 05h reserved - 06h to 11h decoder part read and write Section 9.3.6 to Section 9.3.17 12h reserved - 13h decoder part read and write Section 9.3.18 14h to 1Eh reserved - - 1Fh video decoder status byte read only Section 9.3.19 20h to 3Fh reserved - - 40h to 5Bh general purpose data slicer read and write Section 9.3.20 to Section 9.3.25 5Ch for testability - - 5Dh reserved - - 5Eh sliced data identification code read and write Section 9.3.26 5Fh reserved - 60h to 62h general purpose data slicer status read only Section 9.3.27 and Section 9.3.28 63h to FFh reserved - - 9397 750 14454 Product data sheet - - © Koninklijke Philips Electronics N.V. 2005. All rights reserved. Rev. 01 — 21 April 2005 33 of 64 xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx Philips Semiconductors 9397 750 14454 Product data sheet Table 24: I2C-bus receiver/transmitter overview Rev. 01 — 21 April 2005 7 6 5 4 3 2 1 0 Chip version (read only) 00h ID07 ID06 ID05 ID04 - - - - Increment delay 01h [1] [1] [1] [1] IDEL3 IDEL2 IDEL1 IDEL0 Analog control 1 02h FUSE1 FUSE0 GUDL1 GUDL0 MODE3 MODE2 MODE1 MODE0 Analog control 2 03h [1] HLNRS VBSL WPOFF HOLDG GAFIX [1] GAI18 Analog control 3 04h GAI17 GAI16 GAI15 GAI14 GAI13 GAI12 GAI11 GAI10 Reserved 05h [1] [1] [1] [1] [1] [1] [1] [1] Horizontal sync begin 06h HSB7 HSB6 HSB5 HSB4 HSB3 HSB2 HSB1 HSB0 Horizontal sync stop 07h HSS7 HSS6 HSS5 HSS4 HSS3 HSS2 HSS1 HSS0 Sync control 08h AUFD FSEL FOET HTC1 HTC0 HPLL VNOI1 VNOI0 Luminance control 09h BYPS PREF BPSS1 BPSS0 VBLB UPTCV APER1 APER0 Luminance brightness 0Ah BRIG7 BRIG6 BRIG5 BRIG4 BRIG3 BRIG2 BRIG1 BRIG0 Luminance contrast 0Bh CONT7 CONT6 CONT5 CONT4 CONT3 CONT2 CONT1 CONT0 Chrominance saturation 0Ch SATN7 SATN6 SATN5 SATN4 SATN3 SATN2 SATN1 SATN0 Chrominance hue control 0Dh HUEC7 HUEC6 HUEC5 HUEC4 HUEC3 HUEC2 HUEC1 HUEC0 Chrominance control 0Eh [1] CSTD2 CSTD1 CSTD0 DCCF FCTC CHBW1 CHBW0 Chrominance gain control 0Fh ACGC CGAIN6 CGAIN5 CGAIN4 CGAIN3 CGAIN2 CGAIN1 CGAIN0 Format/delay control 10h OFTS1 OFTS0 HDEL1 HDEL0 VRLN YDEL2 YDEL1 YDEL0 Output control 1 11h [1] [1] [1] [1] OEYC [1] VIPB COLO Reserved 12h [1] [1] [1] [1] [1] [1] [1] [1] Output control 3 13h ADLSB [1] [1] OLDSB [1] [1] [1] [1] Reserved 14h to 1Eh [1] [1] [1] [1] [1] [1] [1] [1] Decoder status byte (read only, OLDSB = 0) 1Fh INTL HLVLN FIDT GLIMT GLIMB WIPA COPRO RDCAP Decoder status byte (read only, OLDSB = 1) 1Fh INTL HLCK FIDT GLIMT GLIMB WIPA SLTCA CODE Reserved 20h to 3Fh [1] [1] [1] [1] [1] [1] [1] [1] CLKSEL1 CLKSEL0 [1] Slicer control 40h FISET HAM_N FCE HUNT_N [1] Line control register 2 41h LCR02_7 LCR02_6 LCR02_5 LCR02_4 LCR02_3 LCR02_2 LCR02_1 LCR02_0 Line control register 3 to 23 42h to 56h LCRN_7 LCRN_6 LCRN_5 LCRN_4 LCRN_3 LCRN_2 LCRN_1 LCRN_0 Line control register 24 57h LCR24_7 LCR24_6 LCR24_5 LCR24_4 LCR24_3 LCR24_2 LCR24_1 LCR24_0 Framing code 58h FC7 FC6 FC5 FC4 FC3 FC2 FC1 FC0 SAA7144HL Subaddress Quadruple video input processor 34 of 64 © Koninklijke Philips Electronics N.V. 2005. All rights reserved. Register function xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx I2C-bus receiver/transmitter overview …continued Register function Subaddress 7 6 5 4 3 2 1 0 Horizontal offset 59h HOFF7 HOFF6 HOFF5 HOFF4 HOFF3 HOFF2 HOFF1 HOFF0 Vertical offset 5Ah VOFF7 VOFF6 VOFF5 VOFF4 VOFF3 VOFF2 VOFF1 VOFF0 [1] VOFF8 [1] HOFF10 HOFF9 HOFF8 Horizontal offset (MSBs), vertical offset (MSB) and field offset 5Bh FOFF [1] For testability 5Ch [1] [1] [1] [1] [1] [1] [1] [1] Reserved 5Dh [1] [1] [1] [1] [1] [1] [1] [1] Sliced data identification code 5Eh [1] [1] SDID5 SDID4 SDID3 SDID2 SDID1 SDID0 Reserved 5Fh [1] [1] [1] [1] [1] [1] [1] [1] Slicer status 1 (read only) 60h - FC8V FC7V VPSV PPV CCV - - Slicer status 2 (read only) 61h - - F21_N LN8 LN7 LN6 LN5 LN4 Slicer status 3 (read only) 62h LN3 LN2 LN1 LN0 DT3 DT2 DT1 DT0 Reserved 63h to FFh [1] [1] [1] [1] [1] [1] [1] [1] Rev. 01 — 21 April 2005 [1] Philips Semiconductors 9397 750 14454 Product data sheet Table 24: All unused control bits must be programmed with logic 0 to ensure compatibility to future enhancements. SAA7144HL Quadruple video input processor 35 of 64 © Koninklijke Philips Electronics N.V. 2005. All rights reserved. SAA7144HL Philips Semiconductors Quadruple video input processor 9.3 I2C-bus detail The I2C-bus receiver slave address is 48h/49h and 4Ah/4Bh. Subaddresses 05h, 12h, 14h to 1Eh, 20h to 3Fh, 5Ch, 5Dh, 5Fh and 63h to FFh are reserved. 9.3.1 Subaddress 00h (read only register) Table 25: Chip version Function Logic levels ID07 ID06 ID05 ID04 Chip Version (CV) CV3 CV2 CV1 CV0 9.3.2 Subaddress 01h Table 26: Horizontal increment delay Function IDEL3 IDEL2 IDEL1 IDEL0 No update 1 1 1 1 Minimum delay 1 1 1 0 Recommended position 1 0 0 0 Maximum delay 0 0 0 0 The programming of the horizontal increment delay is used to match internal processing delays to the delay of the ADC. Use recommended position only. 9.3.3 Subaddress 02h Table 27: Analog control 1 - bit description Bit Symbol Description 7 and 6 FUSE[1:0] analog function select; see Figure 6 00 = amplifier plus anti-alias filter bypassed 01 = amplifier plus anti-alias filter bypassed 10 = amplifier active 11 = amplifier plus anti-alias filter active 5 and 4 GUDL[1:0] update hysteresis for 9-bit gain; see Figure 7 00 = off 01 = ±1 LSB 10 = ±2 LSB 11 = ±3 LSB 3 to 0 MODE[3:0] channel input selector 0000 = select CVBS (automatic gain) from AI11; see Figure 25 0001 = select CVBS (automatic gain) from AI12; see Figure 25 XXXX = reserved; see Table note 1 [1] X = don’t care. 9397 750 14454 Product data sheet © Koninklijke Philips Electronics N.V. 2005. All rights reserved. Rev. 01 — 21 April 2005 36 of 64 SAA7144HL Philips Semiconductors Quadruple video input processor AI12 ADC AI11 MODE[3:0] 001aab319 Fig 25. Mode switch for video inputs AI11 or AI12. 9.3.4 Subaddress 03h Table 28: Analog control 2 - bit description Bit Symbol 7 - not used; has to be set to logic 0 6 HLNRS HL not reference select Description 0 = normal clamping if decoder is in unlocked state 1 = reference select if decoder is in unlocked state 5 VBSL AGC hold during vertical blanking period 0 = short vertical blanking (AGC disabled during equalization and serration pulses) 1 = long vertical blanking (AGC disabled from start of pre-equalization pulses until start of active video (line 22 for 60 Hz, line 24 for 50 Hz) 4 WPOFF white peak off 0 = white peak control active 1 = white peak off 3 HOLDG automatic gain control integration 0 = AGC active 1 = AGC integration hold (freeze) 2 GAFIX gain control fix 0 = automatic gain controlled by MODE[3:0] 1 = gain is user programmable via GAI1 1 - not used; has to be set to logic 0 0 GAI18 sign bit of gain control; see Table 29 9397 750 14454 Product data sheet © Koninklijke Philips Electronics N.V. 2005. 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Rev. 01 — 21 April 2005 37 of 64 SAA7144HL Philips Semiconductors Quadruple video input processor 9.3.5 Subaddress 04h Table 29: Analog control 3; static gain control Decimal value Gain (dB) Sign bit Control bits 7 to 0 GAI18 GAI17 GAI16 GAI15 GAI14 GAI13 GAI12 GAI11 GAI10 0... ≈−3 0 0 0 0 0 0 0 0 0 ...117... ≈0 0 0 1 1 1 0 1 0 1 ...511 ≈6 1 1 1 1 1 1 1 1 1 HSB5 HSB4 HSB3 HSB2 HSB1 HSB0 9.3.6 Subaddress 06h Table 30: Horizontal sync begin Delay time (step size = 8/LLC) Control bits 7 to 0 −128...−109 (50 Hz) forbidden (outside available central counter range) HSB7 HSB6 −128...−108 (60 Hz) −108 (50 Hz)... 1 0 0 1 0 1 0 0 −107 (60 Hz)... 1 0 0 1 0 1 0 1 ...108 (50 Hz) 0 1 1 0 1 1 0 0 ...107 (60 Hz) 0 1 1 0 1 0 1 1 109...127 (50 Hz) forbidden (outside available central counter range) 108...127 (60 Hz) Recommended value for raw data type; see Figure 22 1 1 1 0 1 0 0 1 HSS5 HSS4 HSS3 HSS2 HSS1 HSS0 9.3.7 Subaddress 07h Table 31: Horizontal sync stop Delay time (step size = 8/LLC) Control bits 7 to 0 −128...−109 (50 Hz) forbidden (outside available central counter range) HSS7 HSS6 −128...−108 (60 Hz) −108 (50 Hz)... 1 0 0 1 0 1 0 0 −107 (60 Hz)... 1 0 0 1 0 1 0 1 ...108 (50 Hz) 0 1 1 0 1 1 0 0 ...107 (60 Hz) 0 1 1 0 1 0 1 1 109...127 (50 Hz) forbidden (outside available central counter range) 1 0 1 108...127 (60 Hz) Recommended value for raw data type; see Figure 22 0 0 0 0 9397 750 14454 Product data sheet 1 © Koninklijke Philips Electronics N.V. 2005. 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Rev. 01 — 21 April 2005 38 of 64 SAA7144HL Philips Semiconductors Quadruple video input processor 9.3.8 Subaddress 08h Table 32: Sync control - bit description Bit Symbol Description 7 AUFD automatic field detection 0 = field state directly controlled via FSEL 1 = automatic field detection 6 FSEL field selection 0 = 50 Hz, 625 lines 1 = 60 Hz, 525 lines 5 FOET forced ODD/EVEN toggle 0 = ODD/EVEN signal toggles only with interlaced source 1 = ODD/EVEN signal toggles fieldwise even if source is non-interlaced 4 and 3 HTC[1:0] horizontal time constant selection 00 = TV mode (recommended for poor quality TV signals only; do not use for new applications) 01 = VTR mode (recommended if a deflection control circuit is directly connected to SAA7144HL) 10 = reserved 11 = fast locking mode (recommended setting) 2 HPLL horizontal PLL 0 = PLL closed 1 = PLL open; horizontal frequency fixed 1 and 0 VNOI[1:0] vertical noise reduction 00 = normal mode (recommended setting) 01 = fast mode [applicable for stable sources only; automatic field detection (AUFD) must be disabled] 10 = free running mode 11 = vertical noise reduction bypassed 9.3.9 Subaddress 09h Table 33: Luminance control - bit description Bit Symbol Description 7 BYPS chrominance trap bypass 0 = chrominance trap active; default for CVBS mode 1 = chrominance trap bypassed 6 PREF prefilter active; see Figure 11 to Figure 16 0 = bypassed 1 = active 5 and 4 BPSS[1:0] aperture band-pass (center frequency) 00 = center frequency is 4.1 MHz 01 = center frequency is 3.8 MHz; see Table note 1 10 = center frequency is 2.6 MHz; see Table note 1 11 = center frequency is 2.9 MHz; see Table note 1 9397 750 14454 Product data sheet © Koninklijke Philips Electronics N.V. 2005. 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Rev. 01 — 21 April 2005 39 of 64 SAA7144HL Philips Semiconductors Quadruple video input processor Table 33: Luminance control - bit description …continued Bit Symbol Description 3 VBLB vertical blanking luminance bypass 0 = active luminance processing 1 = chrominance trap and peaking stage are disabled during VBI lines determined by VREF = 0; see Table 41 2 UPTCV update time interval for analog AGC value 0 = horizontal update (once per line) 1 = vertical update (once per field) 1 and 0 APER[1:0] aperture factor; see Figure 11 to Figure 16 00 = aperture factor is 0 01 = aperture factor is 0.25 10 = aperture factor is 0.5 11 = aperture factor is 1.0 [1] Not to be used with bypassed chrominance trap. 9.3.10 Subaddress 0Ah Table 34: Luminance brightness control Offset Control bits 7 to 0 BRIG7 BRIG6 BRIG5 BRIG4 BRIG3 BRIG2 BRIG1 BRIG0 255 (bright) 1 1 1 1 1 1 1 1 128 (CCIR level) 1 0 0 0 0 0 0 0 0 (dark) 0 0 0 0 0 0 0 0 CONT5 CONT4 CONT3 CONT2 CONT1 CONT0 9.3.11 Subaddress 0Bh Table 35: Luminance contrast control Gain Control bits 7 to 0 CONT7 CONT6 1.999 (maximum) 0 1 1 1 1 1 1 1 1.109 (CCIR level) 0 1 0 0 0 1 1 1 1.0 0 1 0 0 0 0 0 0 0 (luminance off) 0 0 0 0 0 0 0 0 −1 (inverse luminance) 1 1 0 0 0 0 0 0 −2 (inverse luminance) 1 0 0 0 0 0 0 0 9397 750 14454 Product data sheet © Koninklijke Philips Electronics N.V. 2005. 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Rev. 01 — 21 April 2005 40 of 64 SAA7144HL Philips Semiconductors Quadruple video input processor 9.3.12 Subaddress 0Ch Table 36: Chrominance saturation control Gain Control bits 7 to 0 SATN7 SATN6 SATN5 SATN4 SATN3 SATN2 SATN1 SATN0 1.999 (maximum) 0 1 1 1 1 1 1 1 1.0 (CCIR level) 0 1 0 0 0 0 0 0 0 (color off) 0 0 0 0 0 0 0 0 −1 (inverse chrominance) 1 1 0 0 0 0 0 0 −2 (inverse chrominance) 1 0 0 0 0 0 0 0 9.3.13 Subaddress 0Dh Table 37: Chrominance hue control Hue phase (deg) Control bits 7 to 0 HUEC7 HUEC6 HUEC5 HUEC4 HUEC3 HUEC2 HUEC1 HUEC0 +178.6... 0 1 1 1 1 1 1 1 ...0... 0 0 0 0 0 0 0 0 ...−180 1 0 0 0 0 0 0 0 9.3.14 Subaddress 0Eh Table 38: Chrominance control - bit description Bit Symbol Description 50 Hz 60 Hz 7 - not used; has to be set to logic 0 6 to 4 CSTD[2:0] color standard selection 000 = PAL BGHIN NTSC M (or NTSC-Japan with special level adjustment: brightness subaddress 0Ah = 95h; contrast subaddress 0Bh = 48h) 001 = NTSC 4.43 (50 Hz) PAL 4.43 (60 Hz) 010 = combination-PAL N NTSC 4.43 (60 Hz) 011 = NTSC N PAL M 100 = reserved; do not use 101 = SECAM reserved 110 = reserved; do not use 111 = reserved; do not use 3 DCCF disable chrominance comb filter 0 = chrominance comb filter on (during lines determined by VREF = 1; see Table 41) 1 = chrominance comb filter permanently off 2 FCTC fast color time constant 0 = nominal time constant 1 = fast time constant 9397 750 14454 Product data sheet © Koninklijke Philips Electronics N.V. 2005. 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Rev. 01 — 21 April 2005 41 of 64 SAA7144HL Philips Semiconductors Quadruple video input processor Table 38: Chrominance control - bit description …continued Bit Symbol Description 50 Hz 1 and 0 CHBW[1:0] 60 Hz chrominance bandwidth 00 = small bandwidth (≈ 620 kHz) 01 = nominal bandwidth (≈ 800 kHz) 10 = medium bandwidth (≈ 920 kHz) 11 = wide bandwidth (≈ 1000 kHz) 9.3.15 Subaddress 0Fh Table 39: Chrominance gain control - bit description Bit Symbol Description 7 ACGC automatic chrominance gain control 0 = on 1 = programmable gain via CGAIN[6:0] 6 to 0 CGAIN[6:0] chrominance gain value (if AGC is set to logic 1) 0000000 = minimum gain (0.5) 0100100 = nominal gain (1.125) 1111111 = maximum gain (7.5) 9.3.16 Subaddress 10h Table 40: Format/delay control - bit description Bit Symbol Description 7 and 6 OFTS[1:0] output format selection; V-flag generation in SAV/EAV codes; see Table 9 and Table 10 00 = standard ITU-R BT 656 format 01 = V-flag in SAV/EAV is generated by VREF 10 = V-flag in SAV/EAV is generated by data type 11 = reserved 5 and 4 HDEL[1:0] fine position of HS 00 = 0 × 2/LLC 01 = 1 × 2/LLC 10 = 2 × 2/LLC 11 = 3 × 2/LLC 3 VRLN VREF pulse position and length; see Table 41 2 to 0 YDEL[2:0] luminance delay compensation (steps in 2/LLC) 100 = −4... × 2/LLC 000 = ...0... × 2/LLC 011 = ...3 × 2/LLC 9397 750 14454 Product data sheet © Koninklijke Philips Electronics N.V. 2005. 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Rev. 01 — 21 April 2005 42 of 64 SAA7144HL Philips Semiconductors Quadruple video input processor Table 41: VREF pulse position and length VRLN SA 10 (bit 3) VRLN VREF at 60 Hz 525 lines 0 Length 1 240 Line number VREF at 50 Hz 625 lines 0 242 1 286 288 first last first last first last first last Field 1 [1] 19 (22) 258 (261) 18 (21) 259 (262) 24 309 23 310 Field 2 [1] 282 (285) 521 (524) 281 (284) 522 (525) 337 622 336 623 [1] The numbers given in parenthesis refer to ITU line counting. 9.3.17 Subaddress 11h Table 42: Output control 1 - bit description Bit Symbol Description 7 to 4 - not used; have to be set to logic 0 3 OEYC output enable Y-CB-CR data 0 = VPO-bus high-impedance 1 = output VPO-bus active 2 - not used; has to be set to logic 0 1 VIPB Y-CB-CR decoder bypassed 0 = processed data to VPO output 1 = ADC data to VPO output; dependent on mode settings 0 COLO color on 0 = automatic color killer 1 = color forced on 9.3.18 Subaddress 13h Table 43: Output control 3 - bit description Bit Symbol Description 7 ADLSB analog-to-digital converter output bits on VPO7 to VPO0 in bypass mode (VIPB = 1, used for test purposes); see Table note 1 0 = AD8 to AD1 (MSBs) on VPO7 to VPO0 1 = AD7 to AD0 (LSBs) on VPO7 to VPO0 6 and 5 - not used; have to be set to logic 0 4 OLDSB selection bit for status byte functionality 0 = default status information; see Table 44 1 = old status information, for compatibility reasons; see Table 44 3 to 0 [1] - not used; have to be set to logic 0 Video input selection via MODE[3:0] (subaddress 02h; see Figure 25). 9397 750 14454 Product data sheet © Koninklijke Philips Electronics N.V. 2005. All rights reserved. Rev. 01 — 21 April 2005 43 of 64 SAA7144HL Philips Semiconductors Quadruple video input processor 9.3.19 Subaddress 1Fh (read only register) Table 44: Status byte - bit description Bit Symbol Description 7 INTL status bit for interlace detection 0 = non-interlaced 1 = interlaced 6 HLCK status bit for locked horizontal frequency (OLDSB = 1) 0 = locked 1 = unlocked HLVLN status bit for horizontal/vertical loop (OLDSB = 0) 0 = locked 1 = unlocked 5 FIDT identification bit for detected field frequency 0 = 50 Hz 1 = 60 Hz 4 GLIMT gain value for active luminance channel is limited [max (top)]; active HIGH 3 GLIMB gain value for active luminance channel is limited [min (bottom)]; active HIGH 2 WIPA white peak loop is activated; active HIGH 1 SLTCA slow time constant active in WIPA mode; active HIGH (OLDSB = 1) COPRO Macrovision® copy protection detection according to Macrovision® detect specification revision 7.01 (OLDSB = 0). CODE color signal in accordance with selected standard has been detected; active HIGH (OLDSB = 1) RDCAP ready for capture (all internal loops locked); active HIGH (OLDSB = 0) 0 9.3.20 Subaddress 40h Table 45: Slicer control - bit description Bit Symbol Description 7 FISET field size select 0 = 50 Hz field rate 1 = 60 Hz field rate 6 HAM_N hamming check 0 = hamming check for 2 bytes after framing code, dependent on data type (default) 1 = no hamming check 5 FCE framing code error 0 = one framing code error allowed 1 = no framing code errors allowed 4 HUNT_N amplitude searching 0 = amplitude searching active (default) 1 = amplitude searching stopped 3 - not used; has to be set to logic 0 9397 750 14454 Product data sheet © Koninklijke Philips Electronics N.V. 2005. All rights reserved. Rev. 01 — 21 April 2005 44 of 64 SAA7144HL Philips Semiconductors Quadruple video input processor Table 45: Slicer control - bit description …continued Bit Symbol Description 2 and 1 CLKSEL[1:0] data slicer clock selection 00 = reserved 01 = 13.5 MHz (default) 10 = reserved 11 = reserved 0 - not used; has to be set to logic 0 9.3.21 Subaddresses 41h to 57h Table 46: LCR register 2 to 24; see Table 7 LCR register 2 to 24 (41h to 57h) Framing code Bit 7 to 4 DT3 to DT0 [1] Bit 3 to 0 DT3 to DT0 [1] WST625 teletext EuroWST, CCST 27h 0000 0000 CC625 European closed caption 001 0001 0001 VPS video programming service 9951h 0010 0010 WSS wide screen signalling bits 1E3C1Fh 0011 0011 WST525 US teletext (WST) 27h 0100 0100 CC525 US closed caption (line 21) 001 0101 0101 Test line video component signal, VBI region - 0110 0110 Intercast™ oversampled CVBS data - 0111 0111 General text teletext programmable 1000 1000 VITC625 VITC/EBU time codes (Europe) programmable 1001 1001 VITC/SMPTE time codes (USA) programmable 1010 1010 Reserved reserved - 1011 1011 NABTS US NABTS - 1100 1100 Japtext MOJI (Japanese) programmable (A7h) 1101 1101 JFS Japanese format switch (L20/22) programmable 1110 1110 Active video video component signal, active video region (default) - 1111 1111 [1] The assignment of the upper and lower nibbles to the corresponding field depends on the setting of FOFF (subaddress 5Bh, bit 7); see Table 47. Table 47: Setting of FOFF (subaddress 5Bh, bit 7) FOFF Bit 7 to 4 Bit 3 to 0 0 field 1 field 2 1 field 2 field 1 9.3.22 Subaddress 58h Table 48: Framing code - bit description Bit Symbol Description 7 to 0 FC[7:0] framing code for programmable data types; 40h (default) 9397 750 14454 Product data sheet © Koninklijke Philips Electronics N.V. 2005. All rights reserved. Rev. 01 — 21 April 2005 45 of 64 SAA7144HL Philips Semiconductors Quadruple video input processor 9.3.23 Subaddresses 59h and 5Bh Table 49: Horizontal offset - bit description Bit Symbol Description Subaddress 5Bh 2 to 0 HOFF[10:8] horizontal offset; recommended value: 03h Subaddress 59h 7 to 0 HOFF[7:0] horizontal offset; recommended value: 54h 9.3.24 Subaddresses 5Ah and 5Bh Table 50: Vertical offset - bit description Bit Symbol Description Subaddress 5Bh 4 VOFF8 vertical offset Subaddress 5Ah 7 to 0 VOFF[7:0] vertical offset 00h = minimum value 0, if VOFF8 = 0 38h = maximum value 312, if VOFF8 = 1 07h = value for 50 Hz 625 lines input, if VOFF8 = 0 0Ah = value for 60 Hz 525 lines input, if VOFF8 = 0 9.3.25 Subaddress 5Bh Table 51: Field offset, MSBs for vertical and horizontal offsets - bit description Bit Symbol Description 7 FOFF field offset 0 = no modification of internal field indicator 1 = invert field indicator (even/odd; default) 6 and 5 - not used; have to be set to logic 0 4 VOFF8 vertical offset; see Table 50 3 - not used; has to be set to logic 0 2 to 0 HOFF[10:8] horizontal offset; see Table 49 9.3.26 Subaddress 5Eh Table 52: Sliced data identification code - bit description Bit Symbol Description 7 and 6 - not used; have to be set to logic 0 5 to 0 SDID[5:0] sliced data identification code; SDID[5:0] = 000000 (default) 9397 750 14454 Product data sheet © Koninklijke Philips Electronics N.V. 2005. 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Rev. 01 — 21 April 2005 46 of 64 SAA7144HL Philips Semiconductors Quadruple video input processor 9.3.27 Subaddress 60h (read only register) Table 53: Slicer status 1 - bit description Bit Symbol Description 7 - not used; has to be set to logic 0 6 and 5 FC8V and FC7V framing code valid 00 = no framing code in the last frame 01 = framing code with 1 error detected in the last frame 1X [1] = framing code without errors detected in the last frame 4 VPSV VPS valid 0 = no VPS in the last frame 1 = VPS detected 3 PPV PALplus valid 0 = no PALplus in the last frame 1 = PALplus detected 2 CCV closed caption valid 0 = no closed caption in the last frame 1 = closed caption detected 1 and 0 [1] - not used; have to be set to logic 0 X = don’t care. 9.3.28 Subaddresses 61h and 62h (read only register) Table 54: Slicer status 2 and 3 - bit description Bit Symbol Description Subaddress 61h 7 and 6 - not used; have to be set to logic 0 5 F21_N internal used slicer status bit 4 to 0 LN[8:4] line number Subaddress 62h 7 to 4 LN[3:0] line number 3 to 0 DT[3:0] data type according to Table 7 10. I2C-bus start set-up The given values force the following behavior of the SAA7144HL: • The analog input AI11 expects a signal in CVBS format; analog anti-alias filter and AGC active • Automatic field detection enabled, PAL BDGHI or NTSC M standard expected • Standard ITU-R BT 656 output format enabled, VBI data slicer disabled; see Table 55 Table note 2 • Contrast, brightness and saturation control in accordance with ITU standards • Chrominance processing with nominal bandwidth (800 kHz). 9397 750 14454 Product data sheet © Koninklijke Philips Electronics N.V. 2005. All rights reserved. Rev. 01 — 21 April 2005 47 of 64 SAA7144HL Philips Semiconductors Quadruple video input processor Table 55: I2C-bus start set-up values Subaddress Function (hexadecimal) Name [1] 00 chip version ID07 to ID04 read only 01 increment delay X, X, X, X, IDEL[3:0] 0 0 0 0 1 0 0 0 08 02 analog control 1 FUSE[1:0], GUDL[1:0], MODE[3:0] 1 0 0 0 0 0 0 0 80 03 analog control 2 X, HLNRS, VBSL, WPOFF, HOLDG, 0 0 1 1 0 0 0 1 31 GAFIX, X, GAI18 04 analog control 3 GAI1[7:0] 05 reserved 06 horizontal sync begin HSB[7:0] 1 1 1 0 1 0 0 1 E9 07 horizontal sync stop HSS[7:0] 0 0 0 0 1 1 0 1 0D 08 sync control AUFD, FSEL, FOET, HTC[1:0], HPLL, VNOI[1:0] 1 0 0 1 1 0 0 0 98 09 luminance control BYPS, PREF, BPSS[1:0], VBLB, UPTCV, APER[1:0] 0 0 0 0 0 0 0 1 01 0A luminance brightness BRIG[7:0] 1 0 0 0 0 0 0 0 80 0B luminance contrast CONT[7:0] 0 1 0 0 0 1 1 1 47 0C chrominance saturation SATN[7:0] 0 1 0 0 0 0 0 0 40 0D chrominance hue control HUEC[7:0] 0 0 0 0 0 0 0 0 00 0E chrominance control X, CSTD[2:0], DCCF, FCTC, CHBW[1:0] 0 0 0 0 0 0 0 1 01 0F chrominance gain control ACGC, CGAIN[6:0] 0 0 1 0 1 0 1 0 2A 10 format/delay control OFTS[1:0], HDEL[1:0], VRLN, YDEL[2:0] 0 0 0 0 0 0 0 0 00 11 output control 1 X, X, X, X, OEYC, X, VIPB, COLO 0 0 0 0 1 0 0 0 0C 12 reserved Values (binary) Start 7 6 5 4 3 2 1 0 (hexadecimal) 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 1 01 13 output control 3 14 to 1E reserved ADLSB, X, X, OLDSB, X, X, X, X 1F decoder status byte 20 to 3F reserved 40 slicer control 41 to 57 line control register 2 to 24 LCRn[7:0] 1 1 1 1 1 1 1 1 FF [2] 58 programmable framing code FC[7:0] 0 0 0 0 0 0 0 0 00 59 horizontal offset for slicer HOFF[7:0] 0 1 0 1 0 1 0 0 54 [2] 5A vertical offset for slicer VOFF[7:0] 0 0 0 0 0 1 1 1 07 [2] 5B field offset and MSBs for horizontal and vertical offset FOFF, X, X, VOFF8, X, HOFF[10:8] 1 0 0 0 0 0 1 1 83 [2] 5C and 5D reserved 5E sliced data identification code 5F reserved 0 0 0 0 0 0 0 0 00 INTL, HLVLN, FIDT, GLIMT, GLIMB, read only WIPA, COPRO, RDCAP 0 0 0 0 0 0 0 0 00 FISET, HAM_N, FCE, HUNT_N, X, CLKSEL[1:0], X 0 0 0 0 0 0 1 0 02 [2] 0 0 0 0 0 0 0 0 00 X, X, SDID[5:0] 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 00 9397 750 14454 Product data sheet 0 0 0 0 0 0 0 0 00 © Koninklijke Philips Electronics N.V. 2005. All rights reserved. Rev. 01 — 21 April 2005 48 of 64 SAA7144HL Philips Semiconductors Quadruple video input processor Table 55: I2C-bus start set-up values …continued Subaddress Function (hexadecimal) Name [1] 60 slicer status 1 -, FC8V, FC7V, VPSV, PPV, CCV, -, - read only 61 slicer status 2 -, -, F21_N, LN[8:4] 62 slicer status 3 LN[3:0], DT[3:0] 63 to FF reserved Start 7 6 5 4 3 2 1 0 (hexadecimal) read only read only 0 0 0 0 0 0 0 0 00 [1] All X values must be set to logic 0. For SECAM decoding set register 0Eh to 50h. [2] For proper data slicer programming refer to Table 11 to Table 14 and Table 7. 9397 750 14454 Product data sheet Values (binary) © Koninklijke Philips Electronics N.V. 2005. All rights reserved. Rev. 01 — 21 April 2005 49 of 64 SAA7144HL Philips Semiconductors Quadruple video input processor 11. Limiting values Table 56: Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). All ground pins connected together and all supply pins connected together. Symbol Parameter Conditions Min Max Unit VDDD digital supply voltage −0.5 +4.6 V VDDA analog supply voltage −0.5 +4.6 V Vi(a) analog input voltage −0.5 VDDA + 0.5 (4.6 max) V Vo(a) analog output voltage −0.5 VDDA + 0.5 V Vi(d) digital input voltage outputs in 3-state −0.5 +5.5 V Vo(d) digital output voltage outputs active −0.5 VDDD + 0.5 V ∆VSS voltage difference between VSSA(all) and VSS(all) - 100 mV Tstg storage temperature −65 +150 °C Tamb ambient temperature 0 70 °C Tamb(bias) ambient temperature under bias electrostatic discharge voltage Vesd [1] Class 2 according to JESD22-A114-B. [2] Class B according to EIA/JESD22-A115-A. −10 +80 °C human body model [1] - ±2000 V machine model [2] - ±200 V 12. Thermal characteristics Table 57: Thermal characteristics Symbol Parameter Conditions Typ Unit Rth(j-a) thermal resistance from junction to ambient in free air 30 K/W 13. Characteristics Table 58: Characteristics VDDD = 3.0 V to 3.6 V; VDDA = 3.1 V to 3.5 V; Tamb = 25 °C; unless otherwise specified. Symbol Parameter Conditions Min Typ Max Unit 3.0 3.3 3.6 V - 125 165 mA Supplies VDDD digital supply voltage IDDD digital supply current (IDDDI + IDDDE) VDDA analog supply voltage 3.1 3.3 3.5 V IDDA analog supply current (IDDA0 + IDDA1) - 210 250 mA PA+D analog and digital power - 1.1 - W - ±8 - µA all outputs unloaded Analog part Iclamp clamping current VI = 0.9 V DC 9397 750 14454 Product data sheet © Koninklijke Philips Electronics N.V. 2005. All rights reserved. Rev. 01 — 21 April 2005 50 of 64 SAA7144HL Philips Semiconductors Quadruple video input processor Table 58: Characteristics …continued VDDD = 3.0 V to 3.6 V; VDDA = 3.1 V to 3.5 V; Tamb = 25 °C; unless otherwise specified. Symbol Parameter Conditions Min Typ Max Unit Vi(p-p) input voltage (peak-to-peak value) for normal video levels 1 V (p-p), termination 18/56 Ω and AC coupling required; coupling capacitor = 47 nF 0.5 0.7 1.4 V Zi input impedance clamping current off 200 - - kΩ Ci input capacitance - - 10 pF αcs channel crosstalk between inputs of one instance AI11_x and AI12_x (e.g. AI11_A to AI12_A) fi = 5 MHz - - −50 dB αinstance crosstalk between two decoder instances CVBS inputs with different line frequencies - −40 - dB at −3 dB - 7 - MHz 9-bit analog-to-digital converter B bandwidth φdiff differential phase (amplifier plus anti-alias filter bypassed) - 2 - deg Gdiff differential gain (amplifier plus anti-alias filter bypassed) - 2 - % fclk(ADC) ADC clock frequency 12.8 - 14.3 MHz DLE DC differential linearity error - 0.7 - LSB ILE DC integral linearity error - 1 - LSB V Digital inputs VIL(SCL,SDA) LOW-level input voltage pins SDA and SCL −0.5 - +0.3VDDD VIH(SCL,SDA) HIGH-level input voltage pins SDA and SCL 0.7VDDD - VDDD + 0.5 V VIL(n) LOW-level input voltage all other inputs −0.3 - +0.8 V VIH(n) HIGH-level input voltage all other inputs 2.0 - 5.5 V ILI input leakage current - - 1 µA ILI/O I/O leakage current - - 10 µA Ci input capacitance - - 8 pF Ci(n) input capacitance all other inputs - - 5 pF - - 0.4 V −0.5 - +0.4 V 2.4 - VDDD + 0.5 V outputs at 3-state Digital outputs VOL(SCL,SDA) LOW-level output voltage SDA/SCL at 3 mA sink pins SDA and SCL current VOL LOW-level output voltage IOL = 2 mA VOH HIGH-level output voltage IOH = −2 mA 9397 750 14454 Product data sheet © Koninklijke Philips Electronics N.V. 2005. All rights reserved. Rev. 01 — 21 April 2005 51 of 64 SAA7144HL Philips Semiconductors Quadruple video input processor Table 58: Characteristics …continued VDDD = 3.0 V to 3.6 V; VDDA = 3.1 V to 3.5 V; Tamb = 25 °C; unless otherwise specified. Symbol Parameter Conditions VOL(clk) LOW-level output voltage IOL = 2 mA for LLC clock VOH(clk) HIGH-level output voltage for LLC clock IOH = −2 mA Min Typ Max Unit −0.5 - +0.6 V 2.4 - VDDD + 0.5 V 15 - 40 pF Data and control output timing; see Figure 26 [1] CL output load capacitance tOHD;DAT output hold time CL = 15 pF 4 - - ns tPD propagation delay CL = 25 pF - - 22 ns tPDZ propagation delay to 3-state - - 22 ns 15 - 40 pF 35 - 39 ns Clock output timing (LLC); see Figure 26 CL(LLC) output load capacitance Tcy cycle time δLLC duty factors for tLLCH/tLLC CL = 25 pF 40 - 60 % tr rise time LLC - - 5 ns tf fall time LLC - - 5 ns nominal frequency 40 - 60 % 50 Hz field - 15625 - Hz 60 Hz field - 15734 - Hz - - 5.7 % - 4433619 - Hz LLC Clock input timing (XTALI) δXTALI duty factor for tXTALIH/tXTALI Horizontal PLL fHn ∆fH/fHn nominal line frequency permissible static deviation Subcarrier PLL fSCn ∆fSC nominal subcarrier frequency PAL BGHIN NTSC M; NTSC Japan - 3579545 - Hz PAL M - 3575612 - Hz combination-PAL N - 3582056 - Hz ±400 - - Hz - 24.576 - MHz lock-in range Crystal oscillator fn nominal frequency 3rd harmonic ∆f/fn permissible nominal frequency deviation - - ±50 10−6 ∆Tf/fn(T) permissible nominal frequency deviation with temperature - - ±20 10−6 Crystal specification (X1) Tamb(X1) operating ambient temperature 0 - 70 °C CL load capacitance 8 - - pF 9397 750 14454 Product data sheet © Koninklijke Philips Electronics N.V. 2005. All rights reserved. Rev. 01 — 21 April 2005 52 of 64 SAA7144HL Philips Semiconductors Quadruple video input processor Table 58: Characteristics …continued VDDD = 3.0 V to 3.6 V; VDDA = 3.1 V to 3.5 V; Tamb = 25 °C; unless otherwise specified. Symbol Parameter Rs series resonance resistor C1 motional capacitance - 1.5 ± 20 % - fF C0 parallel capacitance - 3.5 ± 20 % - pF [1] Conditions Min Typ Max Unit - 40 80 Ω The effects of rise and fall times are included in the calculation of tOHD;DAT, tPD and tPDZ. Timings and levels refer to drawings and conditions illustrated in Figure 26. Table 59: Processing delay Function Typical analog delay AI22 −> ADC(in) (ns) Digital delay ADC(in) −> VPO (LLC CLOCKS); YDEL2 to YDEL0 = 0 Without amplifier or anti-alias filter 15 157 With amplifier, without anti-alias filter 25 With amplifier and anti-alias filter 75 9397 750 14454 Product data sheet © Koninklijke Philips Electronics N.V. 2005. All rights reserved. Rev. 01 — 21 April 2005 53 of 64 SAA7144HL Philips Semiconductors Quadruple video input processor 14. Timing diagrams tLLC tLLCL 2.6 V 1.5 V 0.6 V LLC tr tf tLLCH tPD tOHD;DAT 2.4 V VPO 0.6 V 001aab316 Fig 26. Clock/data output timing. burst CVBS input 28 × 1/LLC burst RAW DATA on VPO-bus 157 × 1/LLC Y-DATA on VPO-bus processing delay CVBS- > VPO(1) sync clipped 001aab317 (1) See Table 59. Fig 27. Horizontal timing diagram. 9397 750 14454 Product data sheet © Koninklijke Philips Electronics N.V. 2005. All rights reserved. Rev. 01 — 21 April 2005 54 of 64 xxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx x xxxxxxxxxxxxxx xxxxxxxxxx xxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxx xx xxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxx xxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxx xxxxxxxxxxxxxx xxxxxx xx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxx xxxxx x x 8 R18 18 Ω C2 47 nF AI11_A R19 18 Ω C3 47 nF AI12_A C4 47 nF AI1D_A AI11_A AI12_A R26 56 Ω R30 56 Ω R34 33 Ω DNC1, DNC4, DNC7 to DNC11 AGND AGND AGND R20 18 Ω 47 nF AI11_B C6 47 nF AI12_B C7 47 nF AI1D_B C5 AI11_B R21 18 Ω AI12_B R27 56 Ω R31 56 Ω R35 33 Ω Rev. 01 — 21 April 2005 DNC3, DNC12, DNC14 to DNC18 AGND AGND AGND 9 6 2 1 18 19 11 digital 100 nF DGND 100 nF DGND 100 nF DGND R40 3.3 Ω R42 3.3 Ω R44 3.3 Ω R46 3.3 Ω 59 58 54 55 74 69 73 TDI TDO VSSDE VDDDE VSSDI VDDDI VSSDE VSSDI VDDDI 16 VDDDE analog 10 100 nF DGND DGND DNC2 100 nF VSSA1(DECB) VDDA1(DECB) 15 3.3 V AGND C21 AGND_B 100 nF VSSA0(DECB) AGND C19 VDDA0(DECB) 100 nF AGND VSSA1(DECA) VDDA1(DECA) AGND_A VSSA0(DECA) VDDA0(DECA) 100 nF C17 R54 0Ω 70 117 118 119 120 121 3 4 5 116 115 114 113 110 107 106 105 7, 22, 39, 40, 41, 42, 43 103 101 100 99 95 94 89 87 12 13 14 79 77 72 71 68 67 65 64 17, 44, 66, 75, 76, 78, 82 SAA7144HL DNC6, DNC26 to DNC31 36, 123, 124, 125, 126, 127, 128 as close as possible to the IC analog 3.3 V 29 VSSA0(DECC) VDDA0(DECC) 28 26 21 20 37 38 35 31 30 C14 C16 C18 C20 100 nF 100 nF 100 nF 100 nF AGND digital Fig 28. Application diagram of SAA7144HL. AGND AGND 80 84 81 2 3 1 C23 C24 10 pF 10 pF C25 AGND 85 L1 10 µH 3.3 V 100 nF 91 96 97 109 108 111 5 6 7 8 5 6 7 8 RN3 33 Ω VPO0_B VPO1_B VPO2_B VPO3_B VPO4_B VPO5_B VPO6_B VPO7_B 1 2 3 4 1 2 3 4 8 7 6 5 8 7 6 5 RN5 33 Ω VPO0_C VPO1_C VPO2_C VPO3_C VPO4_C VPO5_C VPO6_C VPO7_C 1 2 3 4 1 2 3 4 8 7 6 5 8 7 6 5 RN7 33 Ω VPO0_D VPO1_D VPO2_D VPO3_D VPO4_D VPO5_D VPO6_D VPO7_D 4 3 2 1 4 3 2 1 5 6 7 8 5 6 7 8 RN9 33 Ω RN4 33 Ω RN6 33 Ω RN8 33 Ω RN10 33 Ω 8 1 RN11 SCL_AB 46 SDA_AB 7 2 0Ω 47 SCL_CD 6 3 48 SDA_CD 5 4 49 LLC_A R48 33 Ω 104 R49 33 Ω LLC_B 86 LLC_C R50 33 Ω 63 R51 33 Ω LLC_D 50 DNC13 45 as close as DNC25 possible to the IC 122 112 R41 3.3 Ω R43 3.3 Ω R45 3.3 Ω R47 3.3 Ω 100 nF 100 nF 100 nF 100 nF VPOA0 VPOA1 VPOA2 VPOA3 VPOA4 VPOA5 VPOA6 VPOA7 VPOB0 VPOB1 VPOB2 VPOB3 VPOB4 VPOB5 VPOB6 VPOB7 VPOC0 VPOC1 VPOC2 VPOC3 VPOC4 VPOC5 VPOC6 VPOC7 DGND DGND DGND VPOB[0:7] VPOC[0:7] VPOD[0:7] VPOD0 VPOD1 VPOD2 VPOD3 VPOD4 VPOD5 VPOD6 VPOD7 SCL_AB SDA_AB SCL_CD SDA_CD CLK0 CLK1 CLK2 CLK3 CLK[0:3] 4.7 kΩ (4×) 3.3 V DGND 10 nF C22 DGND 93 4 3 2 1 4 3 2 1 VPOA[0:7] 3.3 V 001aab216 SAA7144HL AGND AGND AGND VPO0_A VPO1_A VPO2_A VPO3_A VPO4_A VPO5_A VPO6_A VPO7_A VSSDE R37 33 Ω 34 VSSDI R33 56 Ω 33 VDDDE AI1D_D VDDDI AI12_D 47 nF VSSDE 47 nF C13 VDDDE C12 32 BST0 BST1 BST2 Quadruple video input processor 55 of 64 © Koninklijke Philips Electronics N.V. 2005. All rights reserved. R29 56 Ω 47 nF VSSDI R25 18 Ω AI12_D AI11_D C11 VDDDI R24 18 Ω AI11_D 27, 83, 88, 90, 92, 98, 102 XTALI AGND AGND AGND VDDDA DNC5, DNC19 to DNC24 62 61 60 57 56 53 52 51 25 VSSDA R36 33 Ω XTALO AI1D_C R32 56 Ω VSSA1(DECD) 47 nF C10 R28 56 Ω 24 AGND_D AI12_C VDDA1(DECD) 47 nF VSSA0(DECD) C9 23 VDDA0(DECD) AI12_C AI11_C VSSA1(DECC) R23 18 Ω 47 nF VDDA1(DECC) AI11_C C8 AGND_C R22 18 Ω BST[0:2] TDI TDO TMS TCK TRST_N Philips Semiconductors AGND C15 15. Application information 9397 750 14454 Product data sheet 3.3 V SAA7144HL Philips Semiconductors Quadruple video input processor 15.1 Recommended printed-circuit board layout The SAA7144HL consists of analog and digital areas. Due to this special care needs to be taken for design of layout regarding crosstalk by analog and digital supply interaction. It is recommended to use four layer Printed-Circuit Board (PCB). Top and bottom layer for signal wires, one for ground plane and one for supply plane. Split of analog and digital supply layer areas shows best video performance. The ground and supply plane need to be close to each other to achieve capacitive behavior. Due to this size, distance and also material is responsible for layer capacitor value. Additional decoupling isles are required. DIGITAL SUPPLY LAYERS 2b, 3b R SAA7144HL A31 C C A32 A42 digital supply: analog supply: VDDA layer 3a L (HF trap) 3.3 V VDDD Clayer 100 nF VSSA layer: 1 signals 2a VSSA 2b VSSD 3a VDDA 3b VDDD 4 signals ITU 656 BUS D A41 ITU 656 BUS C A22 C R R C A21 R CVBS INPUTS A12 ITU 656 BUS B A11 OUTPUTS ITU 656 BUS A ANALOG SUPPLY LAYERS 2a, 3a layer 2a R layer 3b L (HF trap) 3.3 V 4Ω Clayer GNDA direct to plane VSSD layer 2b GNDD direct to plane 001aab320 Fig 29. Supply method. 9397 750 14454 Product data sheet © Koninklijke Philips Electronics N.V. 2005. All rights reserved. Rev. 01 — 21 April 2005 56 of 64 SAA7144HL Philips Semiconductors Quadruple video input processor 16. Test information 16.1 Boundary scan test The SAA7144HL has built-in logic and five dedicated pins to support boundary scan testing which allows board testing without special hardware (nails). The SAA7144HL follows the “IEEE Std. 1149.1 - Standard Test Access Port and Boundary - Scan Architecture” set by the Joint Test Action Group (JTAG) chaired by Philips. The 5 special pins are: Test Mode Select (TMS), Test Clock (TCK), Test Reset (TRST_N), Test Data Input (TDI) and Test Data Output (TDO). The Boundary Scan Test (BST) functions BYPASS, EXTEST, INTEST, SAMPLE, CLAMP and IDCODE are all supported (see Table 60). Details about the JTAG BST-test can be found in the specification “IEEE Std. 1149.1”. Table 60: BST instructions supported by the SAA7144HL Instruction Description BYPASS This mandatory instruction provides a minimum length serial path (1 bit) between pins TDI and TDO when no test operation of the component is required. EXTEST This mandatory instruction allows testing of off-chip circuitry and board level interconnections. INTEST This optional instruction allows testing of the internal logic (no support for customers available). SAMPLE This mandatory instruction can be used to take a sample of the inputs during normal operation of the component. It can also be used to preload data values into the latched outputs of the boundary scan register. CLAMP This optional instruction is useful for testing when not all ICs have BST. This instruction addresses the bypass register while the boundary scan register is in external test mode. IDCODE This optional instruction will provide information on the components manufacturer, part number and version number. 16.1.1 Initialization of boundary scan circuit The Test Access Port (TAP) controller of an IC should be in the reset state (TEST_LOGIC_RESET) when the IC is in the functional mode. This reset state also forces the instruction register into a functional instruction such as IDCODE or BYPASS. To solve the power-up reset, the standard specifies that the TAP controller will be forced asynchronously to the TEST_LOGIC_RESET state by setting the TRST_N pin LOW. 9397 750 14454 Product data sheet © Koninklijke Philips Electronics N.V. 2005. All rights reserved. Rev. 01 — 21 April 2005 57 of 64 SAA7144HL Philips Semiconductors Quadruple video input processor 16.1.2 Device identification codes A device identification register is specified in “IEEE Std. 1149.1b-1994”. It is a 32-bit register which contains fields for the specification of the IC manufacturer, the IC part number and the IC version number. Its biggest advantage is the possibility to check for the correct ICs mounted after production and determination of the version number of ICs during field service. When the IDCODE instruction is loaded into the BST instruction register, the identification register will be connected internally between pins TDI and TDO of the IC. The identification register will load a component specific code during the CAPTURE_DATA_REGISTER state of the TAP controller and this code can subsequently be shifted out. At board level, this code can be used to verify component manufacturer, type and version number. The device identification register contains 32 bits, numbered 31 to 0, where bit 31 is the most significant bit (nearest to TDI) and bit 0 is the least significant bit (nearest to TDO); see Figure 30. MSB 31 TDI LSB 28 27 12 11 1 nnnn 0011010110100000 00000010101 4-bit version code 16-bit part number 11-bit manufacturer identification 0 1 TDO 001aab315 Fig 30. 32 bits of identification code. 9397 750 14454 Product data sheet © Koninklijke Philips Electronics N.V. 2005. All rights reserved. Rev. 01 — 21 April 2005 58 of 64 SAA7144HL Philips Semiconductors Quadruple video input processor 17. Package outline LQFP128: plastic low profile quad flat package; 128 leads; body 14 x 20 x 1.4 mm SOT425-1 c y X A 102 103 65 64 ZE e E HE A A2 A 1 (A 3) θ wM Lp bp pin 1 index L detail X 39 128 1 38 v M A ZD wM bp e D B HD v M B 0 5 10 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (1) e mm 1.6 0.15 0.05 1.45 1.35 0.25 0.27 0.17 0.20 0.09 20.1 19.9 14.1 13.9 0.5 HD HE 22.15 16.15 21.85 15.85 L Lp v w y 1 0.75 0.45 0.2 0.12 0.1 Z D(1) Z E(1) 0.81 0.59 0.81 0.59 θ 7o o 0 Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. REFERENCES OUTLINE VERSION IEC JEDEC SOT425-1 136E28 MS-026 JEITA EUROPEAN PROJECTION ISSUE DATE 00-01-19 03-02-20 Fig 31. Package outline SOT425-1 (LQFP128). 9397 750 14454 Product data sheet © Koninklijke Philips Electronics N.V. 2005. All rights reserved. Rev. 01 — 21 April 2005 59 of 64 SAA7144HL Philips Semiconductors Quadruple video input processor 18. Soldering 18.1 Introduction to soldering surface mount packages This text gives a very brief insight to a complex technology. A more in-depth account of soldering ICs can be found in our Data Handbook IC26; Integrated Circuit Packages (document order number 9398 652 90011). There is no soldering method that is ideal for all surface mount IC packages. Wave soldering can still be used for certain surface mount ICs, but it is not suitable for fine pitch SMDs. In these situations reflow soldering is recommended. 18.2 Reflow soldering Reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. Driven by legislation and environmental forces the worldwide use of lead-free solder pastes is increasing. Several methods exist for reflowing; for example, convection or convection/infrared heating in a conveyor type oven. Throughput times (preheating, soldering and cooling) vary between 100 seconds and 200 seconds depending on heating method. Typical reflow peak temperatures range from 215 °C to 270 °C depending on solder paste material. The top-surface temperature of the packages should preferably be kept: • below 225 °C (SnPb process) or below 245 °C (Pb-free process) – for all BGA, HTSSON..T and SSOP..T packages – for packages with a thickness ≥ 2.5 mm – for packages with a thickness < 2.5 mm and a volume ≥ 350 mm3 so called thick/large packages. • below 240 °C (SnPb process) or below 260 °C (Pb-free process) for packages with a thickness < 2.5 mm and a volume < 350 mm3 so called small/thin packages. Moisture sensitivity precautions, as indicated on packing, must be respected at all times. 18.3 Wave soldering Conventional single wave soldering is not recommended for surface mount devices (SMDs) or printed-circuit boards with a high component density, as solder bridging and non-wetting can present major problems. To overcome these problems the double-wave soldering method was specifically developed. If wave soldering is used the following conditions must be observed for optimal results: • Use a double-wave soldering method comprising a turbulent wave with high upward pressure followed by a smooth laminar wave. • For packages with leads on two sides and a pitch (e): – larger than or equal to 1.27 mm, the footprint longitudinal axis is preferred to be parallel to the transport direction of the printed-circuit board; 9397 750 14454 Product data sheet © Koninklijke Philips Electronics N.V. 2005. All rights reserved. Rev. 01 — 21 April 2005 60 of 64 SAA7144HL Philips Semiconductors Quadruple video input processor – smaller than 1.27 mm, the footprint longitudinal axis must be parallel to the transport direction of the printed-circuit board. The footprint must incorporate solder thieves at the downstream end. • For packages with leads on four sides, the footprint must be placed at a 45° angle to the transport direction of the printed-circuit board. The footprint must incorporate solder thieves downstream and at the side corners. During placement and before soldering, the package must be fixed with a droplet of adhesive. The adhesive can be applied by screen printing, pin transfer or syringe dispensing. The package can be soldered after the adhesive is cured. Typical dwell time of the leads in the wave ranges from 3 seconds to 4 seconds at 250 °C or 265 °C, depending on solder material applied, SnPb or Pb-free respectively. A mildly-activated flux will eliminate the need for removal of corrosive residues in most applications. 18.4 Manual soldering Fix the component by first soldering two diagonally-opposite end leads. Use a low voltage (24 V or less) soldering iron applied to the flat part of the lead. Contact time must be limited to 10 seconds at up to 300 °C. When using a dedicated tool, all other leads can be soldered in one operation within 2 seconds to 5 seconds between 270 °C and 320 °C. 18.5 Package related soldering information Table 61: Suitability of surface mount IC packages for wave and reflow soldering methods Package [1] Soldering method Wave Reflow [2] BGA, HTSSON..T [3], LBGA, LFBGA, SQFP, SSOP..T [3], TFBGA, VFBGA, XSON not suitable suitable DHVQFN, HBCC, HBGA, HLQFP, HSO, HSOP, HSQFP, HSSON, HTQFP, HTSSOP, HVQFN, HVSON, SMS not suitable [4] suitable PLCC [5], SO, SOJ suitable suitable not recommended [5] [6] suitable SSOP, TSSOP, VSO, VSSOP not recommended [7] suitable CWQCCN..L [8], PMFP [9], WQCCN..L [8] not suitable LQFP, QFP, TQFP [1] For more detailed information on the BGA packages refer to the (LF)BGA Application Note (AN01026); order a copy from your Philips Semiconductors sales office. [2] All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the maximum temperature (with respect to time) and body size of the package, there is a risk that internal or external package cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). For details, refer to the Drypack information in the Data Handbook IC26; Integrated Circuit Packages; Section: Packing Methods. [3] These transparent plastic packages are extremely sensitive to reflow soldering conditions and must on no account be processed through more than one soldering cycle or subjected to infrared reflow soldering with peak temperature exceeding 217 °C ± 10 °C measured in the atmosphere of the reflow oven. The package body peak temperature must be kept as low as possible. 9397 750 14454 Product data sheet not suitable © Koninklijke Philips Electronics N.V. 2005. All rights reserved. Rev. 01 — 21 April 2005 61 of 64 SAA7144HL Philips Semiconductors Quadruple video input processor [4] These packages are not suitable for wave soldering. On versions with the heatsink on the bottom side, the solder cannot penetrate between the printed-circuit board and the heatsink. On versions with the heatsink on the top side, the solder might be deposited on the heatsink surface. [5] If wave soldering is considered, then the package must be placed at a 45° angle to the solder wave direction. The package footprint must incorporate solder thieves downstream and at the side corners. [6] Wave soldering is suitable for LQFP, QFP and TQFP packages with a pitch (e) larger than 0.8 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm. [7] Wave soldering is suitable for SSOP, TSSOP, VSO and VSSOP packages with a pitch (e) equal to or larger than 0.65 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm. [8] Image sensor packages in principle should not be soldered. They are mounted in sockets or delivered pre-mounted on flex foil. However, the image sensor package can be mounted by the client on a flex foil by using a hot bar soldering process. The appropriate soldering profile can be provided on request. [9] Hot bar soldering or manual soldering is suitable for PMFP packages. 19. Revision history Table 62: Revision history Document ID Release date Data sheet status Change notice Doc. number Supersedes SAA7144HL_1 20050421 Product data sheet - 9397 750 14454 - 9397 750 14454 Product data sheet © Koninklijke Philips Electronics N.V. 2005. All rights reserved. Rev. 01 — 21 April 2005 62 of 64 SAA7144HL Philips Semiconductors Quadruple video input processor 20. Data sheet status Level Data sheet status [1] Product status [2] [3] Definition I Objective data Development This data sheet contains data from the objective specification for product development. Philips Semiconductors reserves the right to change the specification in any manner without notice. II Preliminary data Qualification This data sheet contains data from the preliminary specification. Supplementary data will be published at a later date. Philips Semiconductors reserves the right to change the specification without notice, in order to improve the design and supply the best possible product. III Product data Production This data sheet contains data from the product specification. Philips Semiconductors reserves the right to make changes at any time in order to improve the design, manufacturing and supply. Relevant changes will be communicated via a Customer Product/Process Change Notification (CPCN). [1] Please consult the most recently issued data sheet before initiating or completing a design. [2] The product status of the device(s) described in this data sheet may have changed since this data sheet was published. The latest information is available on the Internet at URL http://www.semiconductors.philips.com. [3] For data sheets describing multiple type numbers, the highest-level product status determines the data sheet status. 21. Definitions customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application. Short-form specification — The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook. Right to make changes — Philips Semiconductors reserves the right to make changes in the products - including circuits, standard cells, and/or software - described or contained herein in order to improve design and/or performance. When the product is in full production (status ‘Production’), relevant changes will be communicated via a Customer Product/Process Change Notification (CPCN). Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified. Limiting values definition — Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 60134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information — Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification. 23. Trademarks 22. Disclaimers Intercast — is a trademark of Intel Corporation. Macrovision — is a registered trademark of Macrovision Corporation. Life support — These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductors 24. Contact information For additional information, please visit: http://www.semiconductors.philips.com For sales office addresses, send an email to: [email protected] 9397 750 14454 Product data sheet © Koninklijke Philips Electronics N.V. 2005. All rights reserved. Rev. 01 — 21 April 2005 63 of 64 SAA7144HL Philips Semiconductors Quadruple video input processor 25. Contents 1 2 2.1 2.2 3 4 5 6 7 7.1 7.2 8 8.1 8.2 8.2.1 8.2.2 8.3 8.4 8.5 8.6 8.7 8.8 8.9 8.10 9 9.1 9.2 9.3 9.3.1 9.3.2 9.3.3 9.3.4 9.3.5 9.3.6 9.3.7 9.3.8 9.3.9 9.3.10 9.3.11 9.3.12 9.3.13 9.3.14 9.3.15 9.3.16 9.3.17 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 General . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Features of each of the four video decoder instances A, B, C and D . . . . . . . . . . . . . . . . . . 2 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Quick reference data . . . . . . . . . . . . . . . . . . . . . 3 Ordering information . . . . . . . . . . . . . . . . . . . . . 3 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Pinning information . . . . . . . . . . . . . . . . . . . . . . 5 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 5 Functional description . . . . . . . . . . . . . . . . . . . 8 Analog input processing . . . . . . . . . . . . . . . . . . 9 Analog control circuits. . . . . . . . . . . . . . . . . . . . 9 Clamping. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Gain control . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Chrominance processing . . . . . . . . . . . . . . . . 12 Luminance processing . . . . . . . . . . . . . . . . . . 16 Synchronization . . . . . . . . . . . . . . . . . . . . . . . 20 Clock generation circuit . . . . . . . . . . . . . . . . . 21 Power-on reset . . . . . . . . . . . . . . . . . . . . . . . . 21 Multistandard VBI data slicer . . . . . . . . . . . . . 23 VBI-raw data bypass. . . . . . . . . . . . . . . . . . . . 23 Digital output port . . . . . . . . . . . . . . . . . . . . . . 24 2 I C-bus description . . . . . . . . . . . . . . . . . . . . . 32 I2C-bus format. . . . . . . . . . . . . . . . . . . . . . . . . 32 I2C-bus register description . . . . . . . . . . . . . . 33 I2C-bus detail . . . . . . . . . . . . . . . . . . . . . . . . . 36 Subaddress 00h (read only register) . . . . . . . 36 Subaddress 01h . . . . . . . . . . . . . . . . . . . . . . . 36 Subaddress 02h . . . . . . . . . . . . . . . . . . . . . . . 36 Subaddress 03h . . . . . . . . . . . . . . . . . . . . . . . 37 Subaddress 04h . . . . . . . . . . . . . . . . . . . . . . . 38 Subaddress 06h . . . . . . . . . . . . . . . . . . . . . . . 38 Subaddress 07h . . . . . . . . . . . . . . . . . . . . . . . 38 Subaddress 08h . . . . . . . . . . . . . . . . . . . . . . . 39 Subaddress 09h . . . . . . . . . . . . . . . . . . . . . . . 39 Subaddress 0Ah . . . . . . . . . . . . . . . . . . . . . . . 40 Subaddress 0Bh . . . . . . . . . . . . . . . . . . . . . . . 40 Subaddress 0Ch . . . . . . . . . . . . . . . . . . . . . . . 41 Subaddress 0Dh . . . . . . . . . . . . . . . . . . . . . . . 41 Subaddress 0Eh . . . . . . . . . . . . . . . . . . . . . . . 41 Subaddress 0Fh . . . . . . . . . . . . . . . . . . . . . . . 42 Subaddress 10h . . . . . . . . . . . . . . . . . . . . . . . 42 Subaddress 11h . . . . . . . . . . . . . . . . . . . . . . . 43 9.3.18 9.3.19 9.3.20 9.3.21 9.3.22 9.3.23 9.3.24 9.3.25 9.3.26 9.3.27 9.3.28 Subaddress 13h . . . . . . . . . . . . . . . . . . . . . . . Subaddress 1Fh (read only register) . . . . . . . Subaddress 40h . . . . . . . . . . . . . . . . . . . . . . . Subaddresses 41h to 57h . . . . . . . . . . . . . . . Subaddress 58h . . . . . . . . . . . . . . . . . . . . . . . Subaddresses 59h and 5Bh. . . . . . . . . . . . . . Subaddresses 5Ah and 5Bh . . . . . . . . . . . . . Subaddress 5Bh. . . . . . . . . . . . . . . . . . . . . . . Subaddress 5Eh. . . . . . . . . . . . . . . . . . . . . . . Subaddress 60h (read only register) . . . . . . . Subaddresses 61h and 62h (read only 43 44 44 45 45 46 46 46 46 47 register) . . . . . . . . . . . . . . . . . . . . . . . . . 47 10 11 12 13 14 15 15.1 16 16.1 16.1.1 16.1.2 17 18 18.1 18.2 18.3 18.4 18.5 19 20 21 22 23 24 I2C-bus start set-up . . . . . . . . . . . . . . . . . . . . . Limiting values . . . . . . . . . . . . . . . . . . . . . . . . Thermal characteristics . . . . . . . . . . . . . . . . . Characteristics . . . . . . . . . . . . . . . . . . . . . . . . Timing diagrams . . . . . . . . . . . . . . . . . . . . . . . Application information . . . . . . . . . . . . . . . . . Recommended printed-circuit board layout . . Test information. . . . . . . . . . . . . . . . . . . . . . . . Boundary scan test . . . . . . . . . . . . . . . . . . . . Initialization of boundary scan circuit . . . . . . . Device identification codes. . . . . . . . . . . . . . . Package outline . . . . . . . . . . . . . . . . . . . . . . . . Soldering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Introduction to soldering surface mount packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . Reflow soldering. . . . . . . . . . . . . . . . . . . . . . . Wave soldering. . . . . . . . . . . . . . . . . . . . . . . . Manual soldering . . . . . . . . . . . . . . . . . . . . . . Package related soldering information . . . . . . Revision history . . . . . . . . . . . . . . . . . . . . . . . Data sheet status. . . . . . . . . . . . . . . . . . . . . . . Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . . Contact information . . . . . . . . . . . . . . . . . . . . 47 50 50 50 54 55 56 57 57 57 58 59 60 60 60 60 61 61 62 63 63 63 63 63 © Koninklijke Philips Electronics N.V. 2005 All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights. Date of release: 21 April 2005 Document number: 9397 750 14454 Published in The Netherlands