74ABT841 10-bit bus interface latch; 3-state Rev. 03 — 25 March 2010 Product data sheet 1. General description The 74ABT841 high performance BiCMOS device combines low static and dynamic power dissipation with high speed and high output drive. The 74ABT841 bus interface register is designed to provide extra data width for wider data/address paths of buses carrying parity. The 74ABT841 consists of ten D-type latches with 3-state outputs. The flip-flops appear transparent to the data when latch enable (LE) is HIGH. This allows asynchronous operation, as the output transition follows the data in transition. On the LE HIGH-to-LOW transition, the data that meets the set-up and hold time is latched. Data appears on the bus when the output enable (OE) is LOW. When OE is HIGH the output is in the high-impedance state. 2. Features and benefits High speed parallel latches Extra data width for wide address/data paths or buses carrying parity Ideal where high speed, light loading, or increased fan-in are required with MOS microprocessors Broadside pinout Output capability: +64 mA and −32 mA Power-up 3-state Power-up reset Latch-up protection exceeds 500 mA per JESD78B class II level A ESD protection: HBM JESD22-A114F exceeds 2000 V MM JESD22-A115-A exceeds 200 V 74ABT841 NXP Semiconductors 10-bit bus interface latch; 3-state 3. Ordering information Table 1. Ordering information Type number Package Temperature range Name Description Version 74ABT841D −40 °C to +85 °C SO24 plastic small outline package; 24 leads; body width 7.5 mm SOT137-1 74ABT841DB −40 °C to +85 °C SSOP24 plastic shrink small outline package; 24 leads; body width 5.3 mm SOT340-1 74ABT841PW −40 °C to +85 °C TSSOP24 plastic thin shrink small outline package; 24 leads; body width 4.4 mm SOT355-1 4. Functional diagram 1 13 2 3 4 5 6 7 8 9 10 11 2 D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 13 1 LE OE Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 Q8 Q9 23 22 21 20 19 18 17 16 15 14 001aae911 EN C1 23 1D 3 22 4 21 5 20 6 19 7 18 8 17 9 16 10 15 11 14 001aae912 Fig 1. Logic symbol D0 2 D1 3 D L LE OE Fig 2. D2 4 D Q L D3 5 D Q L D4 6 D Q L D5 7 D Q IEC logic symbol L D6 8 D Q L D7 9 D Q L D8 10 D Q L D9 11 D Q L D Q L Q 13 1 23 Q0 22 Q1 21 Q2 20 Q3 19 Q4 18 Q5 17 Q6 16 Q7 15 Q8 14 Q9 001aae913 Fig 3. Logic diagram 74ABT841_3 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 03 — 25 March 2010 © NXP B.V. 2010. All rights reserved. 2 of 15 74ABT841 NXP Semiconductors 10-bit bus interface latch; 3-state 5. Pinning information 5.1 Pinning 74ABT841 OE 1 24 VCC D0 2 23 Q0 D1 3 22 Q1 D2 4 21 Q2 D3 5 20 Q3 D4 6 19 Q4 D5 7 18 Q5 D6 8 17 Q6 D7 9 16 Q7 D8 10 15 Q8 D9 11 14 Q9 GND 12 13 LE 001aae910 Fig 4. Pin configuration 5.2 Pin description Table 2. Pin description Symbol Pin Description OE 1 output enable input (active LOW) D0 to D9 2, 3, 4, 5, 6, 7, 8, 9,10, 11 data input GND 12 ground (0 V) LE 13 latch enable input (active falling edge) Q0 to Q9 23, 22, 21, 20, 19, 18, 17, 16, 15, 14 data output VCC 24 positive supply voltage 74ABT841_3 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 03 — 25 March 2010 © NXP B.V. 2010. All rights reserved. 3 of 15 74ABT841 NXP Semiconductors 10-bit bus interface latch; 3-state 6. Functional description Table 3. Function table[1] Input Output Operating mode OE LE nD Q0 to Q9 L H L L L H H H L ↓ l L L ↓ h H H X X Z high-impedance L L X NC hold [1] transparent latched H = HIGH voltage level; h = HIGH voltage level one set-up time prior to the LOW-to-HIGH LE transition; L = LOW voltage level; l = LOW voltage level one set-up time prior to the LOW-to-HIGH LE transition; ↓ = HIGH-to-LOW clock transition; NC = no change; X = don’t care; Z = high-impedance OFF-state. 7. Limiting values Table 4. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol Parameter VCC supply voltage Conditions Min Max Unit −0.5 +7.0 V input voltage [1] −1.2 +7.0 V VO output voltage output in OFF-state or HIGH-state [1] −0.5 +5.5 V IIK input clamping current VI < 0 V −18 - mA IOK output clamping current VO < 0 V −50 - mA IO output current output in LOW-state - 128 mA - 150 °C −65 +150 °C VI Tj junction temperature Tstg storage temperature [2] [1] The input and output voltage ratings may be exceeded if the input and output current ratings are observed. [2] The performance capability of a high-performance integrated circuit in conjunction with its thermal environment can create junction temperatures which are detrimental to reliability. The maximum junction temperature of this integrated circuit should not exceed 150 °C. 74ABT841_3 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 03 — 25 March 2010 © NXP B.V. 2010. All rights reserved. 4 of 15 74ABT841 NXP Semiconductors 10-bit bus interface latch; 3-state 8. Recommended operating conditions Table 5. Recommended operating conditions Symbol Parameter VCC Conditions Min Typ Max Unit supply voltage 4.5 - 5.5 V VI input voltage 0 - VCC V VIH HIGH-level input voltage 2.0 - - V VIL LOW-level input voltage - - 0.8 V IOH HIGH-level output current −32 - - mA IOL LOW-level output current - - 64 mA Δt/ΔV input transition rise and fall rate 0 - 5 ns/V Tamb ambient temperature −40 - +85 °C in free air 9. Static characteristics Table 6. Static characteristics Symbol Parameter 25 °C Conditions Min Typ Max Min Max −1.2 −0.9 - −1.2 - V VCC = 4.5 V; IOH = −3 mA 2.5 3.5 - 2.5 - V VCC = 5.0 V; IOH = −3 mA 3.0 4.0 - 3.0 - V VCC = 4.5 V; IOH = −32 mA 2.0 2.6 - 2.0 - V - 0.42 0.55 - 0.55 V - 0.13 0.55 - 0.55 V control pins - ±0.01 ±1.0 - ±1.0 μA data pins - ±5 ±100 - ±100 μA - ±5.0 ±100 - ±100 μA - ±5.0 ±50 - ±50 μA VIK input clamping voltage VCC = 4.5 V; IIK = −18 mA VOH HIGH-level output voltage VI = VIL or VIH VOL LOW-level output voltage VCC = 4.5 V; IOL = 64 mA; VI = VIL or VIH VOL(pu) power-up LOW-level output voltage VCC = 5.5 V; IO = 1 mA; VI = GND or VCC II input leakage current VCC = 5.5 V; VI = GND or 5.5 V IOFF power-off leakage current VCC = 0 V; VI or VO ≤ 4.5 V IO(pu/pd) power-up/power-down output current VCC = 2.0 V; VO = 0.5 V; VI = GND or VCC; OEn HIGH IOZ OFF-state output current VCC = 5.5 V; VI = VIL or VIH [2] - 5.0 50 - 50 μA VO = 0.5 V - −5.0 −50 - −50 μA - 5.0 50 - 50 μA −180 −100 −50 −180 −50 mA output leakage current HIGH-state; VO = 5.5 V; VCC = 5.5 V; VI = GND or VCC IO output current VCC = 5.5 V; VO = 2.5 V Product data sheet [1] VO = 2.7 V ILO 74ABT841_3 −40 °C to +85 °C Unit [3] All information provided in this document is subject to legal disclaimers. Rev. 03 — 25 March 2010 © NXP B.V. 2010. All rights reserved. 5 of 15 74ABT841 NXP Semiconductors 10-bit bus interface latch; 3-state Table 6. Static characteristics …continued Symbol Parameter ICC supply current 25 °C Conditions −40 °C to +85 °C Unit Min Typ Max Min Max outputs HIGH-state - 0.5 250 - 250 μA outputs LOW-state - 25 38 - 38 mA outputs disabled - 0.5 250 - 250 μA - 0.5 1.5 - 1.5 mA VCC = 5.5 V; VI = GND or VCC ΔICC additional supply current per input pin; VCC = 5.5 V; one input at 3.4 V; other inputs at VCC or GND CI input capacitance VI = 0 V or VCC - 4 - - - pF CO output capacitance outputs disabled; VO = 0 V or VCC - 7 - - - pF [4] [1] For valid test results, data must not be loaded into the flip-flops (or latches) after applying the power. [2] This parameter is valid for any VCC between 0 V and 2.1 V with a transition time of up to 10 ms. For VCC = 2.1 V to VCC = 5 V ± 10 %, a transition time of up to 100 μs is permitted. [3] Not more than one output should be tested at a time, and the duration of the test should not exceed one second. [4] This is the increase in supply current for each input at 3.4 V. 10. Dynamic characteristics Table 7. Dynamic characteristics GND = 0 V; for test circuit, see Figure 9. Symbol Parameter tPLH 25 °C; VCC = 5.0 V Conditions −40 °C to +70 °C; Unit VCC = 5.0 V ± 0.5 V Min Typ Max Min Max LOW to HIGH propagation delay Dn to Qn; see Figure 5 2.1 4.1 5.5 2.1 6.2 ns LE to Qn; see Figure 6 2.1 4.1 5.9 2.1 6.5 ns HIGH to LOW propagation delay Dn to Qn; see Figure 5 2.0 4.0 5.5 2.0 6.2 ns LE to Qn; see Figure 6 2.8 4.6 6.2 2.8 6.7 ns tPZH OFF-state to HIGH propagation delay OE to Qn; see Figure 7 1.0 3.0 4.5 1.0 5.3 ns tPZL OFF-state to LOW propagation delay OE to Qn; see Figure 7 2.2 4.1 5.6 2.2 6.3 ns tPHZ HIGH to OFF-state propagation delay OE to Qn; see Figure 7 2.7 4.7 6.2 2.7 7.1 ns tPLZ LOW to OFF-state propagation delay OE to Qn; see Figure 7 2.8 4.6 6.1 2.8 6.5 ns tsu(H) set-up time HIGH Dn to LE; see Figure 8 2.5 1.0 - 2.5 - ns tsu(L) set-up time LOW Dn to LE; see Figure 8 1.5 0 - 1.5 - ns th(H) hold time HIGH Dn to LE; see Figure 8 1.5 0.2 - 1.5 - ns th(L) hold time LOW Dn to LE; see Figure 8 +1.0 −0.8 - 1.0 - ns tWH pulse width HIGH LE; see Figure 6 3.3 1.9 - 3.3 - ns tWL pulse width LOW LE; see Figure 6 3.3 1.9 - 3.3 - ns tPHL 74ABT841_3 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 03 — 25 March 2010 © NXP B.V. 2010. All rights reserved. 6 of 15 74ABT841 NXP Semiconductors 10-bit bus interface latch; 3-state 11. Waveforms VI VM Dn VM GND tPLH tPHL VOH VM Qn VM VOL 001aae916 VM = 1.5 V VOL and VOH are typical voltage output levels that occur with the output load. Fig 5. Propagation delay for data to output VI VM LE VM VM GND tWH tWL tPLH tPHL VOH Qn VM VM VOL 001aae914 VM = 1.5 V VOL and VOH are typical voltage output levels that occur with the output load. Fig 6. Propagation delay, latch enable input to output and enable pulse width VI OE input VM GND tPZL tPLZ 3.5 V output LOW-to-OFF OFF-to-LOW VM VOL + 0.3 V VOL tPHZ VOH tPZH VOH − 0.3 V output HIGH-to-OFF OFF-to-HIGH VM GND outputs enabled outputs disabled outputs enabled 001aal299 VM = 1.5 V VOL and VOH are typical voltage output levels that occur with the output load. Fig 7. 3-state output (Qn) enable and disable times 74ABT841_3 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 03 — 25 March 2010 © NXP B.V. 2010. All rights reserved. 7 of 15 74ABT841 NXP Semiconductors 10-bit bus interface latch; 3-state VI Dn VM VM VM VM GND tsu(H) th(H) tsu(L) th(L) VI VM LE VM GND 001aae918 VM = 1.5 V The shaded areas indicate when the input is permitted to change for predictable output performance. Fig 8. Data set-up and hold times VI tW 90 % 90 % negative pulse VM 10 % 0V VCC 10 % tf tr tr tf VI 90 % positive pulse 0V VEXT VM VI DUT RT 90 % RL VO G CL RL VM VM 10 % 10 % mna616 tW 001aai298 a. Input pulse definition b. Test circuit Test data and VEXT levels are given in Table 8. RL = Load resistance. CL = Load capacitance including jig and probe capacitance. RT = Termination resistance should be equal to output impedance Zo of the pulse generator. VEXT = Test voltage for switching times. Fig 9. Table 8. Test circuit for measuring switching times Test data Input Load VEXT VI fI tW tr, tf CL RL tPHL, tPLH tPZH, tPHZ tPZL, tPLZ 3.0 V 1 MHz 500 ns ≤ 2.5 ns 50 pF 500 Ω open open 7.0 V 74ABT841_3 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 03 — 25 March 2010 © NXP B.V. 2010. All rights reserved. 8 of 15 74ABT841 NXP Semiconductors 10-bit bus interface latch; 3-state 12. Package outline SO24: plastic small outline package; 24 leads; body width 7.5 mm SOT137-1 D E A X c HE y v M A Z 24 13 Q A2 A (A 3) A1 pin 1 index θ Lp L 1 12 e detail X w M bp 0 5 10 mm scale DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (1) e HE L Lp Q v w y mm 2.65 0.3 0.1 2.45 2.25 0.25 0.49 0.36 0.32 0.23 15.6 15.2 7.6 7.4 1.27 10.65 10.00 1.4 1.1 0.4 1.1 1.0 0.25 0.25 0.1 0.01 0.019 0.013 0.014 0.009 0.61 0.60 0.30 0.29 0.05 0.419 0.043 0.055 0.394 0.016 inches 0.1 0.012 0.096 0.004 0.089 0.043 0.039 0.01 0.01 Z (1) 0.9 0.4 0.035 0.004 0.016 θ o 8 o 0 Note 1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included. REFERENCES OUTLINE VERSION IEC JEDEC SOT137-1 075E05 MS-013 JEITA EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-19 Fig 10. Package outline SOT137-1 (SO24) 74ABT841_3 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 03 — 25 March 2010 © NXP B.V. 2010. All rights reserved. 9 of 15 74ABT841 NXP Semiconductors 10-bit bus interface latch; 3-state SSOP24: plastic shrink small outline package; 24 leads; body width 5.3 mm D SOT340-1 E A X c HE y v M A Z 24 13 Q A2 A (A 3) A1 pin 1 index θ Lp L 1 12 bp e detail X w M 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (1) e HE L Lp Q v w y Z (1) θ mm 2 0.21 0.05 1.80 1.65 0.25 0.38 0.25 0.20 0.09 8.4 8.0 5.4 5.2 0.65 7.9 7.6 1.25 1.03 0.63 0.9 0.7 0.2 0.13 0.1 0.8 0.4 8 o 0 o Note 1. Plastic or metal protrusions of 0.2 mm maximum per side are not included. OUTLINE VERSION SOT340-1 REFERENCES IEC JEDEC JEITA EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-19 MO-150 Fig 11. Package outline SOT340-1 (SSOP24) 74ABT841_3 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 03 — 25 March 2010 © NXP B.V. 2010. All rights reserved. 10 of 15 74ABT841 NXP Semiconductors 10-bit bus interface latch; 3-state TSSOP24: plastic thin shrink small outline package; 24 leads; body width 4.4 mm D SOT355-1 E A X c HE y v M A Z 13 24 Q A2 (A 3) A1 pin 1 index A θ Lp L 1 12 bp e detail X w M 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (2) e HE L Lp Q v w y Z (1) θ mm 1.1 0.15 0.05 0.95 0.80 0.25 0.30 0.19 0.2 0.1 7.9 7.7 4.5 4.3 0.65 6.6 6.2 1 0.75 0.50 0.4 0.3 0.2 0.13 0.1 0.5 0.2 8o 0o Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT355-1 REFERENCES IEC JEDEC JEITA EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-19 MO-153 Fig 12. Package outline SOT355-1 (TSSOP24) 74ABT841_3 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 03 — 25 March 2010 © NXP B.V. 2010. All rights reserved. 11 of 15 74ABT841 NXP Semiconductors 10-bit bus interface latch; 3-state 13. Abbreviations Table 9. Abbreviations Acronym Description BiCMOS Bipolar Complementary Metal-Oxide Semiconductor DUT Device Under Test ESD ElectroStatic Discharge HBM Human Body Model MM Machine Model 14. Revision history Table 10. Revision history Document ID Release date Data sheet status Change notice Supersedes 74ABT841_3 20100325 Product data sheet - 74ABT841_2 74ABT841_2 20100302 Product data sheet - 74ABT841 Modifications: 74ABT841 74ABT841_3 Product data sheet • The format of this data sheet has been redesigned to comply with the new identity guidelines of NXP Semiconductors. • • Legal texts have been adapted to the new company name where appropriate. DIP 24 (SOT222-1) package removed from Section 3 “Ordering information” and Section 12 “Package outline”. 19950906 Product specification - All information provided in this document is subject to legal disclaimers. Rev. 03 — 25 March 2010 - © NXP B.V. 2010. All rights reserved. 12 of 15 74ABT841 NXP Semiconductors 10-bit bus interface latch; 3-state 15. Legal information 15.1 Data sheet status Document status[1][2] Product status[3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification. [1] Please consult the most recently issued document before initiating or completing a design. [2] The term ‘short data sheet’ is explained in section “Definitions”. [3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com. 15.2 Definitions Draft — The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet — A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. Product specification — The information and data provided in a Product data sheet shall define the specification of the product as agreed between NXP Semiconductors and its customer, unless NXP Semiconductors and customer have explicitly agreed otherwise in writing. In no event however, shall an agreement be valid in which the NXP Semiconductors product is deemed to offer functions and qualities beyond those described in the Product data sheet. 15.3 Disclaimers Limited warranty and liability — Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. In no event shall NXP Semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interruption, costs related to the removal or replacement of any products or rework charges) whether or not such damages are based on tort (including negligence), warranty, breach of contract or any other legal theory. Notwithstanding any damages that customer might incur for any reason whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards customer for the products described herein shall be limited in accordance with the Terms and conditions of commercial sale of NXP Semiconductors. Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use in automotive applications — This NXP Semiconductors product has been qualified for use in automotive applications. The product is not designed, authorized or warranted to be 74ABT841_3 Product data sheet suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk. Applications — Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. NXP Semiconductors does not accept any liability related to any default, damage, costs or problem which is based on a weakness or default in the customer application/use or the application/use of customer’s third party customer(s) (hereinafter both referred to as “Application”). It is customer’s sole responsibility to check whether the NXP Semiconductors product is suitable and fit for the Application planned. Customer has to do all necessary testing for the Application in order to avoid a default of the Application and the product. NXP Semiconductors does not accept any liability in this respect. Limiting values — Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) will cause permanent damage to the device. Limiting values are stress ratings only and (proper) operation of the device at these or any other conditions above those given in the Recommended operating conditions section (if present) or the Characteristics sections of this document is not warranted. Constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device. Terms and conditions of commercial sale — NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, unless otherwise agreed in a valid written individual agreement. In case an individual agreement is concluded only the terms and conditions of the respective agreement shall apply. NXP Semiconductors hereby expressly objects to applying the customer’s general terms and conditions with regard to the purchase of NXP Semiconductors products by customer. No offer to sell or license — Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. Export control — This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from national authorities. 15.4 Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. All information provided in this document is subject to legal disclaimers. Rev. 03 — 25 March 2010 © NXP B.V. 2010. All rights reserved. 13 of 15 74ABT841 NXP Semiconductors 10-bit bus interface latch; 3-state 16. Contact information For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: [email protected] 74ABT841_3 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 03 — 25 March 2010 © NXP B.V. 2010. All rights reserved. 14 of 15 74ABT841 NXP Semiconductors 10-bit bus interface latch; 3-state 17. Contents 1 2 3 4 5 5.1 5.2 6 7 8 9 10 11 12 13 14 15 15.1 15.2 15.3 15.4 16 17 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features and benefits . . . . . . . . . . . . . . . . . . . . 1 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2 Pinning information . . . . . . . . . . . . . . . . . . . . . . 3 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3 Functional description . . . . . . . . . . . . . . . . . . . 4 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 4 Recommended operating conditions. . . . . . . . 5 Static characteristics. . . . . . . . . . . . . . . . . . . . . 5 Dynamic characteristics . . . . . . . . . . . . . . . . . . 6 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Package outline . . . . . . . . . . . . . . . . . . . . . . . . . 9 Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Revision history . . . . . . . . . . . . . . . . . . . . . . . . 12 Legal information. . . . . . . . . . . . . . . . . . . . . . . 13 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 13 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Contact information. . . . . . . . . . . . . . . . . . . . . 14 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. © NXP B.V. 2010. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: [email protected] Date of release: 25 March 2010 Document identifier: 74ABT841_3