INTEGRATED CIRCUITS PCK2002 0–300 MHz I2C 1:18 clock buffer Product data File under Integrated Circuits ICL03 2001 Jul 19 Philips Semiconductors Product data 0–300 MHz I2C 1:18 clock buffer PCK2002 • Spread spectrum compliant • Individual clock output enable/disable via I2C FEATURES • HIGH speed, LOW noise non-inverting 1–18 buffer • Typically used to support four SDRAM DIMMs • Multiple VDD, VSS pins for noise reduction • 3.3 V operation • Separate 3-State pin for testing • ESD protection exceeds 2000 V per Standard 801.2 • Optimized for 66 MHz, 100 MHz and 133 MHz operation • Typical 175 ps skew outputs • Available in 48-pin SSOP and TSSOP packages • See PCK2002M for mobile (reduced pincount) 28-pin 1-10 buffer DESCRIPTION The PCK2002 is a 1–18 fanout buffer used for 133/100 MHz CPU, 66/33 MHz PCI, 14.318 MHz REF, or 133/100/66 MHz SDRAM clock distribution. 18 outputs are typically used to support up to 4 SDRAM DIMMS commonly found in desktop, workstation or server applications. All clock outputs meet Intel’s drive, rise/fall time, accuracy, and skew requirements. An I2C interface is included to allow each output to be enabled/disabled individually. An output disabled via the I2C interface will be held in the LOW state. In addition, there is an OE input which 3-States all outputs. version QUICK REFERENCE DATA SYMBOL tPLH tPHL PARAMETER TYPICAL UNIT VCC = 3.3 V, CL = 30 pF 2.7 2.9 ns Rise time VCC = 3.3 V, CL = 30 pF 1.1 ns Fall time VCC = 3.3 V, CL = 30 pF 1.0 ns Total supply current VCC = 3.465 V 35 µA Propagation delay BUF_IN to BUF_OUTn tr tf ICC CONDITIONS ORDERING INFORMATION PACKAGES TEMPERATURE RANGE ORDER CODE DRAWING NUMBER 48-Pin Plastic TSSOP 0 to +70 °C PCK2002DGG SOT362-1 48-Pin Plastic SSOP 0 to +70 °C PCK2002DL SOT370-1 PIN CONFIGURATION PIN DESCRIPTION RESERVED 1 48 RESERVED RESERVED 2 47 RESERVED 46 VDD9 VDD0 3 BUF_OUT0 4 BUF_OUT1 5 45 BUF_OUT15 44 BUF_OUT14 VSS0 6 43 VSS9 VDD1 7 42 VDD8 BUF_OUT2 8 41 BUF_OUT13 BUF_OUT3 9 VSS1 10 40 BUF_OUT12 39 VSS8 VDD2 12 BUF_OUT4 13 BUF_OUT5 14 VSS2 15 VDD3 16 BUF_OUT6 17 BUF_OUT7 18 38 OE PCK2002 BUF_IN 11 37 VDD7 36 BUF_OUT11 35 BUF_OUT10 34 VSS7 33 VDD6 32 BUF_OUT9 31 BUF_OUT8 VSS3 19 30 VSS6 VDD4 20 29 VDD5 BUF_OUT16 21 VSS4 22 VDDI2C 23 SDA 24 28 BUF_OUT17 27 VSS5 is a trademark of Philips Semiconductors Corporation. 2001 Jul 19 I/O TYPE SYMBOL FUNCTION 4, 5, 8, 9 Output BUF_OUT (0–3) Buffered clock outputs 13, 14, 17, 18 Output BUF_OUT (4–7) Buffered clock outputs 31, 32, 35, 36 Output BUF_OUT (8–11) Buffered clock outputs 40, 41, 44, 45 Output BUF_OUT (12–15) Buffered clock outputs 21, 28 Output BUF_OUT (16–17) Buffered clock outputs 11 Input BUF_IN 38 Input OE 24 I/O SDA I2C serial data 25 Input SCL I2C serial clock 3, 7, 12, 16, 20, 29, 33, 37, 42, 46 Input VDD (0–9) 3.3 V Power supply 6, 10, 15, 19, 22, 27, 30, 34, 39, 43 Input VSS (0–9) Ground 23 Input VDDI2C 3.3 V I2C Power supply 26 Input VSSI2C I2C Ground 1, 2, 47, 48 n/a RESERVED Undefined 26 VSSI2C 25 SCL SW00731 I2C PIN NUMBER 2 Buffered clock input Active high output enable 853-2267 26745 Philips Semiconductors Product data 0–300 MHz I2C 1:18 clock buffer PCK2002 FUNCTION TABLE OE BUF_IN I2CEN BUF_OUTn Z L X X H L X L H H H H H H L L ABSOLUTE MAXIMUM RATINGS1, 2 In accordance with the Absolute Maximum Rating System (IEC 134) Voltages are referenced to VSS (VSS = 0V) SYMBOL VDD PARAMETER LIMITS CONDITION DC 3.3 V supply voltage IIK DC input diode current VI < 0 VI DC input voltage Note 2 IOK DC output diode current VO DC output voltage IO DC output source or sink current TSTG Storage temperature range PTOT Power dissipation per package plastic medium-shrink SO (SSOP) MAX –0.5 +4.6 V –50 mA –0.5 +4.6 V ±50 mA VO > VDD or VO < 0 Note 2 UNIT MIN –0.5 VO >= 0 to VDD –65 For temperature range: 0 to +70°C above +55°C derate linearly with 11.3mW/K VCC + 0.5 V ±50 mA +150 °C 850 mW NOTES: 1. Stresses beyond those listed may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. 2. The input and output voltage ratings may be exceeded if the input and output current ratings are observed. RECOMMENDED OPERATING CONDITIONS SYMBOL PARAMETER VDD CONDITIONS LIMITS UNIT MIN MAX DC 3.3 V supply voltage 3.135 3.465 V CL Capacitive load 20 30 pF VI DC input voltage range 0 VDD V VO DC output voltage range 0 VDD V Tamb Operating ambient temperature range in free air 0 +70 °C 2001 Jul 19 3 Philips Semiconductors Product data 0–300 MHz I2C 1:18 clock buffer PCK2002 DC CHARACTERISTICS SYMBOL PARAMETER VDD (V) HIGH level input voltage 3.135 to 3.465 VIL LOW level input voltage 3.135 to 3.465 3 3V output HIGH voltage 3.3V VOL O 3 3V output LOW voltage 3.3V IOH O Output HIGH current IOL O Output LOW current Tamb = 0 to +70 °C OTHER VIH VOH O LIMITS TEST CONDITIONS UNIT MIN MAX 2.0 VDD + 0.3 V V VSS – 0.3 0.8 3.135 to 3.465 IOH = –1 mA VCC – 0.1 — 3.135 IOH = –36 mA 2.4 — 3.135 to 3.465 IOL= 1 mA — 0.1 3.135 IOL= 24 mA — 0.4 3.135 VOUT = 2.0 V –54 –126 3.465 VOUT = 3.135 V –21 –46 3.135 to 3.465 VOUT = 1.0 V 49 118 3.135 to 3.465 VOUT = 0.4 V 24 53 V V mA mA ±II Input leakage current 3.465 — ±5 µA ±IOZ 3-State output OFF-State current 3.465 VOUT = VDDor GND IO = 0 — 10 µA ICC Quiescent supply current 3.465 VI = VDD or GND IO = 0 — 100 µA ∆ICC Additional quiescent supply current given per control pin 3.135 to 3.465 VI = VDD– 0.6V IO = 0 — 500 µA AC CHARACTERISTICS SYMBOL PARAMETER LIMITS Tamb = 0 to +70 °C TEST CONDITIONS UNIT NOTES MIN TYP6 MAX SDRAM rise time 2, 4 1.5 2.0 4.0 V/ns TSDFALL SDRAM fall time 2, 4 1.5 2.9 4.0 V/ns TPLH SDRAM buffer LH propagation delay 4, 5 1.2 2.7 3.5 ns TSDRISE TPHL SDRAM buffer HL propagation delay 4, 5 1.2 2.9 3.5 ns TPZL, TPZH SDRAM buffer enable time 4, 5 1.0 2.6 5.0 ns TPLZ, TPHZ SDRAM buffer disable time 4, 5 1.0 2.7 5.0 ns 3, 4, 5 45 52 55 % 1, 4 — 150 250 ps — — 500 ps DUTY CYCLE Output Duty Cycle TSDSKW SDRAM Bus CLK skew TDDSKW Device to device skew Measured at 1.5 V NOTES: 1. Skew is measured on the rising edge at 1.5 V. 2. TSDRISE and TSDFALL are measured as a transition through the threshold region VOL = 0.4 V and VOH = 2.4 V (1mA) JEDEC specification. 3. Duty cycle should be tested with a 50/50% input. 4. Over MIN (20 pF) to MAX (30 pF) discrete load, process, voltage, and temperature. 5. Input edge rate for these tests must be faster than 1 V/ns. 6. All typical values are at VCC = 3.3 V and Tamb = 25 °C. 2001 Jul 19 4 Philips Semiconductors Product data 0–300 MHz I2C 1:18 clock buffer PCK2002 I2C CONSIDERATIONS I2C has been chosen as the serial bus interface to control the PCK2002. I2C was chosen to support the JEDEC proposal JC-42.5 168 Pin Unbuffered SDRAM DIMM. All vendors are required to determine the legal issues associated with the manufacture of I2C devices. 1) Address assignment: The clock driver in this specification uses the single, 7-bit address shown below. All devices can use the address if only one master clock driver is used in a design. The address can be re-used for the CKBF device if no other conflicting I2C clock driver is used in the system. The following address was confirmed by Philips on 09/04/96. A6 A5 A4 A3 A2 A1 A0 R/W 1 1 0 1 0 0 1 0 NOTE: The R/W bit is used by the I2C controller as a data direction bit. A ‘zero’ indicates a transmission (WRITE) to the clock device. A ‘one’ indicates a request for data (READ) from the clock driver. Since the definition of the clock buffer only allows the controller to WRITE data; the R/W bit of the address will always be seen as ‘zero’. Optimal address decoding of this bit is left to the vendor. 2) Options: It is our understanding that metal mask options and other pinouts of this type of clock driver will be allowed to use the same address as the original CKBF device. I2C addresses are defined in terms of function (master clock driver) rather than form (pinout, and option). 3) Slave/Receiver: The clock driver is assumed to require only slave/receiver functionality. Slave/transmitter functionality is optional. 4) Data Transfer Rate: 100 kbits/s (standard mode) is the base functionality required. Fast mode (400 kbits/s) functionality is optional. 5) Logic Levels: I2C logic levels are based on a percentage of VDD for the controller and other devices on the bus. Assume all devices are based on a 3.3 Volt supply. 6) Data Byte Format: Byte format is 8 Bits as described in the following appendices. 7) Data Protocol: To simplify the clock I2C interface, the clock driver serial protocol was specified to use only block writes from the controller. The bytes must be accessed in sequential order from lowest to highest byte with the ability to stop after any complete byte has been transferred. Indexed bytes are not allowed. However, the SMBus controller has a more specific format than the generic I2C protocol. The clock driver must meet this protocol which is more rigorous than previously stated I2C protocol. Treat the description from the viewpoint of controller. The controller “writes” to the clock driver and if possible would “read” from the clock driver (the clock driver is a slave/receiver only and is incapable of this transaction.) “The block write begins with a slave address and a write condition. After the command code the host (controller) issues a byte count which describes how many more bytes will follow in the message. If the host had 20 bytes to send, the first byte would be the number 20 (14h), followed by the 20 bytes of data. The byte count may not be 0. A block write command is allowed to transfer a maximum of 32 data bytes.” 1 bit 7 bits 1 1 8 bits 1 Start bit Slave Address R/W Ack Command Code Ack Ack Data Byte 1 Ack Data Byte 2 Ack 1 bit 8 bits 1 8 bits 1 ... Byte Count = N Data Byte 2 Ack Stop 8 bits 1 1 SW00279 NOTE: The acknowledgement bit is returned by the slave/receiver (the clock driver). 2001 Jul 19 5 Philips Semiconductors Product data 0–300 MHz I2C 1:18 clock buffer PCK2002 Consider the command code and the byte count bytes required as the first two bytes of any transfer. The command code is software programmable via the controller, but will be specified as 0000 0000 in the clock specification. The byte count byte is the number of additional bytes required to transfer, not counting the command code and byte count bytes. Additionally, the byte count byte is required to be a minimum of 1 byte and a maximum of 32 bytes to satisfy the above requirement. For example: Byte count byte Notes: MSB LSB 0000 0000 Not allowed. Must have at least one byte. 0000 0001 Data for functional and frequency select register (currently byte 0 in spec) 0000 0010 Reads first two bytes of data. (byte 0 then byte 1) 0000 0011 Reads first three bytes (byte 0, 1, 2 in order) 0000 0100 Reads first four bytes (byte 0, 1, 2, 3 in order) 0000 0101 Reads first five bytes (byte 0, 1, 2, 3, 4 in order) 0000 0110 Reads first six bytes (byte 0, 1, 2, 3, 4, 5 in order) 0000 0111 Reads first seven bytes (byte 0, 1, 2, 3, 4, 5, 6 in order) 0010 0000 Max byte count supported = 32 A transfer is considered valid after the acknowledge bit corresponding to the byte count is read by the controller. The serial controller interface can be simplified by discarding the information in both the command code and the byte count bytes and simply reading all the bytes that are sent to the clock driver after being addressed by the controller. It is expected that the controller will not provide more bytes than the clock driver can handle. A clock vendor may choose to discard any number of bytes that exceed the defined byte count. 8) Clock stretching: The clock device must not hold/stretch the SCLOCK or SDATA lines low for more than 10 ms. Clock stretching is discouraged and should only be used as a last resort. Stretching the clock/data lines for longer than this time puts the device in an error/time-out mode and may not be supported in all platforms. It is assumed that all data transfers can be completed as specified without the use of clock/data stretching. 9) General Call: It is assumed that the clock driver will not have to respond to the “general call.” 10) Electrical Characteristics: All electrical characteristics must meet the standard mode specifications found in section 15 of the I2C specification. a) Pull-Up Resistors: Any internal resistors pull-ups on the SDATA and SCLOCK inputs must be stated in the individual datasheet. The use of internal pull-ups on these pins of below 100 k Ω is discouraged. Assume that the board designer will use a single external pull-up resistor for each line and that these values are in the 5–6 k Ω range. Assume one I2C device per DIMM (serial presence detect), one I2C controller, one clock driver plus one/two more I2C devices on the platform for capacitive loading purposes. (b) Input Glitch Filters: Only fast mode I2C devices require input glitch filters to suppress bus noise. The clock driver is specified as a standard mode device and is not required to support this feature. 11) PWR DWN: If a clock driver is placed in PWR DWN mode, the SDATA and SCLK inputs must be Tri-Stated and the device must retain all programming information. Idd current due to the I2C circuitry must be characterized and in the data sheet. For specific I2C information consult the Philips I2C Peripherals Data Handbook IC12 (1997). 2001 Jul 19 6 Philips Semiconductors Product data 0–300 MHz I2C 1:18 clock buffer PCK2002 SERIAL CONFIGURATION MAP The serial bits will be read by the clock buffer in the following order: Byte 0 – Bits 7, 6, 5, 4, 3, 2, 1, 0 Byte 1 – Bits 7, 6, 5, 4, 3, 2, 1, 0 Byte 2 – Bits 7, 6, 5, 4, 3, 2, 1, 0 All unused register bits (Reserved and N/A) should be desined as “Don’t Care”. It is expected that the controller will force all of these bits to a “0” level. All register bits labeled “Initialize to 0” must be written to zero during intialization. Failure to do so may result in a higher than normal operating current. The controller will read back the last written value. Byte 0: SDRAM Output active/inactive register 1 = enable; 0 = disable BIT(S) AFFECTED PIN CONTROL FUNCTION BIT CONTROL PIN NO. PIN NAME 0 1 7 18 BUF_OUT7 Clock Output Disable Low Active 6 17 BUF_OUT6 Clock Output Disable Low Active 5 14 BUF_OUT5 Clock Output Disable Low Active 4 13 BUF_OUT4 Clock Output Disable Low Active 3 9 BUF_OUT3 Clock Output Disable Low Active 2 8 BUF_OUT2 Clock Output Disable Low Active 1 5 BUF_OUT1 Clock Output Disable Low Active 0 4 BUF_OUT0 Clock Output Disable Low Active NOTE: 1. At power up all SDRAM outputs are enabled and active. Program all reserved bits to “0”. Byte 1: SDRAM Output active/inactive register 1 = enable; 0 = disable BIT(S) AFFECTED PIN PIN NO. PIN NAME 7 45 BUF_OUT15 6 44 5 41 4 40 3 2 1 CONTROL FUNCTION 1 Clock Output Disable Low Active BUF_OUT14 Clock Output Disable Low Active BUF_OUT13 Clock Output Disable Low Active BUF_OUT12 Clock Output Disable Low Active 36 BUF_OUT11 Clock Output Disable Low Active 35 BUF_OUT10 Clock Output Disable Low Active 32 BUF_OUT9 Clock Output Disable Low Active Low Active 0 31 BUF_OUT8 Clock Output Disable NOTE: 1. At power up all SDRAM outputs are enabled and active. Program all reserved bits to “0”. 2001 Jul 19 BIT CONTROL 0 7 Philips Semiconductors Product data 0–300 MHz I2C 1:18 clock buffer PCK2002 Byte 2: SDRAM Output active/inactive register 1 = enable; 0 = disable BIT(S) AFFECTED PIN PIN NO. PIN NAME N/A BUF_OUT17 6 12 5 N/A 4 3 CONTROL FUNCTION BIT CONTROL 0 1 Clock Output Disable Low Active BUF_OUT16 Clock Output Disable Low Active Reserved (Reserved) — — N/A Reserved (Reserved) — — N/A Reserved (Reserved) — — 2 N/A Reserved (Reserved) — — 1 N/A Reserved (Reserved) — — 0 N/A Reserved (Reserved) — — 7 NOTE: 1. At power up all SDRAM outputs are enabled and active. Program all reserved bits to “0”. 2001 Jul 19 8 Philips Semiconductors Product data 0–300 MHz I2C 1:18 clock buffer PCK2002 AC WAVEFORMS TEST CIRCUIT VM = 1.5 V VX = VOL + 0.3 V VY = VOH –0.3 V VOL and VOH are the typical output voltage drop that occur with the output load. S1 VDD 2<VDD Open VSS VDD BUF_IN INPUT 500Ω VI VM VM VO PULSE GENERATOR tPLH tPHL VM D.U.T. RT CL 500Ω VM BUF_OUT TEST SW00246 Figure 1. Load circuitry for switching times. S1 tPLH/tPHL Open tPLZ/tPZL 2<VDD tPHZ/tPZH VSS VI SW00251 VDD Figure 4. Load circuitry for switching times VM nOE INPUT GND tPLZ tPZL VDD OUTPUT LOW-to-OFF OFF-to-LOW VM VX VOL tPHZ tPZH VOH OUTPUT HIGH-to-OFF OFF-to-HIGH VY VM VSS outputs enabled outputs enabled outputs disabled SW00245 Figure 2. 3-State enable and disable times TSDKP TSDKH DUTY CYCLE 2.4 1.5 0.4 TSDKL TSDRISE TSDFALL SW00247 Figure 3. Buffer Output clock 2001 Jul 19 9 Philips Semiconductors Product data 0–300 MHz I2C 1:18 clock buffer PCK2002 TSSOP48: plastic thin shrink small outline package; 48 leads; body width 6.1 mm 2001 Jul 19 10 SOT362-1 Philips Semiconductors Product data 0–300 MHz I2C 1:18 clock buffer PCK2002 SSOP48: plastic shrink small outline package; 48 leads; body width 7.5 mm 2001 Jul 19 11 SOT370-1 Philips Semiconductors Product data 0–300 MHz I2C 1:18 clock buffer PCK2002 Data sheet status Data sheet status [1] Product status [2] Definitions Objective data Development This data sheet contains data from the objective specification for product development. Philips Semiconductors reserves the right to change the specification in any manner without notice. Preliminary data Qualification This data sheet contains data from the preliminary specification. Supplementary data will be published at a later date. Philips Semiconductors reserves the right to change the specification without notice, in order to improve the design and supply the best possible product. Product data Production This data sheet contains data from the product specification. Philips Semiconductors reserves the right to make changes at any time in order to improve the design, manufacturing and supply. Changes will be communicated according to the Customer Product/Process Change Notification (CPCN) procedure SNW-SQ-650A. [1] Please consult the most recently issued datasheet before initiating or completing a design. [2] The product status of the device(s) described in this data sheet may have changed since this data sheet was published. The latest information is available on the Internet at URL http://www.semiconductors.philips.com. Definitions Short-form specification — The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook. Limiting values definition — Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information — Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Disclaimers Life support — These products are not designed for use in life support appliances, devices or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application. Right to make changes — Philips Semiconductors reserves the right to make changes, without notice, in the products, including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified. Copyright Philips Electronics North America Corporation 2001 All rights reserved. Printed in U.S.A. Philips Semiconductors 811 East Arques Avenue P.O. Box 3409 Sunnyvale, California 94088–3409 Telephone 800-234-7381 Date of release: 07-01 Document order number: 2001 Jul 19 12 9397 750 08585