PHILIPS P87C575EBBB

INTEGRATED CIRCUITS
80C575/83C575/87C575
80C51 8-bit microcontroller family
8K/256 OTP/ROM/ROMless, 4 comparator,
failure detect circuitry, watchdog timer
Product specification
Supersedes data of 1998 Jan 27
IC20 Data Handbook
1998 May 01
Philips Semiconductors
Product specification
80C51 8-bit microcontroller family
80C575/83C575/
87C575
8K/256 OTP/ROM/ROMless, 4 comparator, failure detect circuitry, watchdog timer
DESCRIPTION
FEATURES
The Philips 80C575/83C575/87C575 is a
high-performance microcontroller fabricated
with Philips high-density CMOS technology.
The Philips CMOS technology combines the
high speed and density characteristics of
HMOS with the low power attributes of
CMOS. Philips epitaxial substrate minimizes
latch-up sensitivity.
The 8XC575 contains an 8k × 8 ROM
(83C575) EPROM (87C575), a 256 × 8 RAM,
32 I/O lines, three 16-bit counter/timers, a
Programmable Counter Array (PCA), a
seven-source, two-priority level nested
interrupt structure, an enhanced UART, four
analog comparators, power-fail detect and
oscillator fail detect circuits, and on-chip
oscillator and clock circuits.
In addition, the 8XC575 has a low active
reset, and the port pins are reset to a low
level. There is also a fully configurable
watchdog timer, and internal power on clear
circuit. The part includes idle mode and
power-down mode states for reduced power
consumption.
• 80C51 based architecture
– 8k × 8 ROM (83C575)
– 8k × 8 EPROM (87C575)
PIN CONFIGURATIONS
CMP0+/P1.0/T2
1
40 V
DD
CMP0-/P1.1/T2EX
2
39 P0.0/AD0
ECI/P1.2
– ROMless (80C575)
3
38 P0.1/AD1
– Three 16-bit counter/timers
CMP0/CEX0/P1.3
4
37 P0.2/AD2
– Programmable Counter Array
CMP1/CEX1/P1.4
5
36 P0.3/AD3
– Enhanced UART
CMP2/CEX2/P1.5
6
35 P0.4/AD4
– Boolean processor
CMP3/CEX3/P1.6
7
34 P0.5/AD5
CEX4/P1.7
8
33 P0.6/AD6
RST
9
32 P0.7/AD7
– 256 × 8 RAM
– Oscillator fail detect
– Low active reset
– Asynchronous low port reset
31 EA/V
PP
– Schmitt trigger inputs
RxD/P3.0 10
– 4 analog comparators
TxD/P3.1
11
INT0/P3.2
12
29 PSEN
INT1/P3.3
– Watchdog timer
– Low VCC detect
• Memory addressing capability
– 64k ROM and 64k RAM
• Power control modes:
DUAL
IN-LINE
PACKAGE
30 ALE/PROG
13
28 P2.7/A15
CMPR-/T0/P3.4 14
27 P2.6/A14
CMP1+/T1/P3.5 15
26 P2.5/A13
CMP2+/WR/P3.6 16
25 P2.4/A12
CMP3+/RD/P3.7 17
24 P2.3/A11
– Idle mode
– Power-down mode
• CMOS and TTL compatible
• 4.0 to 16MHz
• Extended temperature ranges
• OTP package available
XTAL2
18
23 P2.2/A10
XTAL1
19
22 P2.1/A9
VSS
20
21 P2.0/A8
6
1
44
40
39
7
1
33
PQFP
LCC
17
29
18
34
11
23
28
12
22
SU00234
ORDERING INFORMATION
TEMPERATURE RANGE °C AND PACKAGE
FREQ
(MHz)
DRAWING
NUMBER
OTP
0 to +70, 40-Pin Plastic Dual In-line Package
16
SOT129-1
OTP
0 to +70, 44-Pin Plastic Leaded Chip Carrier
16
SOT187-2
P87C575EHAA
OTP
–40 to +125, 44-Pin Plastic Leaded Chip Carrier
16
SOT187-2
P87C575EBBB
OTP
0 to +70, 44-Pin Plastic Quad Flat Pack
16
SOT307-2
EPROM1
ROMless
ROM
P80C575EBP N
P83C575EBP N
P87C575EBPN
P80C575EBA A
P83C575EBA A
P87C575EBAA
P80C575EHAA
P83C575EHAA
P80C575EBB B
P83C575EBB B
NOTE:
1. OTP - One Time Programmable EPROM.
1998 May 01
2
853-1684 19332
Philips Semiconductors
Product specification
80C51 8-bit microcontroller family
80C575/83C575/
87C575
8K/256 OTP/ROM/ROMless, 4 comparator, failure detect circuitry, watchdog timer
BLOCK DIAGRAM
P0.0-P0.7
P2.0-P2.7
PORT 0
DRIVERS
PORT 2
DRIVERS
VCC
VSS
RAM ADDR
REGISTER
PORT 0
LATCH
RAM
B
REGISTER
ROM/
EPROM
PORT 2
LATCH
STACK
POINTER
ACC
PROGRAM
ADDRESS
REGISTER
TMP1
TMP2
BUFFER
ALU
SFRs
TIMERS
PCA
PSW
PC
INCREMENTER
PSEN
ALE
EA
TIMING
AND
CONTROL
RST
INSTRUCTION
REGISTER
PROGRAM
COUNTER
PD
DPTR
PORT 1
LATCH
PORT 3
LATCH
PORT 1
DRIVERS
PORT 3
DRIVERS
P1.0-P1.7
P3.0-P3.7
OSCILLATOR
XTAL1
XTAL2
SU00238
1998 May 01
3
Philips Semiconductors
Product specification
80C51 8-bit microcontroller family
8K/256 OTP/ROM/ROMless, 4 comparator, failure detect circuitry, watchdog timer
CERAMIC AND PLASTIC LEADED
CHIP CARRIER PIN FUNCTIONS
6
1
PLASTIC QUAD FLAT PACK
PIN FUNCTIONS
44
40
7
34
39
1
33
LCC
PQFP
17
11
29
18
28
12
Function
NC*
T2/P1.0/CMP0+
T2EX/P1.1/CMP0–
Pin
23
24
25
Function
NC*
P2.0/A8
P2.1/A9
Pin
1
2
3
4
5
6
7
P1.2/ECI
P1.3/CMP0/CEX0
P1.4/CMP1/CEX1
P1.5/CMP2/CEX2
26
27
28
29
P2.2/A10
P2.3/A11
P2.4/A12
P2.5/A13
4
5
6
7
8
9
10
11
P1.6/CMP3/CEX3
P1.7/CEX4
RST
RxD/P3.0
30
31
32
33
P2.6/A14
P2.7/A15
PSEN
ALE/PROG
12
13
14
15
NC*
TxD/P3.1
INT0/P3.2
INT1/P3.3
34
35
36
37
16
17
18
19
T0/P3.4/CMPR–
T1/P3.5/CMP1+
WR/P3.6/CMP2+
RD/P3.7/CMP3+
20
21
22
XTAL2
XTAL1
VSS
Pin
1
2
3
23
22
Function
P1.5/CMP2/CEX2
P1.6/CMP3/CEX3
P1.7/CEX4
Pin
23
24
25
Function
P2.5/A13
P2.6/A14
P2.7/A15
RST
RxD/P3.0
NC*
TxD/P3.1
26
27
28
29
PSEN
ALE/PROG
NC*
EA/VPP
8
9
10
11
INT0/P3.2
INT1/P3.3
T0/P3.4/CMPR–
T1/P3.5/CMP1+
30
31
32
33
P0.7/AD7
P0.6/AD6
P0.5/AD5
P0.4/AD4
NC*
EA/VPP
P0.7/AD7
P0.6/AD6
12
13
14
15
WR/P3.6/CMP2+
RD/P3.7CMP3+
XTAL2
XTAL1
34
35
36
37
P0.3/AD3
P0.2/AD2
P0.1/AD1
P0.0/AD0
38
39
40
41
P0.5/AD5
P0.4/AD4
P0.3/AD3
P0.2/AD2
16
17
18
19
VSS
NC*
P2.0/A8
P2.1/A9
38
39
40
41
VCC
NC*
T2/P1.0/CMP0+
T2EX/P1.1/CMP0–
42
43
44
P0.1/AD1
P0.0/AD0
VCC
20
21
22
P2.2/A10
P2.3/A11
P2.4/A12
42
43
44
P1.2/ECI
P1.3/CMP0/CEX0
P1.4/CMP1/CEX1
* NO INTERNAL CONNECTION
* NO INTERNAL CONNECTION
SU00235
LOGIC SYMBOL
VCC
VSS
PORT 0
XTAL1
ADDRESS AND
DATA BUS
XTAL2
PORT 2
ALE/PROG
RxD
TxD
INT0
INT1
T0
T1
WR
RD
PORT 3
CMPR–
CMP1+
CMP2+
CMP3+
SECONDARY FUNCTIONS
RST
EA/VPP
PSEN
PORT 1
T2
T2EX
CMP0+
CMP0–
ECI
CMP0/CEX0
CMP1/CEX1
CMP2/CEX2
CMP3/CEX3
CEX4
ADDRESS BUS
SU00237
1998 May 01
4
SU00236
80C575/83C575/
87C575
Philips Semiconductors
Product specification
80C51 8-bit microcontroller family
8K/256 OTP/ROM/ROMless, 4 comparator, failure detect circuitry, watchdog timer
80C575/83C575/
87C575
PIN DESCRIPTIONS
PIN NUMBER
MNEMONIC
DIP
LCC
QFP
TYPE
VSS
20
22
16
I
Ground: 0V reference.
VCC
40
44
38
I
Power Supply: This is the power supply voltage for normal, idle, and power-down
operation.
39-32
43-36
37-30
I/O
Port 0: Port 0 is an open-drain bidirectional I/O port. Port 0 pins that have 1s written to them
float and can be used as high-impedance inputs. Port 0 is also the multiplexed low-order
address and data bus during accesses to external program and data memory. In this
application, it uses strong internal pull-ups when emitting 1s. Port 0 also receives code
bytes during EPROM programming and outputs code bytes during program verification.
External pull-ups are required during program verification. During reset, port 0 will be
asynchronously driven low and will remain low until written to by software. All port 0 pins
have Schmitt trigger inputs with 200mV hysteresis. A weak pulldown on port 0 guarantees
positive leakage current (see DC Electrical Characteristics: IL1).
1-8
2-9
40-44
1-3
I/O
1
2
40
I/O
2
3
41
I
3
4
4
5
42
43
I
I/O
5
6
44
I/O
6
7
1
I/O
7
8
2
I/O
Port 1: Port 1 is an 8-bit bidirectional I/O port. Port 1 pins have internal pull-ups such that
pins that have 1s written to them can be used as inputs but will source current when
externally pulled low (see DC Electrical Characteristics: IIL). Port 1 receives the low-order
address byte during program memory verification and EPROM programming. During reset,
port 1 will be asynchronously driven low and will remain low until written to by software. All
port 1 pins have Schmitt trigger inputs with 50mV hysteresis. Port 1 pins also serve
alternate functions as follows:
P1.0 T2
Timer 2 external I/O – clockout (programmable)
CMP0+ Comparator 0 positive input
P1.1 T2EX
Timer 2 capture input
CMP0- Comparator 0 negative input
P1.2 ECI
PCA count input
P1.3 CEX0
PCA module 0 external I/O
CMP0
Comparator 0 output
P1.4 CEX1
PCA module 1 external I/O
CMP1
Comparator 1 output
P1.5 CEX2
PCA module 2 external I/O
CMP2
Comparator 2 output
P1.6 CEX3
PCA module 3 external I/O
CMP3
Comparator 3 output
P1.7 CEX4
PCA module 4 external I/O
P0.0-0.7
P1.0-P1.7
NAME AND FUNCTION
8
9
3
I/O
P2.0-P2.7
21-28
24-31
18-25
I/O
Port 2: Port 2 is an 8-bit bidirectional I/O port with internal pull-ups. Port 2 pins that have 1s
written to them can be used as inputs, but will source current when externally pulled low
(see DC Electrical Characteristics: IIL). Port 2 emits the high-order address byte during
accesses to external program and data memory that use 16-bit addresses (MOVX
@DPTR). In this application, it uses strong internal pull-ups when emitting 1s. Port 2
receives the high-order address byte during program verification and EPROM programming.
During reset, port 2 will be asynchronously driven low and will remain low until written to by
software. Port 2 can be made open drain by writing to the P2OD register (AIH). In open
drain mode, weak pulldowns on port 2 guarantee positive leakage current (see DC
Electrical Characteristics IL1).
P3.0-P3.7
10-17
11,
13-19
5,
7-13
I/O
Port 3: Port 3 is an 8-bit bidirectional I/O port with internal pull-ups. Port 3 pins except P3.1
that have 1s written to them can be used as inputs but will source current when externally
pulled low (see DC Electrical Characteristics: IIL). P3.1 will be a high impedance pin except
while transmitting serial data, in which case the strong pull-up will remain on continuously
when outputting a 1 level. The P3.1 output drive level when transmitting can be set to one of
two levels by the writing to the P3.1 register bit. During reset all pins (except P3.1) will be
asynchronously driven low and will remain low until written to by software. All port 3 pins
have Schmitt trigger inputs with 200mV hysteresis, except P3.2 and P3.3, which have 50mV
hysteresis. Port 3 pins serve alternate functions as follows:
1998 May 01
5
Philips Semiconductors
Product specification
80C51 8-bit microcontroller family
8K/256 OTP/ROM/ROMless, 4 comparator, failure detect circuitry, watchdog timer
80C575/83C575/
87C575
PIN DESCRIPTIONS (Continued)
PIN NUMBER
MNEMONIC
DIP
LCC
QFP
TYPE
10
11
12
13
14
11
13
14
15
16
5
7
8
9
10
I
O
I
I
I
15
17
11
I
16
18
12
O
17
19
13
O
RST
9
10
4
I
Reset: A low on this pin asynchronously resets all port pins to a low state except P3.1. The
pin must be held low with the oscillator running for 24 oscillator cycles to initialize the
internal registers. An internal diffused resistor to VCC permits a power on reset using only
an external capacitor to VSS. RST has a Schmitt trigger input stage to provide additional
noise immunity with a slow rising input voltage.
ALE/PROG
30
33
27
I/O
Address Latch Enable/Program Pulse: Output pulse for latching the low byte of the
address during an access to external memory. In normal operation, ALE is emitted at a
constant rate of 1/6 the oscillator frequency, and can be used for external timing or clocking.
Note that one ALE pulse is skipped during each access to external data memory. ALE is
switched off if the bit 0 in the AUXR register (8EH) is set. This pin is also the program pulse
input (PROG) during EPROM programming.
PSEN
29
32
26
O
Program Store Enable: The read strobe to external program memory. When the device is
executing code from the external program memory, PSEN is activated twice each machine
cycle, except that two PSEN activations are skipped during each access to external data
memory. PSEN is not activated during fetches from internal program memory.
EA/VPP
31
35
29
I
External Access Enable/Programming Supply Voltage: EA must be externally held low
to enable the device to fetch code from external program memory locations 0000H to
1FFFH. If EA is held high, the device executes from internal program memory unless the
program counter contains an address greater than 1FFFH. This pin also receives the
12.75V programming supply voltage (VPP) during EPROM programming.
XTAL1
19
21
15
I
Crystal 1: Input to the inverting oscillator amplifier and input to the internal clock generator
circuits.
XTAL2
18
20
14
O
Crystal 2: Output from the inverting oscillator amplifier.
1998 May 01
NAME AND FUNCTION
Port 3: (continued)
P3.0 RxD
Serial receive port
P3.1 TxD
Serial transmit port enabled only when transmitting serial data
P3.2 INT0
External interrupt 0
P3.3 INT1
External interrupt 1
P3.4 T0
Timer/counter 0 input
CMPR- Common - reference to comparators 1, 2, 3
P3.5 T1
Timer/counter 1 input
CMP1+ Comparator 1 positive input
P3.6 WR
External data memory write strobe
CMP2+ Comparator 2 positive input
P3.7 RD
External data memory read strobe
CMP3+ Comparator 3 positive input
6
Philips Semiconductors
Product specification
80C51 8-bit microcontroller family
80C575/83C575/
87C575
8K/256 OTP/ROM/ROMless, 4 comparator, failure detect circuitry, watchdog timer
Table 1.
87C575 Special Function Registers
DIRECT
ADDRESS
E0H
8EH
F0H
FAH
FBH
FCH
FDH
FEH
EAH
EBH
ECH
EDH
EEH
SYMBOL
DESCRIPTION
ACC*
AUXR#
B*
CCAP0H#
CCAP1H#
CCAP2H#
CCAP3H#
CCAP4H#
CCAP0L#
CCAP1L#
CCAP2L#
CCAP3L#
CCAP4L#
Accumulator
Auxiliary
B register
Module 0 Capture High
Module 1 Capture High
Module 2 Capture High
Module 3 Capture High
Module 4 Capture High
Module 0 Capture Low
Module 1 Capture Low
Module 2 Capture Low
Module 3 Capture Low
Module 4 Capture Low
CCAPM0#
CCAPM1#
CCAPM2#
CCAPM3#
CCAPM4#
Module 0 Mode
Module 1 Mode
Module 2 Mode
Module 3 Mode
Module 4 Mode
DAH
DBH
DCH
DDH
DEH
CCON*#
CH#
CL#
CMOD#
PCA Counter Control
PCA Counter High
PCA Counter Low
PCA Counter Mode
D8H
F9H
E9H
D9H
CMP*#
CMPE#
Comparator
Comparator Enable
E8H
91H
DPTR:
DPH
DPL
Data Pointer (2 bytes)
Data Pointer High
Data Pointer Low
83H
82H
IE*
Interrupt Enable
A8H
IP*
Interrupt Priority
P0*
BIT ADDRESS, SYMBOL, OR ALTERNATIVE PORT FUNCTION
MSB
LSB
E7
E6
E5
E4
E3
E2
E1
E0
–
–
–
–
–
–
LO
AO
F7
F6
F5
F4
F3
F2
F1
F0
–
–
–
–
–
ECOM
ECOM
ECOM
ECOM
ECOM
CAPP
CAPP
CAPP
CAPP
CAPP
CAPN
CAPN
CAPN
CAPN
CAPN
MAT
MAT
MAT
MAT
MAT
TOG
TOG
TOG
TOG
TOG
PWM
PWM
PWM
PWM
PWM
ECCF
ECCF
ECCF
ECCF
ECCF
DF
CF
DE
CR
DD
–
DC
CCF4
DB
CCF3
DA
CCF2
D9
CCF1
D8
CCF0
CIDL
WDTE
–
–
–
CPS1
CPS0
ECF
EF
EC3DP
EC3TDC
EE
EC2DP
EC2TDC
ED
EC1DP
EC1TDC
EC
EC0DP
EC0TDC
EB
C3RO
EC3OD
EA
C2RO
EC2OD
E9
C1RO
EC1OD
E8
C0RO
EC0OD
x0000000B
x0000000B
x0000000B
x0000000B
x0000000B
00x00000B
00H
00H
00xxx000B
00H
00H
00H
00H
B8H
AF
EA
BF
–
AE
EC
BE
PPC
AD
ET2
BD
PT2
AC
ES
BC
PS
AB
ET1
BB
PT1
AA
EX1
BA
PX1
A9
ET0
B9
PT0
A8
EX0
B8
PX0
Port 0
80H
87
AD7
86
AD6
85
AD5
84
AD4
83
AD3
82
AD2
81
AD1
80
AD0
97
96
95
94
93
92
91
90
P1*
Port 1
90H
CEX4
CEX3
CEX2
CEX1
CEX0
EXI
T2EX
T2
A7
A6
A5
A4
A3
A2
A1
A0
P2*
Port 2
A0H
AD15
AD14
AD13
AD12
AD11
AD10
AD9
AD8
B7
B6
B5
B4
B3
B2
B1
B0
P3*
Port 3
B0H
RD
* SFRs are bit addressable.
# SFRs are modified from or added to the 80C51 SFRs.
1. 87C575 only.
WR
T1
T0
INT1
INT0
TxD
RxD
1998 May 01
RESET
VALUE
00H
xxxxxx00B
00H
xxxxxxxxB
xxxxxxxxB
xxxxxxxxB
xxxxxxxxB
xxxxxxxxB
xxxxxxxxB
xxxxxxxxB
xxxxxxxxB
xxxxxxxxB
xxxxxxxxB
7
00H
x0000000B
00H
00H
00H
00H
Philips Semiconductors
Product specification
80C51 8-bit microcontroller family
80C575/83C575/
87C575
8K/256 OTP/ROM/ROMless, 4 comparator, failure detect circuitry, watchdog timer
Table 1.
SYMBOL
87C575 Special Function Registers (Continued)
DESCRIPTION
DIRECT
ADDRESS
BIT ADDRESS, SYMBOL, OR ALTERNATIVE PORT FUNCTION
MSB
LSB
RESET
VALUE
P2OD#
Port 2 Pullup Disable
A1H
00H
PCON#
Power Control
87H
SMOD1
PSW*
Program Status Word
D0H
RACAP2H#
RACAP2L#
Timer 2 Capture High
Timer 2 Capture Low
CBH
CAH
00H
00H
SADDR#
SADEN#
Slave Address
Slave Address Mask
A9H
B9H
00H
00H
SBUF
Serial Data Buffer
99H
xxxxxxxxB
SCON*
Serial Control
98H
SP
Stack Pointer
81H
TCON*
Timer Control
88H
SMOD0
OSF1
POF1
D7
D6
D5
D4
CY
AC
F0
RS1
LVF1
GF0
PD
IDL
D3
D2
D1
D0
RS0
OV
–
P
9F
9E
9D
9C
9B
9A
99
98
SM0
SM1
SM2
REN
TB8
RB8
TI
RI
8F
8E
8D
8C
8B
8A
89
88
TF1
TR1
TF0
TR0
IE1
IT1
IE0
IT0
CF
CE
CD
CC
CB
CA
C9
C8
Timer 2 Control
C8H
TF2
EXF2
RCLK
TCLK
EXEN2
TR2
C/T2
CP/RL2
T2MOD#
Timer 2 Mode Control
C9H
–
–
–
–
–
–
T2OE2
DCEN
TH0
TH1
TH2#
TL0
TL1
TL2#
Timer High 0
Timer High 1
Timer High 2
Timer Low 0
Timer Low 1
Timer Low 2
8CH
8DH
CDH
8AH
8BH
CCH
TMOD
Timer Mode
89H
GATE
C7
C6
C5
C4
C3
C2
C1
C0
WDCON*#
Watchdog Timer Control
C0H
PRE2
PRE1
PRE0
LVRE
OFRE
WDRUN
WDTOF
WDMOD
WDL#
WFEED1#
WFEED2#
Watchdog Timer Reload
Watchdog Feed 1
Watchdog Feed 2
C1H
C2H
C3H
00H
00H
00H
xxxxxxx0B
00H
00H
00H
00H
00H
00H
C/T
M1
M0
GATE
C/T
M1
M0
00H
11111101B
00H
xxH
xxH
SFRs are bit addressable.
SFRs are modified from or added to the 80C51 SFRs.
Reset value depends on reset source.
Programmable clock-out.
1998 May 01
00H
07H
T2CON*
*
#
1.
2.
00xxx000B
8
Philips Semiconductors
Product specification
80C51 8-bit microcontroller family
80C575/83C575/
87C575
8K/256 OTP/ROM/ROMless, 4 comparator, failure detect circuitry, watchdog timer
POWER ON CLEAR/
POWER ON FLAG
LOW ACTIVE RESET
An on-chip Power On Detect Circuit resets
the 8XC575 and sets the Power Off Flag
(PCON.4) on power up or if VCC drops to
zero momentarily. The POF can only be
cleared by software. The RST pin is not
driven by the power on detect circuit. The
POF can be read by software to determine
that a power failure has occurred and can
also be set by software.
LOW VOLTAGE DETECT
An on-chip Low Voltage Detect circuit sets
the Low Voltage Flag (PCON.3) if VCC drops
below VLOW (see DC Electrical
Characteristics) and resets the 8XC575 if the
Low Voltage Reset Enable bit (WDCON.4) is
set. If the LVRE is cleared, the reset is
disabled but LVF will still be set if VCC is low.
The RST pin is not driven by the low voltage
detect circuit. The LVF can be read by
software to determine that VCC was low. The
LVF can be set or cleared by software.
OSCILLATOR FAIL DETECT
An on-chip Oscillator Fail Detect circuit sets
the Oscillator Fail Flag (PCON.5) if the
oscillator frequency drops below OSCF for
one or more cycles (see AC Electrical
Characteristics: OSCF) and resets the
8XC575 if the Oscillator Fail Reset Enable bit
(WDCON.3) is set. If OFRE is cleared, the
reset is disabled but OSF will still be set if the
oscillator fails. The RST pin is not driven by
the oscillator fail detect circuit. The OSF can
be read by software to determine that an
oscillator failure has occurred. The OSF can
be set or cleared by software.
VCC
One of the most notable features on this part
is the low active reset. At this time this is the
only 80C51 derivative available that has low
active reset. This feature makes it easier to
interface the 8XC575 into an application to
accommodate the power-on and low voltage
conditions that can occur. The low active
reset operates exactly the same as high
active reset with the exception that the part is
put into the reset mode by applying a low
level to the reset pin. For power-on reset it is
also necessary to invert the power-on reset
circuit; connecting the 8.2K resistor from the
reset pin to VCC and the 10µf capacitor from
the reset pin to ground. Figure 1 shows all of
the reset related circuitry.
When reset the port pins on the 87C575 are
driven low asynchronously. This is different
from all other 80C51 derivatives.
The 8XC575 also has Low voltage detection
circuitry that will, if enabled, force the part to
reset when VCC (on the part) fails below a set
level. Low Voltage Reset is enabled by a
normal reset. Low Voltage Reset can be
disabled by clearing LVRE (bit 4 in the
WDCON SFR) then executing a watchdog
feed sequence (A5H to WFEED1 followed
immediately by 5A to WFEED2). In addition
there is a flag (LVF) that is set if a low voltage
condition is detected. The LVF flag is set
even if the Low Voltage detection circuitry is
disabled. Notice that the Low voltage
detection circuitry does not drive the RST#
pin so the LVF flag is the only way that the
microcontroller can determine if it has been
reset due to a low voltage condition.
SMOD1
SMOD0
OSF
POF
LVF
GF0
The 8XC575 has an on-chip power-on
detection circuit that sets the POF (PCON.4)
flag on power up or if the VCC level
momentarily drops to 0V. This flag can be
used to determine if the part is being started
from a power-on (cold start) or if a reset has
occurred due to another condition (warm
start).
TIMERS
The 87C575 has four on-chip timers.
Timers 0 and 1 are identical in every way to
Timers 0 and 1 on the 80C51.
Timer 2 on the 8XC575 is identical to the
80C52 Timer 2 (described in detail in the
80C52 overview) with the exception that it is
an up or down counter. To configure the
Timer to count down the DCEN bit in the
T2MOD special function register must be set
and a low level must be present on the T2EX
pin (P1.1).
The Watchdog timer operation and
implementation is the same as that for the
8XC550 (described in the 8XC550 overview)
with the exception that the reset values of the
WDCON and WDL special function registers
have been changed. The changes in these
registers cause the watchdog timer to be
enabled with a timeout of 98304 × TOSC
when the part is reset. The watchdog can be
disabled by executing a valid feed sequence
and then clearing WDRUN (bit 2 in the
WDCON SFR).
GF1
IDL
PCON
(87GH)
POWER-ON DETECT
VLOW
(LOW VCC
REFERENCE)
8xC575
INTERNAL
RESET
+
–
RST
OSC FREQ BELOW OSCF
(MIN FREQUENCY)
PCA WATCHDOG
SHADOW REGISTER
FOR WDCON
WATCHDOG TIMER
WATCHDOG FEED
PRE2
PRE1
PRE0
LVRE
OFRE
WDRUN
WDTOF
WDMOD
WDCON
(C0H)
SU00239
Figure 1. Reset Circuitry
1998 May 01
9
Philips Semiconductors
Product specification
80C51 8-bit microcontroller family
80C575/83C575/
87C575
8K/256 OTP/ROM/ROMless, 4 comparator, failure detect circuitry, watchdog timer
PROGRAMMABLE COUNTER
ARRAY (PCA)
The Programmable Counter Array is a
special Timer that has five 16-bit
capture/compare modules associated with it.
Each of the modules can be programmed to
operate in one of four modes: rising and/or
falling edge capture, software timer,
high-speed output, or pulse width modulator.
Each module has a pin associated with it in
port 1. Module 0 is connected to P1.3(CEX0),
module 1 to P1.4(CEX1), etc.. The basic
PCA configuration is shown in Figure 2.
The PCA timer is a common time base for all
five modules and can be programmed to run
at: 1/12 the oscillator frequency, 1/4 the
oscillator frequency, the Timer 0 overflow, or
the input on the ECI pin (P1.2). The timer
count source is determined from the CPS1
and CPS0 bits in the CMOD SFR as follows
(see Figure 3):
CPS1 CPS0 PCA Timer Count Source
0
0
1/12 oscillator frequency
0
1
1/4 oscillator frequency
1
0
Timer 0 overflow
1
1
External Input at ECI pin
In the CMOD SFR are three additional bits
associated with the PCA. They are CIDL
which allows the PCA to stop during idle
mode, WDTE which enables or disables the
watchdog function on module 4, and ECF
which when set causes an interrupt and the
PCA overflow flag CF (in the CCON SFR) to
be set when the PCA timer overflows. These
functions are shown in Figure 3.
The watchdog timer function is implemented
in module 4 as implemented in other parts
that have a PCA that are available on the
market. However, if a watchdog timer is
required in the target application, it is
recommended to use the hardware watchdog
timer that is implemented on the 87C575
separately from the PCA (see Figure 14).
The CCON SFR contains the run control bit
for the PCA and the flags for the PCA timer
(CF) and each module (refer to Figure 6). To
run the PCA the CR bit (CCON.6) must be
set by software. The PCA is shut off by
clearing this bit. The CF bit (CCON.7) is set
when the PCA counter overflows and an
interrupt will be generated if the ECF bit in
the CMOD register is set, The CF bit can only
be cleared by software. Bits 0 through 4 of
the CCON register are the flags for the
modules (bit 0 for module 0, bit 1 for module
1, etc.) and are set by hardware when either
a match or a capture occurs. These flags
also can only be cleared by software. The
PCA interrupt system shown in Figure 4.
Each module in the PCA has a special
function register associated with it. These
registers are: CCAPM0 for module 0,
CCAPM1 for module 1, etc. (see Figure 7).
The registers contain the bits that control the
mode that each module will operate in. The
ECCF bit (CCAPMn.0 where n=0, 1, 2, 3, or
4 depending on the module) enables the CCF
flag in the CCON SFR to generate an
interrupt when a match or compare occurs in
the associated module. PWM (CCAPMn.1)
enables the pulse width modulation mode.
The TOG bit (CCAPMn.2) when set causes
the CEX output associated with the module to
toggle when there is a match between the
PCA counter and the module’s
capture/compare register. The match bit MAT
(CCAPMn.3) when set will cause the CCFn
bit in the CCON register to be set when there
is a match between the PCA counter and the
module’s capture/compare register.
The next two bits CAPN (CCAPMn.4) and
CAPP (CCAPMn.5) determine the edge that
a capture input will be active on. The CAPN
bit enables the negative edge, and the CAPP
bit enables the positive edge. If both bits are
set both edges will be enabled and a capture
will occur for either transition. The last bit in
the register ECOM (CCAPMn.6) when set
enables the comparator function. Figure 8
shows the CCAPMn settings for the various
PCA functions.
There are two additional registers associated
with each of the PCA modules. They are
CCAPnH and CCAPnL and these are the
registers that store the 16-bit count when a
capture occurs or a compare should occur.
When a module is used in the PWM mode
these registers are used to control the duty
cycle of the output.
PCA Capture Mode
To use one of the PCA modules in the
capture mode either one or both of the
CCAPM bits CAPN and CAPP for that
module must be set. The external CEX input
for the module (on port 1) is sampled for a
transition. When a valid transition occurs the
PCA hardware loads the value of the PCA
counter registers (CH and CL) into the
module’s capture registers (CCAPnL and
CCAPnH). If the CCFn bit for the module in
the CCON SFR and the ECCFn bit in the
CCAPMn SFR are set then an interrupt will
be generated. Refer to Figure 9.
16-bit Software Timer Mode
The PCA modules can be used as software
timers by setting both the ECOM and MAT
bits in the modules CCAPMn register. The
PCA timer will be compared to the module’s
capture registers and when a match occurs
an interrupt will occur if the CCFn (CCON
SFR) and the ECCFn (CCAPMn SFR) bits for
the module are both set (see Figure 10).
High Speed Output Mode
In this mode the CEX output (on port 1)
associated with the PCA module will toggle
each time a match occurs between the PCA
counter and the module’s capture registers.
To activate this mode the TOG, MAT, and
ECOM bits in the module’s CCAPMn SFR
must be set (see Figure 11).
16 BITS
MODULE 0
P1.3/CEX0
MODULE 1
P1.4/CEX1
MODULE 2
P1.5/CEX2
MODULE 3
P1.6/CEX3
MODULE 4
P1.7/CEX4
16 BITS
PCA TIMER/COUNTER
TIME BASE FOR PCA MODULES
MODULE FUNCTIONS:
16-BIT CAPTURE
16-BIT TIMER
16-BIT HIGH SPEED OUTPUT
8-BIT PWM
WATCHDOG TIMER (MODULE 4 ONLY)
SU00032
Figure 2. Programmable Counter Array (PCA)
1998 May 01
10
Philips Semiconductors
Product specification
80C51 8-bit microcontroller family
80C575/83C575/
87C575
8K/256 OTP/ROM/ROMless, 4 comparator, failure detect circuitry, watchdog timer
TO PCA
MODULES
OSC/12
OVERFLOW
OSC/4
CH
INTERRUPT
CL
16–BIT UP COUNTER
TIMER 0
OVERFLOW
EXTERNAL INPUT
(P1.2/ECI)
00
01
10
11
DECODE
IDLE
CIDL
CF
WDTE
––
––
––
CPS1
CPS0
ECF
CMOD
(D9H)
CR
––
CCF4
CCF3
CCF2
CCF1
CCF0
CCON
(D8H)
SU00033
Figure 3. PCA Timer/Counter
CF
CR
––
CCF4
CCF3
CCF2
CCF1
CCF0
CCON
(D8H)
PCA TIMER/COUNTER
MODULE 0
IE.6
EC
IE.7
EA
TO
INTERRUPT
PRIORITY
DECODER
MODULE 1
MODULE 2
MODULE 3
MODULE 4
CMOD.0
ECF
CCAPMn.0
ECCFn
SU00034
Figure 4. PCA Interrupt System
1998 May 01
11
Philips Semiconductors
Product specification
80C51 8-bit microcontroller family
80C575/83C575/
87C575
8K/256 OTP/ROM/ROMless, 4 comparator, failure detect circuitry, watchdog timer
CMOD Address = OD9H
Reset Value = 00XX X000B
CIDL
WDTE
–
–
–
CPS1
7
6
5
4
3
2
Bit:
CPS0
1
ECF
0
Symbol
Function
CIDL
Counter Idle control: CIDL = 0 programs the PCA Counter to continue functioning during idle Mode. CIDL = 1 programs
it to be gated off during idle.
WDTE
Watchdog Timer Enable: WDTE = 0 disables Watchdog Timer function on PCA Module 4. WDTE = 1 enables it.
–
Not implemented, reserved for future use.*
CPS1
PCA Count Pulse Select bit 1.
CPS0
PCA Count Pulse Select bit 0.
CPS1
CPS0
Selected PCA Input**
0
0
1
1
ECF
0
1
0
1
Internal clock, fOSC ÷ 12
Internal clock, fOSC ÷ 4
Timer 0 overflow
External clock at ECI/P1.2 pin (max. rate = fOSC ÷ 8)
0
1
2
3
PCA Enable Counter Overflow interrupt: ECF = 1 enables CF bit in CCON to generate an interrupt. ECF = 0 disables
that function of CF.
NOTE:
* User software should not write 1s to reserved bits. These bits may be used in future 8051 family products to invoke new features. In that case, the reset or inactive value of the
new bit will be 0, and its active value will be 1. The value read from a reserved bit is indeterminate.
** fOSC = oscillator frequency
SU00035
Figure 5. CMOD: PCA Counter Mode Register
CCON Address = OD8H
Reset Value = 00X0 0000B
Bit Addressable
Bit:
CF
CR
–
CCF4
CCF3
CCF2
CCF1
CCF0
7
6
5
4
3
2
1
0
Symbol
Function
CF
PCA Counter Overflow flag. Set by hardware when the counter rolls over. CF flags an interrupt if bit ECF in CMOD is
set. CF may be set by either hardware or software but can only be cleared by software.
CR
PCA Counter Run control bit. Set by software to turn the PCA counter on. Must be cleared by software to turn the PCA
counter off.
–
Not implemented, reserved for future use*.
CCF4
PCA Module 4 interrupt flag. Set by hardware when a match or capture occurs. Must be cleared by software.
CCF3
PCA Module 3 interrupt flag. Set by hardware when a match or capture occurs. Must be cleared by software.
CCF2
PCA Module 2 interrupt flag. Set by hardware when a match or capture occurs. Must be cleared by software.
CCF1
PCA Module 1 interrupt flag. Set by hardware when a match or capture occurs. Must be cleared by software.
CCF0
PCA Module 0 interrupt flag. Set by hardware when a match or capture occurs. Must be cleared by software.
NOTE:
* User software should not write 1s to reserved bits. These bits may be used in future 8051 family products to invoke new features. In that case, the reset or inactive value of the
new bit will be 0, and its active value will be 1. The value read from a reserved bit is indeterminate.
SU00036
Figure 6. CCON: PCA Counter Control Register
1998 May 01
12
Philips Semiconductors
Product specification
80C51 8-bit microcontroller family
80C575/83C575/
87C575
8K/256 OTP/ROM/ROMless, 4 comparator, failure detect circuitry, watchdog timer
CCAPMn Address
CCAPM0
CCAPM1
CCAPM2
CCAPM3
CCAPM4
0DAH
0DBH
0DCH
0DDH
0DEH
Reset Value = X000 0000B
Not Bit Addressable
Bit:
–
ECOMn
CAPPn
CAPNn
MATn
TOGn
PWMn
ECCFn
7
6
5
4
3
2
1
0
Symbol
Function
–
ECOMn
CAPPn
CAPNn
MATn
Not implemented, reserved for future use*.
Enable Comparator. ECOMn = 1 enables the comparator function.
Capture Positive, CAPPn = 1 enables positive edge capture.
Capture Negative, CAPNn = 1 enables negative edge capture.
Match. When MATn = 1, a match of the PCA counter with this module’s compare/capture register causes the CCFn bit
in CCON to be set, flagging an interrupt.
Toggle. When TOGn = 1, a match of the PCA counter with this module’s compare/capture register causes the CEXn
pin to toggle.
Pulse Width Modulation Mode. PWMn = 1 enables the CEXn pin to be used as a pulse width modulated output.
Enable CCF interrupt. Enables compare/capture flag CCFn in the CCON register to generate an interrupt.
TOGn
PWMn
ECCFn
NOTE:
*User software should not write 1s to reserved bits. These bits may be used in future 8051 family products to invoke new features. In that case, the reset or inactive value of the new
bit will be 0, and its active value will be 1. The value read from a reserved bit is indeterminate.
SU00037
Figure 7. CCAPMn: PCA Modules Compare/Capture Registers
–
ECOMn
CAPPn
CAPNn
MATn
TOGn
PWMn
ECCFn
X
0
0
0
0
0
0
0
No operation
MODULE FUNCTION
X
X
1
0
0
0
0
X
16-bit capture by a positive-edge trigger on CEXn
X
X
0
1
0
0
0
X
16-bit capture by a negative trigger on CEXn
X
X
1
1
0
0
0
X
16-bit capture by a transition on CEXn
X
1
0
0
1
0
0
X
16-bit Software Timer
X
1
0
0
1
1
0
X
16-bit High Speed Output
X
1
0
0
0
0
1
0
8-bit PWM
X
1
0
0
1
X
0
X
Watchdog Timer
Figure 8. PCA Module Modes (CCAPMn Register)
1998 May 01
13
Philips Semiconductors
Product specification
80C51 8-bit microcontroller family
80C575/83C575/
87C575
8K/256 OTP/ROM/ROMless, 4 comparator, failure detect circuitry, watchdog timer
CF
CR
––
CCF4
CCF3
CCF2
CCF1
CCON
(D8H)
CCF0
PCA INTERRUPT
(TO CCFn)
PCA TIMER/COUNTER
CH
CL
CCAPnH
CCAPnL
CAPTURE
CEXn
––
ECOMn
CAPPn
CAPNn
MATn
TOGn
PWMn
0
0
0
0
ECCFn
CCAPMn, n= 0 to 4
(DAH – DEH)
SU00749
Figure 9. PCA Capture Mode
CF
WRITE TO
CCAPnH
––
CCF4
CCF3
CCF2
CCF1
CCF0
CCON
(D8H)
RESET
CCAPnH
WRITE TO
CCAPnL
0
CR
PCA INTERRUPT
CCAPnL
(TO CCFn)
1
ENABLE
MATCH
16–BIT COMPARATOR
CH
CL
PCA TIMER/COUNTER
––
ECOMn
CAPPn
CAPNn
0
0
MATn
TOGn
PWMn
0
0
ECCFn
CCAPMn, n= 0 to 4
(DAH – DEH)
SU00750
Figure 10. PCA Compare Mode
1998 May 01
14
Philips Semiconductors
Product specification
80C51 8-bit microcontroller family
80C575/83C575/
87C575
8K/256 OTP/ROM/ROMless, 4 comparator, failure detect circuitry, watchdog timer
CF
WRITE TO
CCAPnH
––
CCF4
CCF3
CCF2
CCF1
CCF0
CCON
(D8H)
RESET
CCAPnH
WRITE TO
CCAPnL
0
CR
PCA INTERRUPT
CCAPnL
(TO CCFn)
1
MATCH
ENABLE
16–BIT COMPARATOR
TOGGLE
CH
CEXn
CL
PCA TIMER/COUNTER
––
ECOMn
CAPPn
CAPNn
0
0
MATn
TOGn
1
PWMn
ECCFn
CCAPMn, n: 0..4
(DAH – DEH)
0
SU00751
Figure 11. PCA High Speed Output Mode
Pulse Width Modulator Mode
All of the PCA modules can be used as PWM
outputs. Figure 12 shows the PWM function.
The frequency of the output depends on the
source for the PCA timer. All of the modules
will have the same frequency of output
because they all share the PCA timer. The
duty cycle of each module is independently
variable using the module’s capture register
CCAPLn. When the value of the PCA CL
SFR is less than the value in the module’s
CCAPLn SFR the output will be low, when it
is equal to or greater than the output will be
high. When CL overflows from FF to 00,
CCAPLn is reloaded with the value in
CCAPHn. the allows updating the PWM
without glitches. The PWM and ECOM bits in
the module’s CCAPMn register must be set
to enable the PWM mode.
WATCHDOG TIMER
The watchdog timer is not directly loadable
by the user. Instead, the value to be loaded
into the main timer is held in an autoload
register or is part of the mask ROM
programming. In order to cause the main
timer to be loaded with the appropriate value,
a special sequence of software action must
take place. This operation is referred to as
feeding the watchdog timer.
To feed the watchdog, two instructions must
be sequentially executed successfully. No
1998 May 01
intervening instruction fetches are allowed,
so interrupts should be disabled before
feeding the watchdog. The instructions
should move A5H to the WFEED1 register
and then 5AH to the WFEED2 register. If
WFEED1 is correctly loaded and WFEED2 is
not correctly loaded, then an immediate
underflow will occur.
The watchdog timer subsystem has two
modes of operation. Its principal function is a
watchdog timer. In this mode it protects the
system from incorrect code execution by
causing a system reset when the watchdog
timer underflows as a result of a failure of
software to feed the timer prior to the timer
reaching its terminal count. If the user does
not employ the watchdog function, the
watchdog subsystem can be used as a timer.
In this mode, reaching the terminal count sets
a flag. In most other respects, the timer mode
possesses the characteristics of the
watchdog mode. This is done to protect the
integrity of the watchdog function.
The watchdog timer subsystem consists of a
prescaler and a main counter. The prescaler
has 8 selectable taps off the final stages and
the output of a selected tap provides the
clock to the main counter. The main counter
is the section that is loaded as a result of the
software feeding the watchdog and it is the
section that causes the system reset
15
(watchdog mode) or time-out flag to be set
(timer mode) if allowed to reach its terminal
count.
Programming the Watchdog Timer
Both the EPROM and ROM devices have a
set of SFRs for holding the watchdog
autoload values and the control bits. The
watchdog time-out flag is present in the
watchdog control register and operates the
same in all versions. In the EPROM device,
the watchdog parameters (autoload value
and control) are always taken from the SFRs.
In the ROM device, the watchdog parameters
can be mask programmed or taken from the
SFRs. The selection to take the watchdog
parameters from the SFRs or from the mask
programmed values is controlled by EA
(external access). When EA is high (internal
ROM access), the watchdog parameters are
taken from the mask programmed values. If
the watchdog is mask programmed to the
timer mode, then the autoload values and the
pre-scaler taps are taken from the SFRs.
When EA is low (external access), the
watchdog parameters are taken from the
SFRs. The user should be able to leave code
in his program which initializes the watchdog
SFRs even though he has migrated to the
mask ROM part. This allows no code
changes from EPROM prototyping to ROM
coded production parts.
Philips Semiconductors
Product specification
80C51 8-bit microcontroller family
80C575/83C575/
87C575
8K/256 OTP/ROM/ROMless, 4 comparator, failure detect circuitry, watchdog timer
CCAPnH
CCAPnL
0
CL < CCAPnL
ENABLE
8–BIT
COMPARATOR
CEXn
CL >= CCAPnL
1
CL
OVERFLOW
PCA TIMER/COUNTER
––
ECOMn
CAPPn
CAPNn
MATn
TOGn
0
0
0
0
PWMn
ECCFn
CCAPMn, n: 0..4
(DAH – DEH)
0
SU00752
Figure 12. PCA PWM Mode
Watchdog Detailed Operation
EPROM Device (and ROMless Operation:
EA = 0)
In the ROMless operation (ROM part, EA = 0)
and in the EPROM device, the watchdog
operates in the following manner (see
Figure 14).
Whether the watchdog is in the watchdog or
timer mode, when external RESET is applied,
the following takes place:
• Watchdog mode bit set to watchdog mode.
• Watchdog run control bit set to ON.
• Autoload register set to 00 (min. count).
• Watchdog time-out flag cleared.
• Prescaler is cleared.
• Prescaler tap set to the highest divide.
• Autoload takes place.
The watchdog can be fed even though it is in
the timer mode.
Note that the operational concept is for the
watchdog mode of operation, when coming
out of a hardware reset, the software should
load the autoload registers, set the mode to
watchdog, and then feed the watchdog
(cause an autoload). The watchdog will now
be starting at a known point.
If the watchdog is in the watchdog mode and
running and happens to underflow at the time
the external RESET is applied, the watchdog
time-out flag will be cleared.
1998 May 01
When the watchdog is in the watchdog mode
and the watchdog underflows, the following
action takes place (see Figure 16):
• Autoload takes place.
• Watchdog time-out flag is set
• Mode bit unchanged.
• Watchdog run bit unchanged.
• Autoload register unchanged.
• Prescaler tap unchanged.
• All other device action same as external
reset.
Note that if the watchdog underflows, the
program counter will start from 00H as in the
case of an external reset. The watchdog
time-out flag can be examined to determine if
the watchdog has caused the reset condition.
The watchdog time-out flag bit can be cleared
by software.
When the watchdog is in the timer mode and
the timer software underflows, the following
action takes place:
• Autoload takes place.
• Watchdog time-out flag is set
• Mode bit unchanged.
• Watchdog run bit unchanged.
• Autoload register unchanged.
• Prescaler tap unchanged.
16
Mask ROM Device (EA = 1)
In the mask ROM device, the watchdog
mode bit (WDMOD) is mask programmed
and the bit in the watchdog command register
is read only and reflects the mask
programmed selection. If the mask
programmed mode bit selects the timer
mode, then the watchdog run bit (WDRUN)
operates as described under EPROM
Device. If the mask programmed bit selects
the watchdog mode, then the watchdog run
bit has no effect on the timer operation (see
Figure 15).
Watchdog Function
The watchdog consists of a programmable
prescaler and the main timer. The prescaler
derives its clock from the on-chip oscillator.
The prescaler consists of a divide by 12
followed by a 13 stage counter with taps from
stage 6 through stage 13. This is shown in
Figure 17. The tap selection is
programmable. The watchdog main counter
is a down counter clocked (decremented)
each time the programmable prescaler
underflows. The watchdog generates an
underflow signal (and is autoloaded) when
the watchdog is at count 0 and the clock to
decrement the watchdog occurs. The
watchdog is 8 bits long and the autoload
value can range from 0 to FFH. (The
autoload value of 0 is permissible since the
prescaler is cleared upon autoload).
This leads to the following user design
equations. Definitions :tOSC is the oscillator
Philips Semiconductors
Product specification
80C51 8-bit microcontroller family
8K/256 OTP/ROM/ROMless, 4 comparator, failure detect circuitry, watchdog timer
period, N is the selected prescaler tap value,
W is the main counter autoload value, tMIN is
the minimum watchdog time-out value (when
the autoload value is 0), tMAX is the maximum
time-out value (when the autoload value is
FFH), tD is the design time-out value.
tMIN = tOSC × 12 × 64
tMAX = tMIN × 128 × 256
tD = tMIN × 2PRESCALER × (W + 1)
(where prescaler = 0, 1, 2, 3, 4, 5, 6, or 7)
Note that the design procedure is anticipated
to be as follows. A tMAX will be chosen either
from equipment or operation considerations
and will most likely be the next convenient
value higher than tD. (If the watchdog were
inadvertently to start from FFH, an overflow
would be guaranteed, barring other
anomalies, to occur within tMAX). Then the
value for the prescaler would be chosen
from:
prescaler = log2 (tMAX / (tOSC × 12 × 256)) - 6
This then also fixes tMIN. An autoload value
would then be chosen from:
W = tD / tMIN - 1
The software must be written so that a feed
operation takes place every tD seconds from
the last feed operation. Some tradeoffs may
need to be made. It is not advisable to
include feed operations in minor loops or in
subroutines unless the feed operation is a
specific subroutine.
Watchdog Control Register (WDCON)
(Bit Addressable) Address C0
The following bits of this register are read
only in the ROM part when EA is high:
WDMOD, PRE0, PRE1, and PRE2. That is,
the register will reflect the mask programmed
values. In the ROM part with EA high, these
bits are taken from mask coded bits and are
not readable by the program. WDRUN is
read only in the ROM part when EA is high
and WDMOD is in the watchdog mode. When
1998 May 01
WDMOD is in the timer mode, WDRUN
functions normally.
The parameters written into WDMOD, PRE0,
PRE1, and PRE2 by the program are not
applied directly to the watchdog timer
subsystem. The watchdog timer subsystem is
directly controlled by a second register which
stores these bits. The transfer of these bits
from the user register (WDMOD) to the
second control register takes place when the
watchdog is fed. This prevents random code
execution from directly foiling the watchdog
function. This does not affect the operation
where these bits are taken from mask coded
values.
The reset values of the WDCON and WDL
registers will be such that the timer resets to
the watchdog mode with a timeout period of
12 × 64 × 128 × tOSC. The watchdog timer
will not generate an interrupt. Additional bits
in WDCON are used to disable reset
generation by the oscillator fail and low
voltage detect circuits. WDCON can be
written by software only by executing a valid
watchdog feed sequence.
WDCON Register Bit Definitions
WDCON.7 PRE2
Prescaler Select 2,
reset to 1
WDCON.6 PRE1
Prescaler Select 1,
reset to 1
WDCON.5 PRE0
Prescaler Select 0,
reset to 1
WDCON.4 LVRE
Low Voltage Reset
Enable, reset to 1
(enabled)
WDCON.3 OFRE
Oscillator Fail Reset
Enable, reset to 1
(enabled)
WDCON.2 WDRUN Watchdog Run,
reset to 1 (enabled)
WDCON.1 WDTOF
Watchdog Timeout
Flag, reset =
Indeterminate
WDCON.0 WDMOD Watchdog Mode,
reset to 1 (watchdog
mode)
17
80C575/83C575/
87C575
Enhanced UART
The UART operates in all of the usual modes
that are described in the first section of this
book for the 80C51. In addition the UART can
perform framing error detect by looking for
missing stop bits, and automatic address
recognition. The 87C575 UART also fully
supports multiprocessor communication as
does the standard 80C51 UART.
When used for framing error detect the UART
looks for missing stop bits in the
communication. A missing bit will set the FE
bit in the SCON register. The FE bit shares
the SCON.7 bit with SM0 and the function of
SCON.7 is determined by PCON.6 (SMOD0)
(see Figure 19). If SMOD0 is set then
SCON.7 functions as FE. SCON.7 functions
as SM0 when SMOD0 is cleared. When used
as FE SCON.7 can only be cleared by
software. Refer to Figure 18.
Automatic Address Recognition
Automatic Address Recognition is a feature
which allows the UART to recognize certain
addresses in the serial bit stream by using
hardware to make the comparisons. This
feature saves a great deal of software
overhead by eliminating the need for the
software to examine every serial address
which passes by the serial port. This feature
is enabled by setting the SM2 bit in SCON. In
the 9 bit UART modes, mode 2 and mode 3,
the Receive Interrupt flag (RI) will be
automatically set when the received byte
contains either the “Given” address or the
“Broadcast” address. The 9 bit mode requires
that the 9th information bit is a 1 to indicate
that the received information is an address
and not data. Automatic address recognition
is shown in Figure 20.
The 8 bit mode is called Mode 1. In this mode
the RI flag will be set if SM2 is enabled and
the information received has a valid stop bit
following the 8 address bits and the
information is either a Given or Broadcast
address.
Mode 0 is the Shift Register mode and SM2
is ignored.
Philips Semiconductors
Product specification
80C51 8-bit microcontroller family
80C575/83C575/
87C575
8K/256 OTP/ROM/ROMless, 4 comparator, failure detect circuitry, watchdog timer
CIDL
WRITE TO
CCAP4H
WDTE
––
––
CPS1
CPS0
ECF
CMOD
(D9H)
RESET
CCAP4H
WRITE TO
CCAP4L
0
––
CCAP4L
1
ENABLE
MATCH
RESET
16–BIT COMPARATOR
CH
CL
PCA TIMER/COUNTER
––
ECOMn
CAPPn
CAPNn
MATn
0
0
1
TOGn
PWMn
ECCFn
0
X
X
CCAPM4
(DEH)
SU00042
Figure 13. PCA Watchdog Timer
WDL
(C1H)
WATCHDOG FEED SEQUENCE
MOV WFEED1,#0A5H
MOV WFEED2,#5AH
OSC/12
8–BIT DOWN
COUNTER
PRESCALER
RESET
SHADOW REGISTER
FOR WDCON
PRE2
PRE1
PRE0
LVRE
OFRE
WDRUN
WDTOF
WDMOD
WDCON
(C0H)
SU00240
Figure 14. Watchdog Timer in 87C575 and 80C575 / 83C575 (EA = 0)
1998 May 01
18
Philips Semiconductors
Product specification
80C51 8-bit microcontroller family
80C575/83C575/
87C575
8K/256 OTP/ROM/ROMless, 4 comparator, failure detect circuitry, watchdog timer
ROM–CODE
CONTENT
WD
PRE2:0
WDMOD
WATCHDOG FEED SEQUENCE
ADDRESS
2032H
2031H
2030H
MOV WFEED1,#0A5H
MOV WFEED2,#5AH
OSC/12
8–BIT DOWN
COUNTER
PRESCALER
SHADOW REGISTER
FOR WDCON
1
PRE2
PRE1
PRE0
LVRE
OFRE
WDRUN
WDTOF
WDMOD
WDCON
(C0H)
SU00241
Figure 15. Watchdog Timer of 83C575 in Watchdog Mode (EA = 1, WDMOD = 1)
ROM–CODE
CONTENT
WD
PRE2:0
WDMOD
WATCHDOG FEED SEQUENCE
ADDRESS
2032H
2031H
2030H
MOV WFEED1,#0A5H
MOV WFEED2,#5AH
OSC/12
8–BIT DOWN
COUNTER
PRESCALER
SHADOW REGISTER
FOR WDCON
0
PRE2
PRE1
PRE0
LVRE
OFRE
WDRUN
WDTOF
WDMOD
WDCON
(C0H)
SU00242
Figure 16. Watchdog Timer of 83C575 in Timer Mode (EA = 1, WDMOD = 0)
1998 May 01
19
Philips Semiconductors
Product specification
80C51 8-bit microcontroller family
80C575/83C575/
87C575
8K/256 OTP/ROM/ROMless, 4 comparator, failure detect circuitry, watchdog timer
÷64
OSC/12
÷2
÷64
÷128
÷2
÷256
÷2
÷2
÷512
÷1024
÷2
÷2048
÷2
÷4096
÷2
÷8192
TO WATCHDOG
DOWN COUNTER
000
001
010
011
DECODE 100
101
110
111
PRE2
PRE1
PRE0
SU00243
Figure 17. Watchdog Prescaler
SCON Address = 98H
Reset Value = 0000 0000B
Bit Addressable
SM0/FE
Bit:
SM1
7
6
(SMOD0 = 0/1)*
SM2
REN
TB8
RB8
Tl
Rl
5
4
3
2
1
0
Symbol
Function
FE
Framing Error bit. This bit is set by the receiver when an invalid stop bit is detected. The FE bit is not cleared by valid
frames but should be cleared by software. The SMOD0 bit must be set to enable access to the FE bit.
SM0
Serial Port Mode Bit 0, (SMOD0 must = 0 to access bit SM0)
SM1
Serial Port Mode Bit 1
SM0
SM1
Mode
0
0
1
1
0
1
0
1
0
1
2
3
Description
Baud Rate**
shift register
8-bit UART
9-bit UART
9-bit UART
fOSC/12
variable
fOSC/64 or fOSC/32
variable
SM2
Enables the Automatic Address Recognition feature in Modes 2 or 3. If SM2 = 1 then Rl will not be set unless the
received 9th data bit (RB8) is 1, indicating an address, and the received byte is a Given or Broadcast Address.
In Mode 1, if SM2 = 1 then Rl will not be activated unless a valid stop bit was received, and the received byte is a
Given or Broadcast Address. In Mode 0, SM2 should be 0.
REN
Enables serial reception. Set by software to enable reception. Clear by software to disable reception.
TB8
The 9th data bit that will be transmitted in Modes 2 and 3. Set or clear by software as desired.
RB8
In modes 2 and 3, the 9th data bit that was received. In Mode 1, if SM2 = 0, RB8 is the stop bit that was received.
In Mode 0, RB8 is not used.
Tl
Transmit interrupt flag. Set by hardware at the end of the 8th bit time in Mode 0, or at the beginning of the stop bit in the
other modes, in any serial transmission. Must be cleared by software.
Rl
Receive interrupt flag. Set by hardware at the end of the 8th bit time in Mode 0, or halfway through the stop bit time in
the other modes, in any serial reception (except see SM2). Must be cleared by software.
NOTE:
*SMOD0 is located at PCON6.
**fOSC = oscillator frequency
SU00043
Figure 18. SCON: Serial Port Control Register
1998 May 01
20
Philips Semiconductors
Product specification
80C51 8-bit microcontroller family
80C575/83C575/
87C575
8K/256 OTP/ROM/ROMless, 4 comparator, failure detect circuitry, watchdog timer
D0
D1
D2
D3
D4
D5
D6
D7
D8
DATA BYTE
START
BIT
ONLY IN
MODE 2, 3
STOP
BIT
SET FE BIT IF STOP BIT IS 0 (FRAMING ERROR)
SM0 TO UART MODE CONTROL
SM0 / FE
SM1
SM2
REN
TB8
RB8
TI
RI
SCON
(98H)
SMOD1
SMOD0
–
POF
LVF
GF0
GF1
IDL
PCON
(87H)
0 : SCON.7 = SM0
1 : SCON.7 = FE
SU00044
Figure 19. UART Framing Error Detection
Using the Automatic Address Recognition
feature allows a master to selectively
communicate with one or more slaves by
invoking the Given slave address or
addresses. All of the slaves may be
contacted by using the Broadcast address.
Two special Function Registers are used to
define the slave’s address, SADDR, and the
address mask, SADEN. SADEN is used to
define which bits in the SADDR are to b used
and which bits are “don’t care”. The SADEN
mask can be logically ANDed with the
SADDR to create the “Given” address which
the master will use for addressing each of the
slaves. Use of the Given address allows
multiple slaves to be recognized while
excluding others. The following examples will
help to show the versatility of this scheme:
Slave 0
SADDR
SADEN
Given
=
=
=
1100 0000
1111 1101
1100 00X0
Slave 1
SADDR
SADEN
Given
=
=
=
1100 0000
1111 1110
1100 000X
In the above example SADDR is the same
and the SADEN data is used to differentiate
between the two slaves. Slave 0 requires a 0
in bit 0 and it ignores bit 1. Slave 1 requires a
0 in bit 1 and bit 0 is ignored. A unique
address for Slave 0 would be 1100 0010
since slave 1 requires a 0 in bit 1. A unique
address for slave 1 would be 1100 0001
since a 1 in bit 0 will exclude slave 0. Both
1998 May 01
slaves can be selected at the same time by
an address which has bit 0 = 0 (for slave 0)
and bit 1 = 0 (for slave 1). Thus, both could
be addressed with 1100 0000.
In a more complex system the following could
be used to select slaves 1 and 2 while
excluding slave 0:
Slave 0
SADDR
SADEN
Given
=
=
=
1100 0000
1111 1001
1100 0XX0
Slave 1
SADDR
SADEN
Given
=
=
=
1110 0000
1111 1010
1110 0X0X
SADDR
SADEN
Given
=
=
=
1110 0000
1111 1100
1110 00XX
Slave 2
In the above example the differentiation
among the 3 slaves is in the lower 3 address
bits. Slave 0 requires that bit 0 = 0 and it can
be uniquely addressed by 1110 0110. Slave 1
requires that bit 1 = 0 and it can be uniquely
addressed by 1110 and 0101. Slave 2
requires that bit 2 = 0 and its unique address
is 1110 0011. To select Slaves 0 and 1 and
exclude Slave 2 use address 1110 0100,
since it is necessary t make bit 2 = 1 to
exclude slave 2.
The Broadcast Address for each slave is
created by taking the logical OR of SADDR
and SADEN. Zeros in this result are treated
21
as don’t-cares. In most cases, interpreting
the don’t-cares as ones, the broadcast
address will be FF hexadecimal.
Upon reset SADDR (SFR address 0A9H) and
SADEN (SFR address 0B9H) are loaded with
0s. This produces a given address of all
“don’t cares” as well as a Broadcast address
of all “don’t cares”. this effectively disables
the Automatic Addressing mode and allows
the microcontroller to use standard 80C51
type UART drivers which do not make use of
this feature.
Analog Comparators
Four analog comparators are provided on
chip. Three comparators have a common
negative reference CMPR- and independent
positive inputs CMP1+, CMP2+, CMP3+ on
port 3. The fourth comparator has
independent positive and negative inputs
CMP0+ and CMP0- on port 1. The CMP
register contains an output and enable bit for
each comparator. The CMP register is bit
addressable and is located at SFR address
E8H. Figure 21 shows the connection of the
comparators.
Pullups at the comparator input pins will be
disabled by hardware when the comparator is
enabled. In addition, to make inputs high
impedance, the corresponding port SFR bits
must be set by software to disable the
pulldowns.
Philips Semiconductors
Product specification
80C51 8-bit microcontroller family
80C575/83C575/
87C575
8K/256 OTP/ROM/ROMless, 4 comparator, failure detect circuitry, watchdog timer
D0
D1
D2
D3
D4
SM0
SM1
1
1
1
0
D5
SM2
1
D6
D7
D8
REN
TB8
RB8
1
X
TI
RI
SCON
(98H)
RECEIVED ADDRESS D0 TO D7
COMPARATOR
PROGRAMMED ADDRESS
IN UART MODE 2 OR MODE 3 AND SM2 = 1:
INTERRUPT IF REN=1, RB8=1 AND “RECEIVED ADDRESS” = “PROGRAMMED ADDRESS”
– WHEN OWN ADDRESS RECEIVED, CLEAR SM2 TO RECEIVE DATA BYTES
– WHEN ALL DATA BYTES HAVE BEEN RECEIVED: SET SM2 TO WAIT FOR NEXT ADDRESS.
SU00045
Figure 20. UART Multiprocessor Communication, Automatic Address Recognition
CMP Register Bit Definitions
CMP.7 enable comparator 3,
disable pullups at P3.4, P3.7
CMP.6 enable comparator 2,
disable pullups at P3.4, P3.6
CMP.5 enable comparator 1,
disable pullups at P3.4, P3.5
CMP.4 enable comparator 0,
disable pullups at P1.0, P1.1
CMP.3 comparator 3 output (read only)
CMP.2 comparator 2 output (read only)
CMP.1 comparator 1 output (read only)
CMP.0 comparator 0 output (read only)
All comparators are disabled automatically in
power down mode, in idle mode unused
comparators should be disabled by software
to save power. A comparator can generate
an interrupt that will terminate idle mode.
The CMPE register contains bits to enable
each comparator to drive external output pins
or internal PCA capture inputs. Pullups at the
output pins are disabled by hardware when
the external comparator output is enabled.
The comparator output is wire-ORed with the
corresponding port SFR bit, so the SFR bit
must also be set by software to enable the
output.
1998 May 01
CMPE Register Bit Definitions
CMPE.7 enables comparator 3 to drive
CEX3
CMPE.6 enables comparator 2 to drive
CEX2
CMPE.5 enables comparator 1 to drive
CEX1
CMPE.4 enables comparator 0 to drive
CEX0
CMPE.3 enables comparator 3 output on
P1.6 (open drain)
CMPE.2 enables comparator 2 output on
P1.5 (open drain)
CMPE.1 enables comparator 1 output on
P1.4 (open drain)
CMPE.0 enables comparator 0 output on
P1.3 (open drain)
When 1s are written to CMPE bits 7-4,
the comparator outputs will drive the
corresponding capture input. (This function is
not available in the idle or power-down
mode.) When 1s are written to CMPE bits 3-0
the comparator output will also drive the
corresponding port 1 pin. (This function is
available in idle mode.) If the comparator’s
enabled to drive the capture input but not the
port pin, then the port pin can be used for
general purpose I/O. When a comparator
output is enabled, pullups at the output pin
are disabled and the output becomes open
drain. The comparator output can be used to
trigger a capture input in idle mode by
programming the CMPE register to drive the
22
pin from the comparator output to have the
pin supply the capture trigger.
There are two special function registers
associated with the comparators. They are
CMP which contains the comparator enables
and a bit that can be read by software to
determine the state of each comparator’s
output, and CMPE which controls whether
the output from each comparator drives the
associated output pin or a capture input
associated with one of the PCA modules.
The CMP registers bits 0–3 can be read by
software to determine the state of the output
of each comparator. To do this the associated
comparator must be enabled but the output in
port 1 can be disabled. This allows easy
polling of the comparator output value without
the need to use up a port pin.
The CMPE register allows the comparator to
drive the associated PCA module capture
input, so that on compare a capture can be
generated in the PCA. Bits 0–3 of this
register enable the comparator output to drive
the associated port 1 output circuitry. Used
as a comparator output this circuitry is open
drain. To enable the comparator output to
drive to port 1, the corresponding port bit
must also be set to disable the pulldown. If
the comparator is not enabled to drive the
port 1 circuitry, the associated port 1 pin can
be used for other I/O. This includes when a
comparator is enabled to drive the capture
input to a PCA module.
Philips Semiconductors
Product specification
80C51 8-bit microcontroller family
80C575/83C575/
87C575
8K/256 OTP/ROM/ROMless, 4 comparator, failure detect circuitry, watchdog timer
EC3TDC
P1.0 / CMP0+
+
P1.1 / CMP0–
–
EC2TDC
EC1TDC
EC0TDC
EC3OD *
EC2OD *
EC1OD *
EC0OD *
CMPE
(91H)
P1.3 / CMP0
TO CEX0 INPUT OF
PCA MODULE 0
ENABLE
P3.5 / CMP1+
+
P1.4 / CMP1
–
TO CEX1 INPUT OF
PCA MODULE 1
ENABLE
P3.6 / CMP2+
+
P1.5 / CMP2
–
TO CEX2 INPUT OF
PCA MODULE 2
ENABLE
P3.7 / CMP3+
+
P3.4 / CMPR–
–
P1.6 / CMP3
TO CEX3 INPUT OF
PCA MODULE 3
ENABLE
* : WILL DISABLE PULLUPS
ON RELEVANT PINS
EC3DP *
EC2DP *
EC1DP *
EC0DP *
C3R0
C2R0
C1R0
C0R0
CMP
(E8H)
SU00244
Figure 21. Analog Comparators
Reduced EMI Mode
INTERNAL RESET
There are two bits in the AUXR register that
can be set to reduce the internal clock drive
and disable the ALE output. AO (AUXR.0)
when set turns off the ALE output. LO
(AUXR.1) when set reduces the drive of the
internal clock circuitry. Both bits are cleared
on Reset. With LO set the 87C575 will still
operate at 12MHz, but will have reduced EMI
in the range above 100MHz.
Internal resets generated by the power on,
low voltage, and oscillator fail detect circuits
are self timed to guarantee proper
initialization of the 8XC575. Reset will be held
approximately 24 oscillator periods after
normal conditions are detected by all enabled
detect circuits. Internal resets do not drive
RST but will cause missing pulses on ALE.
AUXR (8EH)
––
––
––
––
––
––
LO
AO
AO:
Turns off ALE output.
LO:
Reduces drive of internal clock
circuitry. 8XC575 spec’d to 12MHz
when LO set.
Interrupt Enable (IE) Register
EA
IE.7 enable all interrupts
EC
IE.6 enable PCA interrupt
ET2 IE.5 enable Timer 2 interrupt
ES
IE.4 enable Serial I/O interrupt
ET1 IE.3 enable Timer 1 interrupt
EX1 IE.2 enable External interrupt 1
ET0 IE.1 enable Timer 0 interrupt
EX0 IE.0 enable External interrupt 0
Interrupt Priority (IP) Register
IP.7 reserved
PPC IP.6 PCA interrupt priority
PT2 IP.5 Timer 2 interrupt priority
PS
IP.4 Serial I/O interrupt priority
PT1 IP.3 Timer 1 interrupt priority
PX1 IP.2 External interrupt 1 priority
PT0 IP.1 Timer 0 interrupt priority
PX0 IP.0 External interrupt 0 priority
Priority
1
2
3
4
Source
INT0
Timer 0
INT1
Timer 1
Flag
IE0
TF0
IE1
TF1
Vector
03H highest priority
0BH
13H
1BH
87C575
5
PCA
CF,CCFn 33H
6
Serial I/O RI,TI
23H
Timer 2 TF2/EXF2 2BH lowest priority
7
80C575/83C575/87C575
5
Serial I/O RI/TI
23H
Timer 2 TF2/EXF2 23H
6
7
PCA
CF, CCFn 33H lowest priority
Power Control (PCON) Register
SMOD1 PCON.7 double baud rate bit
SMOD0 PCON.6 SCON.7 access control
OSF
PCON.5 oscillator fail flag
POF
PCON.4 power off flag
LVF
PCON.3 low voltage flag
GF0
PCON.2 general purpose flag
PD
PCON.1 power down mode bit
IDL
PCON.0 idle mode bit
Port 2 Pullup Disable Register
1998 May 01
23
Philips Semiconductors
Product specification
80C51 8-bit microcontroller family
80C575/83C575/
87C575
8K/256 OTP/ROM/ROMless, 4 comparator, failure detect circuitry, watchdog timer
OSCILLATOR
CHARACTERISTICS
XTAL1 and XTAL2 are the input and output,
respectively, of an inverting amplifier. The
pins can be configured for use as an on-chip
oscillator, as shown in the Logic Symbol,
page 4.
To drive the device from an external clock
source, XTAL1 should be driven while XTAL2
is left unconnected. There are no
requirements on the duty cycle of the
external clock signal, because the input to
the internal clock circuitry is through a
divide-by-two flip-flop. However, minimum
and maximum high and low times specified in
the data sheet must be observed.
IDLE MODE
POWER-DOWN MODE
In idle mode, the CPU puts itself to sleep
while all of the on-chip peripherals stay
active. The instruction to invoke the idle
mode is the last instruction executed in the
normal operating mode before the idle mode
is activated. The CPU contents, the on-chip
RAM, and all of the special function registers
remain intact during this mode. The idle
mode can be terminated either by any
enabled interrupt (at which time the process
is picked up at the interrupt service routine
and continued), or by a hardware reset which
starts the processor in the same manner as a
power-on reset.
In the power-down mode, the oscillator is
stopped and the instruction to invoke
power-down is the last instruction executed.
Only the contents of the on-chip RAM are
preserved. The control bits for the reduced
power modes are in the special function
register PCON. Power-down mode can be
terminated with either a hardware reset or
external interrupt. With an external interrupt
INT0 or INT1 must be enabled and
configured as level sensitive. Holding the pin
low restarts to oscillator and bringing the pin
back high completes the exit.
If the watchdog is enabled (WDRUN = 1),
then power-down mode is disabled.
DESIGN CONSIDERATIONS
At power-on, the voltage on VCC must come
up with RST low for a proper start-up.
Table 2 shows the state of I/O ports during
low current operating modes.
Table 2. External Pin Status During Idle and Power-Down Modes
PROGRAM MEMORY
ALE
PSEN
PORT 0
PORT 1
PORT 2
PORT 3
Idle
MODE
Internal
1
1
Data
Data
Data
Data
Idle
External
1
1
Float
Data
Address
Data
Power-down
Internal
0
0
Data
Data
Data
Data
Power-down
External
0
0
Float
Data
Data
Data
1998 May 01
24
Philips Semiconductors
Product specification
80C51 8-bit microcontroller family
80C575/83C575/
87C575
8K/256 OTP/ROM/ROMless, 4 comparator, failure detect circuitry, watchdog timer
ROM CODE SUBMISSION
When submitting ROM code for the 83C575, the following must be specified:
1. 8k byte user ROM data
2. 32 byte ROM encryption key
3. ROM security bits
4. The watchdog timer parameters.
ADDRESS
CONTENT
BIT(S)
COMMENT
0000H to 1FFFH
DATA
7:0
User ROM Data
2000H to 201FH
KEY
7:0
ROM Encryption Key
FFH = no encryption
2020H
Reserved
Security Bit 2
Security Bit 1
2
1
0
Must = 1
0 = enable, 1 = disable
0 = enable, 1 = disable
2030H
Reserved
7:0
Must = FFH
2031H
Reserved
7:0
Must = FFH
7:0
Watchdog reload value
(see specification)
PRE2:0
1
2032H
WDL
2033H
WDCON 1
7:5
2033H
WDCON 1
4
LVRE
2033H
WDCON
1
3
OFRE
2033H
WDCON 1
2
WDRUN=0, not ROM coded
2033H
WDCON
1
1
WDTOF=0, not ROM coded
2033H
WDCON 1
0
WDMOD
NOTES:
1. See Watchdog Timer Specification for definition of WDL and WDCON bits.
Security Bit 1: When programmed, this bit has two effects on masked ROM parts:
1. External MOVC is disabled, and
2. EA# is latched on Reset.
Security Bit 2: When programmed, this bit inhibits Verify User ROM.
ABSOLUTE MAXIMUM RATINGS1, 2, 3
RATING
UNIT
Operating temperature under bias
–55 to +125
°C
Storage temperature range
–65 to +150
°C
0 to +13.0
V
–0.5 to +6.5
V
Maximum IOL per I/O pin
15
mA
Power dissipation (based on package heat transfer limitations, not
device power consumption)
1.5
W
PARAMETER
Voltage on EA/VPP pin to VSS
Voltage on any other pin to VSS
NOTES:
1. Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or any conditions other than those described in the AC and DC Electrical Characteristics section
of this specification is not implied.
2. This product includes circuitry specifically designed for the protection of its internal devices from the damaging effects of excessive static
charge. Nonetheless, it is suggested that conventional precautions be taken to avoid applying greater than the rated maxima.
3. Parameters are valid over operating temperature range unless otherwise specified. All voltages are with respect to VSS unless otherwise
noted.
1998 May 01
25
Philips Semiconductors
Product specification
80C51 8-bit microcontroller family
80C575/83C575/
87C575
8K/256 OTP/ROM/ROMless, 4 comparator, failure detect circuitry, watchdog timer
DC ELECTRICAL CHARACTERISTICS
Tamb = 0°C to +70°C and –40°C to +125°C, VCC = 5V ±10%, VSS = 0V
SYMBOL
TEST
CONDITIONS
PARAMETER
LIMITS
MIN
TYP1
UNIT
MAX
VIL
Input low voltage (Ports 0, 2, 3, except 3.2, 3.3)
–0.5
0.5VCC–0.6
V
VIL1
Input low voltage (Ports 1, 3.2, 3.3, XTAL1, RST)
–0.5
0.2VCC–0.5
V
VIL2
Input low voltage (EA)
0
0.2VCC–0.45
V
VIH
Input high voltage (Ports 0, 2, 3, except 3.2, 3.3)
0.5VCC+0.8
VCC+0.5
V
VIH1
Input high voltage (Ports 1, 3.2, 3.3)
0.8VCC+0.3
VCC+0.5
V
VIH2
Input high voltage (EA)
0.2VCC+0.9
VCC+0.5
V
VIH3
Input high voltage (XTAL1, RST)
0.7VCC
VCC+0.5
V
HYS
Hysteresis (Ports 0, 2, 3, except 3.2, 3.3)
200
mV
HYS1
Hysteresis (Ports 1, 3.2, 3.3)
50
mV
VOL
Output voltage low (Ports 1, 2, 3, except 3.1)
PSEN)
IOL = 1.6mA
0.45
V
IOL = 3.2mA
0.45
V
0.50
0.45
V
V
VOL1
Output voltage low (Ports 0, ALE,
VOL2
Output voltage low
P3.1 with bit cleared
P3.1 with bit set
IOL = 10.0mA
IOL = 1.6mA
VOH
Output voltage high (Ports 1, 2, 3, except P3.1)
IOH = –30µA
VCC–0.7
V
VOH1
Output voltage high (Port 0 in external bus mode, ALE, PSEN)
IOH = –3.2mA
VCC–0.7
V
VOH2
Output voltage high
P3.1 with bit cleared
P3.1 with bit set
IOH = –10.0mA
IOH = –1.6mA
VCC–1.5
VCC–1.5
V
V
VIO
Offset voltage comparator inputs
VCR
Common mode range comparator inputs
IIL
Logical 0 input current (Ports 1, 2, 3, except 3.1)
ITL
Logical 1-to-0 transition current
(Ports 2, 3, except 3.1, 3.2, 3.3) 4
ITL1
Logical 1-to-0 transition current (Ports 1, 3.2, 3.3)
IL1
Input leakage current (Port 0, Port2 in open drain
IL2
Input leakage current (EA, P3.1)
ILC
Input leakage current comparator inputs
ICC
Power supply current:7
Active mode @ 16MHz5
Idle mode @ 16MHz
Power-down mode
RRST
Internal reset pull-up resistor
VLOW
Low VCC detect voltage
CIO
Pin
mode)9
+35
mV
0
VCC
V
VIN = 0.45V
–75
µA
See Note 4
–600
µA
See Note 4
–450
µA
40
µA
0.45 < VIN < VCC
2
0.45 < VIN < VCC
–10
+10
µA
0 < VIN < VCC
–1.0
+1.0
µA
30
12
75
mA
mA
µA
50
200
kΩ
4.0
4.45
V
10
pF
See note 6
20
8
5
VIN = 0V
capacitance10
f = 1MHz
NOTES: (SEE NEXT PAGE)
1998 May 01
–35
26
Philips Semiconductors
Product specification
80C51 8-bit microcontroller family
8K/256 OTP/ROM/ROMless, 4 comparator, failure detect circuitry, watchdog timer
80C575/83C575/
87C575
NOTES TO THE DC ELECTRICAL CHARACTERISTICS TABLE:
1. Typical ratings are not guaranteed. The values listed are at room temperature, 5V.
2. Capacitive loading on ports 0 and 2 may cause spurious noise to be superimposed on the VOLs of ALE and ports 1 and 3. The noise is due
to external bus capacitance discharging into the port 0 and port 2 pins when these pins make 1-to-0 transitions during bus operations. In the
worst cases (capacitive loading > 100pF), the noise pulse on the ALE pin may exceed 0.8V. In such cases, it may be desirable to qualify
ALE with a Schmitt Trigger, or use an address latch with a Schmitt Trigger STROBE input. IOL can exceed these conditions provided that no
single output sinks more than 5mA and no more than two outputs exceed the test conditions.
3. Capacitive loading on ports 0 and 2 may cause the VOH on ALE and PSEN to momentarily fall below the 0.9VCC specification when the
address bits are stabilizing.
4. Pins of ports 1, 2 and 3 source a transition current when they are being externally driven from 1 to 0. The transition current reaches its
maximum value when VIN is between VIH and VIL.
5. ICCMAX at other frequencies can be determined from Figure 29.
6. See Figures 30 through 33 for ICC test conditions.
7. Load capacitance for port 0, ALE, and PSEN = 100pF, load capacitance for all other outputs = 80pF.
8. Under steady state (non-transient) conditions, IOL must be externally limited as follows:
10mA
Maximum IOL per port pin:
Maximum IOL per 8-bit port:
26mA
71mA
Maximum total IOL for all outputs:
If IOL exceeds the test condition, VOL may exceed the related specification. Pins are not guaranteed to sink current greater than the listed
test conditions.
9. Specification applies to Port 2 when P2OD bit is set.
10. 15pF MAX for the EA/VPP and P0.0 pins.
1998 May 01
27
Philips Semiconductors
Product specification
80C51 8-bit microcontroller family
80C575/83C575/
87C575
8K/256 OTP/ROM/ROMless, 4 comparator, failure detect circuitry, watchdog timer
AC ELECTRICAL CHARACTERISTICS
Tamb = 0°C to +70°C and –40°C to +125°C, VCC = 5V ±10%, VSS = 0V1, 2
VARIABLE CLOCK
SYMBOL
FIGURE
1/tCLCL
22
PARAMETER
MIN
Oscillator frequency: Speed Versions
8XC575
E
OSCF
Oscillator fail detect frequency
TR
Comparator response time
MAX
UNIT
6
16
MHz
0.6
5.5
MHz
10
µs
tLHLL
22
ALE pulse width
2tCLCL–40
ns
tAVLL
22
Address valid to ALE low
tCLCL–25
ns
tLLAX
22
Address hold after ALE low
tCLCL–25
tLLIV
22
ALE low to valid instruction in
tLLPL
22
ALE low to PSEN low
tCLCL–25
tPLPH
22
PSEN pulse width
3tCLCL–45
tPLIV
22
PSEN low to valid instruction in
tPXIX
22
Input instruction hold after PSEN
tPXIZ
22
Input instruction float after PSEN
tCLCL–25
ns
tAVIV
22
Address to valid instruction in
5tCLCL–85
ns
tPLAZ
22
PSEN low to address float
10
ns
ns
4tCLCL–75
ns
ns
ns
3tCLCL–70
0
ns
ns
Data Memory
tRLRH
23, 24
RD pulse width
6tCLCL–100
ns
tWLWH
23, 24
WR pulse width
6tCLCL–100
tRLDV
23, 24
RD low to valid data in
tRHDX
23, 24
Data hold after RD
tRHDZ
23, 24
Data float after RD
2tCLCL–28
ns
tLLDV
23, 24
ALE low to valid data in
8tCLCL–150
ns
tAVDV
23, 24
Address to valid data in
9tCLCL–165
ns
tLLWL
23, 24
ALE low to RD or WR low
3tCLCL–50
3tCLCL+50
ns
tAVWL
23, 24
Address valid to WR low or RD low
4tCLCL–75
ns
tQVWX
23, 24
Data valid to WR transition
tCLCL–30
ns
tWHQX
23, 24
Data hold after WR
tCLCL–25
ns
tRLAZ
23, 24
RD low to address float
tWHLH
23, 24
RD or WR high to ALE high
ns
5tCLCL–110
0
tCLCL–25
ns
ns
0
ns
tCLCL+25
ns
External Clock
tCHCX
26
High time
12
ns
tCLCX
26
Low time
12
ns
tCLCH
26
Rise time
20
ns
tCHCL
26
Fall time
20
ns
tXLXL
25
Serial port clock cycle time
12tCLCL
ns
tQVXH
25
Output data setup to clock rising edge
10tCLCL–133
ns
tXHQX
25
Output data hold after clock rising edge
2tCLCL–60
ns
tXHDX
25
Input data hold after clock rising edge
0
ns
Shift Register
tXHDV
25
Clock rising edge to input data valid
10tCLCL–133
ns
NOTES:
1. Parameters are valid over operating temperature range unless otherwise specified.
2. Load capacitance for port 0, ALE, and PSEN = 100pF, load capacitance for all other outputs = 80pF.
3. Interfacing the 80C32/52 to devices with float times up to 45ns is permitted. This limited bus contention will not cause damage to Port 0
drivers.
1998 May 01
28
Philips Semiconductors
Product specification
80C51 8-bit microcontroller family
80C575/83C575/
87C575
8K/256 OTP/ROM/ROMless, 4 comparator, failure detect circuitry, watchdog timer
EXPLANATION OF THE AC SYMBOLS
P – PSEN
Q – Output data
R – RD signal
t – Time
V – Valid
W – WR signal
X – No longer a valid logic level
Z – Float
Examples: tAVLL = Time for address valid to
ALE low.
tLLPL =Time for ALE low to
PSEN low.
Each timing symbol has five characters. The
first character is always ‘t’ (= time). The other
characters, depending on their positions,
indicate the name of a signal or the logical
status of that signal. The designations are:
A – Address
C – Clock
D – Input data
H – Logic level high
I – Instruction (program memory contents)
L – Logic level low, or ALE
tLHLL
ALE
tAVLL
tLLPL
tPLPH
tLLIV
tPLIV
PSEN
tLLAX
INSTR IN
A0–A7
PORT 0
tPXIZ
tPLAZ
tPXIX
A0–A7
tAVIV
PORT 2
A0–A15
A8–A15
SU00006
Figure 22. External Program Memory Read Cycle
ALE
tWHLH
PSEN
tLLDV
tLLWL
tRLRH
RD
tAVLL
tLLAX
tRLAZ
PORT 0
tRHDZ
tRLDV
tRHDX
A0–A7
FROM RI OR DPL
DATA IN
A0–A7 FROM PCL
INSTR IN
tAVWL
tAVDV
PORT 2
P2.0–P2.7 OR A8–A15 FROM DPF
A0–A15 FROM PCH
SU00025
Figure 23. External Data Memory Read Cycle
1998 May 01
29
Philips Semiconductors
Product specification
80C51 8-bit microcontroller family
80C575/83C575/
87C575
8K/256 OTP/ROM/ROMless, 4 comparator, failure detect circuitry, watchdog timer
ALE
tWHLH
PSEN
tWLWH
tLLWL
WR
tLLAX
tAVLL
tWHQX
tQVWX
tQVWH
A0–A7
FROM RI OR DPL
PORT 0
DATA OUT
A0–A7 FROM PCL
INSTR IN
tAVWL
PORT 2
P2.0–P2.7 OR A8–A15 FROM DPF
A0–A15 FROM PCH
SU00026
Figure 24. External Data Memory Write Cycle
INSTRUCTION
0
1
2
3
4
5
6
7
8
ALE
tXLXL
CLOCK
tXHQX
tQVXH
OUTPUT DATA
0
1
2
WRITE TO SBUF
3
4
5
6
7
tXHDX
tXHDV
SET TI
INPUT DATA
VALID
VALID
VALID
VALID
VALID
VALID
VALID
VALID
CLEAR RI
SET RI
SU00027
Figure 25. Shift Register Mode Timing
VCC–0.5
0.45V
0.7VCC
0.2VCC–0.1
tCHCL
tCHCX
tCLCH
tCLCX
tCLCL
SU00009
Figure 26. External Clock Drive
1998 May 01
30
Philips Semiconductors
Product specification
80C51 8-bit microcontroller family
80C575/83C575/
87C575
8K/256 OTP/ROM/ROMless, 4 comparator, failure detect circuitry, watchdog timer
VCC–0.5
0.2VCC+0.9
0.2VCC–0.1
0.45V
NOTE:
AC inputs during testing are driven at VCC –0.5 for a logic ‘1’ and 0.45V for a logic ‘0’.
Timing measurements are made at VIH min for a logic ‘1’ and VIL max for a logic ‘0’.
SU00010
Figure 27. AC Testing Input/Output
VLOAD+0.1V
TIMING
REFERENCE
POINTS
VLOAD
VLOAD–0.1V
VOH–0.1V
VOL+0.1V
NOTE:
For timing purposes, a port is no longer floating when a 100mV change from load voltage occurs,
and begins to float when a 100mV change from the loaded VOH/VOL level occurs. IOH/IOL ≥ ±20mA.
SU00011
Figure 28. Float Waveform
30
MAX ACTIVE
25
20
TYP ACTIVE
ICC (mA)
15
MAX IDLE
10
TYP IDLE
5
0
0
4
5
10
15
16
20
FREQUENCY (MHz)
SU00245
Figure 29. ICC vs. FREQ
Valid only within frequency specifications of the device under test
1998 May 01
31
Philips Semiconductors
Product specification
80C51 8-bit microcontroller family
8K/256 OTP/ROM/ROMless, 4 comparator, failure detect circuitry, watchdog timer
VCC
ICC
VCC
VCC
RST
EA
(NC)
XTAL2
CLOCK SIGNAL
XTAL1
VSS
SU00246
Figure 30. ICC Test Condition, Active Mode
All other pins are disconnected
VCC
ICC
VCC
VCC
RST
EA
(NC)
XTAL2
CLOCK SIGNAL
XTAL1
VSS
SU00247
Figure 31. ICC Test Condition, Idle Mode
All other pins are disconnected
VCC–0.5
0.45V
0.7VCC
0.2VCC–0.1
tCHCL
tCHCX
tCLCH
tCLCX
tCLCL
SU00009
Figure 32. Clock Signal Waveform for ICC Tests in Active and Idle Modes
tCLCH = tCHCL = 5ns
1998 May 01
32
80C575/83C575/
87C575
Philips Semiconductors
Product specification
80C51 8-bit microcontroller family
8K/256 OTP/ROM/ROMless, 4 comparator, failure detect circuitry, watchdog timer
VCC
ICC
VCC
VCC
RST
EA
(NC)
XTAL2
XTAL1
VSS
SU00248
Figure 33. ICC Test Condition, Power Down Mode
All other pins are disconnected. VCC = 2V to 5.5V
1998 May 01
33
80C575/83C575/
87C575
Philips Semiconductors
Product specification
80C51 8-bit microcontroller family
80C575/83C575/
87C575
8K/256 OTP/ROM/ROMless, 4 comparator, failure detect circuitry, watchdog timer
EPROM CHARACTERISTICS
To put the 87C575 in the EPROM
programming mode, PSEN must be held high
during power up, then driven low with reset
active. The 87C575 is programmed by using
a modified Quick-Pulse Programming
algorithm. It differs from older methods in the
value used for VPP (programming supply
voltage) and in the width and number of the
ALE/PROG pulses.
The 87C575 contains two signature bytes
that can be read and used by an EPROM
programming system to identify the device.
The signature bytes identify the device as an
87C575 manufactured by Philips.
Table 3 shows the logic levels for reading the
signature byte, and for programming the
program memory, the encryption table, and
the security bits. The circuit configuration and
waveforms for quick-pulse programming are
shown in Figures 34 and 35. Figure 36 shows
the circuit configuration for normal program
memory verification.
Quick-Pulse Programming
The setup for microcontroller quick-pulse
programming is shown in Figure 34. Note that
the 87C575 is running with a 4 to 6MHz
oscillator. The reason the oscillator needs to
be running is that the device is executing
internal address and program data transfers.
Table 3.
The address of the EPROM location to be
programmed is applied to ports 1 and 2, as
shown in Figure 34. The code byte to be
programmed into that location is applied to
port 0. RST, PSEN and pins of ports 2 and 3
specified in Table 3 are held at the ‘Program
Code Data’ levels indicated in Table 3. The
ALE/PROG is pulsed low 25 times as shown
in Figure 35.
To program the encryption table, repeat the
25 pulse programming sequence for
addresses 0 through 1FH, using the ‘Pgm
Encryption Table’ levels. Do not forget that
after the encryption table is programmed,
verification cycles will produce only encrypted
data.
To program the security bits, repeat the 25
pulse programming sequence using the ‘Pgm
Security Bit’ levels. After one security bit is
programmed, further programming of the
code memory and encryption table is
disabled. However, the other security bit can
still be programmed.
Note that the EA/VPP pin must not be allowed
to go above the maximum specified VPP level
for any amount of time. Even a narrow glitch
above that voltage can cause permanent
damage to the device. The VPP source
should be well regulated and free of glitches
and overshoot.
Program Verification
If security bit 2 has not been programmed,
the on-chip program memory can be read out
for program verification. The address of the
program memory locations to be read is
applied to ports 1 and 2 as shown in
Figure 36. The other pins are held at the
‘Verify Code Data’ levels indicated in Table 3.
The contents of the address location will be
emitted on port 0. External pull-ups are
required on port 0 for this operation.
If the encryption table has been programmed,
the data presented at port 0 will be the
exclusive NOR of the program byte with one
of the encryption bytes. The user will have to
know the encryption table contents in order to
correctly decode the verification data. The
encryption table itself cannot be read out.
Reading the Signature Bytes
The signature bytes are read by the same
procedure as a normal verification of
locations 030H and 031H, except that P3.6
and P3.7 need to be pulled to a logic low. The
values are:
(030H) = 15H indicates manufactured by
Philips
(B0H) = 97H indicates 87C575
Program/Verify Algorithms
Any algorithm in agreement with the
conditions listed in Table 3, and which
satisfies the timing specifications, is suitable.
EPROM Programming Modes
MODE
RST
PSEN
ALE/PROG
EA/VPP
P2.7
P2.6
P3.7
P3.6
Read signature
0
0
1
1
0
0
0
0
Program code data
0
0
0*
VPP
1
0
1
1
Verify code data
0
0
1
1
0
0
1
1
Pgm encryption table
0
0
0*
VPP
1
0
1
0
Pgm security bit 1
0
0
0*
VPP
1
1
1
1
Pgm security bit 2
0
0
0*
VPP
1
1
0
0
NOTES:
1. ‘0’ = Valid low for that pin, ‘1’ = valid high for that pin.
2. VPP = 12.75V ±0.25V.
3. VCC = 5V±10% during programming and verification.
* ALE/PROG receives 25 programming pulses while VPP is held at 12.75V. Each programming pulse is low for 100µs (±10µs) and high for a
minimum of 10µs.
Trademark phrase of Intel Corporation.
1998 May 01
34
Philips Semiconductors
Product specification
80C51 8-bit microcontroller family
80C575/83C575/
87C575
8K/256 OTP/ROM/ROMless, 4 comparator, failure detect circuitry, watchdog timer
+5V
VCC
A0–A7
P0
P1
0
RST
1
P3.6
1
P3.7
PGM DATA
+12.75V
EA/VPP
25 100µs PULSES TO GROUND
ALE/PROG
87C575
XTAL2
4–6MHz
XTAL1
PSEN
0
P2.7
1
P2.6
0
A8–A12
P2.0–P2.4
VSS
SU00249
Figure 34. Programming Configuration
25 PULSES
1
ALE/PROG:
0
10µs MIN
1
ALE/PROG:
100µs+10
0
SU00018
Figure 35. PROG Waveform
+5V
VCC
A0–A7
P0
P1
PGM DATA
0
RST
EA/VPP
1
1
P3.6
ALE/PROG
1
1
P3.7
PSEN
0
87C575
XTAL2
4–6MHz
XTAL1
P2.7
0 ENABLE
P2.6
0
P2.0–P2.4
A8–A12
VSS
SU00250
Figure 36. Program Verification
1998 May 01
35
Philips Semiconductors
Product specification
80C51 8-bit microcontroller family
80C575/83C575/
87C575
8K/256 OTP/ROM/ROMless, 4 comparator, failure detect circuitry, watchdog timer
EPROM PROGRAMMING AND VERIFICATION CHARACTERISTICS
Tamb = 21°C to +27°C, VCC = 5V±10%, VSS = 0V (See Figure 37)
SYMBOL
PARAMETER
MIN
MAX
UNIT
12.5
13.0
V
50
mA
6
MHz
VPP
Programming supply voltage
IPP
Programming supply current
1/tCLCL
Oscillator frequency
tAVGL
Address setup to PROG low
48tCLCL
tGHAX
Address hold after PROG
48tCLCL
tDVGL
Data setup to PROG low
48tCLCL
tGHDX
Data hold after PROG
48tCLCL
tEHSH
P2.7 (ENABLE) high to VPP
48tCLCL
tSHGL
VPP setup to PROG low
10
µs
tGHSL
VPP hold after PROG
10
µs
tGLGH
PROG width
90
tAVQV
Address to data valid
48tCLCL
tELQZ
ENABLE low to data valid
48tCLCL
tEHQZ
Data float after ENABLE
0
tGHGL
PROG high to PROG low
10
P1.0–P1.7
P2.0–P2.4
4
PROGRAMMING*
VERIFICATION*
ADDRESS
ADDRESS
110
µs
48tCLCL
µs
tAVQV
DATA IN
PORT 0
DATA OUT
tDVGL
tAVGL
tGHDX
tGHAX
ALE/PROG
tGLGH
tSHGL
tGHGL
tGHSL
LOGIC 1
LOGIC 1
EA/VPP
LOGIC 0
tEHSH
tELQV
tEHQZ
P2.7
ENABLE
SU00020
*
FOR PROGRAMMING VERIFICATION SEE FIGURE 34.
FOR VERIFICATION CONDITIONS SEE FIGURE 36.
Figure 37. EPROM Programming and Verification
1998 May 01
36
Philips Semiconductors
Product specification
80C51 8-bit microcontroller family
8K/256 OTP/ROM/ROMless, 4 comparator, failure detect circuitry, watchdog timer
DIP40: plastic dual in-line package; 40 leads (600 mil)
1998 May 01
37
80C575/83C575/
87C575
SOT129-1
Philips Semiconductors
Product specification
80C51 8-bit microcontroller family
8K/256 OTP/ROM/ROMless, 4 comparator, failure detect circuitry, watchdog timer
PLCC44: plastic leaded chip carrier; 44 leads
1998 May 01
80C575/83C575/
87C575
SOT187-2
38
Philips Semiconductors
Product specification
80C51 8-bit microcontroller family
8K/256 OTP/ROM/ROMless, 4 comparator, failure detect circuitry, watchdog timer
80C575/83C575/
87C575
QFP44: plastic quad flat package; 44 leads (lead length 1.3 mm); body 10 x 10 x 1.75 mm
1998 May 01
39
SOT307-2
Philips Semiconductors
Product specification
80C51 8-bit microcontroller family
8K/256 OTP/ROM/ROMless, 4 comparator, failure detect circuitry, watchdog timer
80C575/83C575/
87C575
Data sheet status
Data sheet
status
Product
status
Definition [1]
Objective
specification
Development
This data sheet contains the design target or goal specifications for product development.
Specification may change in any manner without notice.
Preliminary
specification
Qualification
This data sheet contains preliminary data, and supplementary data will be published at a later date.
Philips Semiconductors reserves the right to make chages at any time without notice in order to
improve design and supply the best possible product.
Product
specification
Production
This data sheet contains final specifications. Philips Semiconductors reserves the right to make
changes at any time without notice in order to improve design and supply the best possible product.
[1] Please consult the most recently issued datasheet before initiating or completing a design.
Definitions
Short-form specification — The data in a short-form specification is extracted from a full data sheet with the same type number and title. For
detailed information see the relevant data sheet or data handbook.
Limiting values definition — Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one
or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or
at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended
periods may affect device reliability.
Application information — Applications that are described herein for any of these products are for illustrative purposes only. Philips
Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or
modification.
Disclaimers
Life support — These products are not designed for use in life support appliances, devices or systems where malfunction of these products can
reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications
do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application.
Right to make changes — Philips Semiconductors reserves the right to make changes, without notice, in the products, including circuits, standard
cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no
responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these
products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless
otherwise specified.
 Copyright Philips Electronics North America Corporation 1998
All rights reserved. Printed in U.S.A.
Philips Semiconductors
811 East Arques Avenue
P.O. Box 3409
Sunnyvale, California 94088–3409
Telephone 800-234-7381
Date of release: 05-98
Document order number:
1998 May 01
40
9397 750 03854