PHILIPS PSMN004-25P

Philips Semiconductors
Product specification
N-channel logic level TrenchMOS transistor PSMN004-25B, PSMN004-25P
FEATURES
SYMBOL
QUICK REFERENCE DATA
• ’Trench’ technology
• Very low on-state resistance
• Fast switching
• Low thermal resistance
d
VDSS = 25 V
ID = 75 A
RDS(ON) ≤ 4 mΩ (VGS = 10 V)
g
RDS(ON) ≤ 5 mΩ (VGS = 5 V)
s
GENERAL DESCRIPTION
SiliconMAX products use the latest Philips Trench technology to achieve the lowest possible on-state resistance in
each package at each voltage rating.
Applications:• d.c. to d.c. converters
• switched mode power supplies
The PSMN004-25P is supplied in the SOT78 (TO220AB) conventional leaded package.
The PSMN004-25B is supplied in the SOT404 surface mounting package.
PINNING
SOT78 (TO220AB)
PIN
SOT404 (D2PAK)
DESCRIPTION
tab
tab
1
gate
2
drain1
3
source
tab
2
drain
1
1 23
3
LIMITING VALUES
Limiting values in accordance with the Absolute Maximum System (IEC 134)
SYMBOL PARAMETER
CONDITIONS
VDSS
VDGR
VGS
VGSM
ID
IDM
PD
Tj, Tstg
Drain-source voltage
Drain-gate voltage
Continuous gate-source
voltage
Peak pulsed gate-source
voltage
Continuous drain current
Pulsed drain current
Total power dissipation
Operating junction and
storage temperature
MIN.
MAX.
UNIT
Tj = 25 ˚C to 175˚C
Tj = 25 ˚C to 175˚C; RGS = 20 kΩ
-
25
25
± 16
V
V
V
Tj ≤ 150 ˚C
-
± 20
V
- 55
752
752
240
230
175
A
A
A
W
˚C
Tmb = 25 ˚C; VGS = 5 V
Tmb = 100 ˚C; VGS = 5 V
Tmb = 25 ˚C
Tmb = 25 ˚C
1 It is not possible to make connection to pin:2 of the SOT404 package
2 maximum continuous current limited by package
January 2000
1
Rev 1.200
Philips Semiconductors
Product specification
N-channel logic level TrenchMOS transistor
PSMN004-25B, PSMN004-25P
THERMAL RESISTANCES
SYMBOL PARAMETER
Rth j-mb
Rth j-a
Thermal resistance junction
to mounting base
Thermal resistance junction
to ambient
CONDITIONS
MIN.
SOT78 package, vertical in still air
SOT404 package, pcb mounted, minimum
footprint
TYP. MAX. UNIT
-
-
0.65
K/W
-
60
50
-
K/W
K/W
AVALANCHE ENERGY LIMITING VALUES
Limiting values in accordance with the Absolute Maximum System (IEC 134)
SYMBOL PARAMETER
EAS
Non-repetitive avalanche
energy
IAS
Non-repetitive avalanche
current
CONDITIONS
MIN.
MAX.
UNIT
-
120
mJ
-
75
A
Unclamped inductive load, IAS = 75 A;
tp = 100 µs; Tj prior to avalanche = 25˚C;
VDD ≤ 15 V; RGS = 50 Ω; VGS = 5 V
ELECTRICAL CHARACTERISTICS
Tj= 25˚C unless otherwise specified
SYMBOL PARAMETER
CONDITIONS
V(BR)DSS
VGS = 0 V; ID = 0.25 mA;
VGS(TO)
Drain-source breakdown
voltage
Gate threshold voltage
MIN.
Tj = -55˚C
VDS = VGS; ID = 1 mA
Tj = 175˚C
Tj = -55˚C
RDS(ON)
IGSS
IDSS
Drain-source on-state
resistance
VGS = 10 V; ID = 25 A
VGS = 5 V; ID = 25 A
VGS = 4.5 V; ID = 25 A
VGS = 5 V; ID = 25 A; Tj = 175˚C
Gate-source leakage current VGS = ± 10 V; VDS = 0 V;
Zero gate voltage drain
VDS = 25 V; VGS = 0 V;
current
Tj = 175˚C
TYP. MAX. UNIT
25
22
1
0.5
-
1.5
3.5
4
0.02
0.05
-
2
2.3
4
5
5.4
9.25
100
10
500
V
V
V
V
V
mΩ
mΩ
mΩ
mΩ
nA
µA
µA
Qg(tot)
Qgs
Qgd
Total gate charge
Gate-source charge
Gate-drain (Miller) charge
ID = 75 A; VDD = 15 V; VGS = 5 V
-
97
20
39
-
nC
nC
nC
td on
tr
td off
tf
Turn-on delay time
Turn-on rise time
Turn-off delay time
Turn-off fall time
VDD = 15 V; RD = 1.2 Ω
VGS = 5 V; RG = 5.6 Ω
Resistive load
-
45
220
435
320
-
ns
ns
ns
ns
Ld
Ld
Internal drain inductance
Internal drain inductance
-
3.5
4.5
-
nH
nH
Ls
Internal source inductance
Measured tab to centre of die
Measured from drain lead to centre of die
(SOT78 package only)
Measured from source lead to source
bond pad
-
7.5
-
nH
Ciss
Coss
Crss
Input capacitance
Output capacitance
Feedback capacitance
VGS = 0 V; VDS = 20 V; f = 1 MHz
-
6000
1700
1400
-
pF
pF
pF
January 2000
2
Rev 1.200
Philips Semiconductors
Product specification
N-channel logic level TrenchMOS transistor
PSMN004-25B, PSMN004-25P
REVERSE DIODE LIMITING VALUES AND CHARACTERISTICS
Tj = 25˚C unless otherwise specified
SYMBOL PARAMETER
IS
VSD
Continuous source current
(body diode)
Pulsed source current (body
diode)
Diode forward voltage
trr
Qrr
Reverse recovery time
Reverse recovery charge
ISM
January 2000
CONDITIONS
MIN.
TYP. MAX. UNIT
-
-
75
A
-
-
240
A
IF = 25 A; VGS = 0 V
IF = 75 A; VGS = 0 V
-
0.85
1.1
1.2
-
V
IF = 20 A; -dIF/dt = 100 A/µs;
VGS = 0 V; VR = 25 V
-
400
1
-
ns
µC
3
Rev 1.200
Philips Semiconductors
Product specification
N-channel logic level TrenchMOS transistor
PSMN004-25B, PSMN004-25P
Normalised Power Derating, PD (%)
1
Transient thermal impedance, Zth j-mb (K/W)
100
D = 0.5
90
0.2
80
0.1
70
0.1
60
0.05
50
0.02
40
P
D
0.01
D = tp/T
tp
30
single pulse
20
T
10
0.001
1E-06
0
0
25
50
75
100
125
Mounting Base temperature, Tmb (C)
150
175
1E-05
1E-04
1E-03
1E-02
1E-01
1E+00
Pulse width, tp (s)
Fig.1. Normalised power dissipation.
PD% = 100⋅PD/PD 25 ˚C = f(Tmb)
Fig.4. Transient thermal impedance.
Zth j-mb = f(t); parameter D = tp/T
Drain Current, ID (A)
100
Normalised Current Derating, ID (%)
100
10 V
4.5 V
5V
80
Tj = 25 C
2.8 V
90
90
VGS = 2.6 V
80
70
70
60
60
50
50
40
40
30
30
20
2.4 V
2.2 V
20
10
2V
10
0
1.8 V
0
25
50
75
100
125
Mounting Base temperature, Tmb (C)
150
0
175
0
Fig.2. Normalised continuous drain current.
ID% = 100⋅ID/ID 25 ˚C = f(Tmb)
0.4
0.6
0.8
1
1.2
1.4
Drain-Source Voltage, VDS (V)
1.6
1.8
2
Fig.5. Typical output characteristics, Tj = 25 ˚C.
ID = f(VDS)
Peak Pulsed Drain Current, IDM (A)
1000
0.2
0.02
RDS(on) = VDS/ ID
Drain-Source On Resistance, RDS(on) (Ohms)
2V
0.018
tp = 10 us
2.2 V
2.4 V
2.6 V
0.016
100 us
100
0.014
1 ms
D.C.
0.012
0.01
10 ms
100 ms
10
2.8 V
0.008
0.006
5V
4.5 V
0.004
VGS = 10V
0.002
1
Tj = 25 C
0
1
10
Drain-Source Voltage, VDS (V)
100
0
Fig.3. Safe operating area. Tmb = 25 ˚C
ID & IDM = f(VDS); IDM single pulse; parameter tp
January 2000
10
20
30
40
50
60
Drain Current, ID (A)
70
80
90
100
Fig.6. Typical on-state resistance, Tj = 25 ˚C.
RDS(ON) = f(ID)
4
Rev 1.200
Philips Semiconductors
Product specification
N-channel logic level TrenchMOS transistor
PSMN004-25B, PSMN004-25P
Threshold Voltage, VGS(TO) (V)
Drain current, ID (A)
2.25
100
VDS > ID X RDS(ON)
90
2
maximum
1.75
80
70
1.5
typical
60
1.25
50
1
40
minimum
175 C
0.75
30
20
0.5
Tj = 25 C
10
0.25
0
0
0.2 0.4 0.6 0.8
1
1.2 1.4 1.6 1.8
2
2.2 2.4 2.6 2.8
0
3
-60
-40
-20
0
Gate-source voltage, VGS (V)
40
60
80
100
120
140
160
180
Junction Temperature, Tj (C)
Fig.7. Typical transfer characteristics.
ID = f(VGS)
Fig.10. Gate threshold voltage.
VGS(TO) = f(Tj); conditions: ID = 1 mA; VDS = VGS
Transconductance, gfs (S)
140
20
Drain current, ID (A)
1.0E-01
Tj = 25 C
VDS > ID X RDS(ON)
VDS = 5 V
120
1.0E-02
175 C
100
1.0E-03
80
minimum
60
typical
maximum
1.0E-04
40
1.0E-05
20
0
1.0E-06
0
10
20
30
40
50
60
70
Drain current, ID (A)
80
90
100
0
Fig.8. Typical transconductance, Tj = 25 ˚C.
gfs = f(ID)
2
1.9
1.8
1.7
1.6
1.5
1.4
1.3
1.2
1.1
1
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
0.5
1
1.5
2
Gate-source voltage, VGS (V)
2.5
3
Fig.11. Sub-threshold drain current.
ID = f(VGS); conditions: Tj = 25 ˚C; VDS = VGS
Normalised On-state Resistance
100000
Capacitances, Ciss, Coss, Crss (pF)
10000
Ciss
Coss
Crss
1000
-60
-40
-20
0
20
40
60
80
100
Junction temperature, Tj (C)
120
140
160
180
0.1
Fig.9. Normalised drain-source on-state resistance.
RDS(ON)/RDS(ON)25 ˚C = f(Tj)
January 2000
1
10
Drain-Source Voltage, VDS (V)
100
Fig.12. Typical capacitances, Ciss, Coss, Crss.
C = f(VDS); conditions: VGS = 0 V; f = 1 MHz
5
Rev 1.200
Philips Semiconductors
Product specification
N-channel logic level TrenchMOS transistor
PSMN004-25B, PSMN004-25P
Gate-source voltage, VGS (V)
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Maximum Avalanche Current, IAS (A)
100
ID = 75 A
25 C
VDD = 15 V
Tj = 25 C
Tj prior to avalanche = 150 C
10
0
25
50
75
100 125 150 175
Gate charge, QG (nC)
200
225
1
0.001
250
0.01
0.1
1
10
Avalanche time, tAV (ms)
Fig.13. Typical turn-on gate-charge characteristics.
VGS = f(QG)
Fig.15. Maximum permissible non-repetitive
avalanche current (IAS) versus avalanche time (tAV);
unclamped inductive load
Source-Drain Diode Current, IF (A)
100
VGS = 0 V
90
80
70
60
50
40
175 C
30
Tj = 25 C
20
10
0
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1
1.1
1.2
Source-Drain Voltage, VSDS (V)
Fig.14. Typical reverse diode current.
IF = f(VSDS); conditions: VGS = 0 V; parameter Tj
January 2000
6
Rev 1.200
Philips Semiconductors
Product specification
N-channel logic level TrenchMOS transistor
PSMN004-25B, PSMN004-25P
MECHANICAL DATA
Plastic single-ended package; heatsink mounted; 1 mounting hole; 3-lead TO-220
E
SOT78
A
A1
P
q
D1
D
L1
L2(1)
Q
b1
L
1
2
e
e
3
c
b
0
5
10 mm
scale
DIMENSIONS (mm are the original dimensions)
(1)
UNIT
A
A1
b
b1
c
D
D1
E
mm
4.5
4.1
1.39
1.27
0.9
0.7
1.3
1.0
0.7
0.4
15.8
15.2
6.4
5.9
10.3
9.7
e
L
L1
2.54
15.0
13.5
3.30
2.79
L2
max.
P
q
Q
3.0
3.8
3.6
3.0
2.7
2.6
2.2
Note
1. Terminals in this zone are not tinned.
OUTLINE
VERSION
SOT78
REFERENCES
IEC
JEDEC
EIAJ
EUROPEAN
PROJECTION
ISSUE DATE
97-06-11
TO-220
Fig.16. SOT78 (TO220AB); pin 2 connected to mounting base (Net mass:2g)
Notes
1. This product is supplied in anti-static packaging. The gate-source input must be protected against static
discharge during transport or handling.
2. Refer to mounting instructions for SOT78 (TO220AB) package.
3. Epoxy meets UL94 V0 at 1/8".
January 2000
7
Rev 1.200
Philips Semiconductors
Product specification
N-channel logic level TrenchMOS transistor
PSMN004-25B, PSMN004-25P
MECHANICAL DATA
Plastic single-ended surface mounted package (Philips version of D2-PAK); 3 leads
(one lead cropped)
SOT404
A
A1
E
mounting
base
D1
D
HD
2
Lp
1
3
c
b
e
e
Q
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
UNIT
A
A1
b
c
mm
4.50
4.10
1.40
1.27
0.85
0.60
0.64
0.46
OUTLINE
VERSION
D
max.
D1
E
11
1.60
1.20
10.30
9.70
e
Lp
HD
Q
2.54
2.90
2.10
15.40
14.80
2.60
2.20
REFERENCES
IEC
JEDEC
EIAJ
EUROPEAN
PROJECTION
ISSUE DATE
98-12-14
99-06-25
SOT404
Fig.17. SOT404 surface mounting package. Centre pin connected to mounting base.
Notes
1. This product is supplied in anti-static packaging. The gate-source input must be protected against static
discharge during transport or handling.
2. Refer to SMD Footprint Design and Soldering Guidelines, Data Handbook SC18.
3. Epoxy meets UL94 V0 at 1/8".
January 2000
8
Rev 1.200
Philips Semiconductors
Product specification
N-channel logic level TrenchMOS transistor
PSMN004-25B, PSMN004-25P
MOUNTING INSTRUCTIONS
Dimensions in mm
11.5
9.0
17.5
2.0
3.8
5.08
Fig.18. SOT404 : soldering pattern for surface mounting.
DEFINITIONS
Data sheet status
Objective specification
This data sheet contains target or goal specifications for product development.
Preliminary specification This data sheet contains preliminary data; supplementary data may be published later.
Product specification
This data sheet contains final product specifications.
Limiting values
Limiting values are given in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one
or more of the limiting values may cause permanent damage to the device. These are stress ratings only and
operation of the device at these or at any other conditions above those given in the Characteristics sections of
this specification is not implied. Exposure to limiting values for extended periods may affect device reliability.
Application information
Where application information is given, it is advisory and does not form part of the specification.
 Philips Electronics N.V. 2000
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the
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The information presented in this document does not form part of any quotation or contract, it is believed to be
accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any
consequence of its use. Publication thereof does not convey nor imply any license under patent or other
industrial or intellectual property rights.
LIFE SUPPORT APPLICATIONS
These products are not designed for use in life support appliances, devices or systems where malfunction of these
products can be reasonably expected to result in personal injury. Philips customers using or selling these products
for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting
from such improper use or sale.
January 2000
9
Rev 1.200