NSC TP5088N

TP5088 DTMF Generator for Binary Data
General Description
Features
This CMOS device provides low cost tone-dialing capability
in microprocessor-controlled telephone applications. 4-bit
binary data is decoded directly, without the need for conversion to simulated keyboard inputs required by standard
DTMF generators. With the TONE ENABLE input low, the
oscillator is inhibited and the device is in a low power idle
mode. On the low-to-high transition of TONE ENABLE, data
is latched into the device and the selected tone pair from
the standard DTMF frequencies is generated. An open-drain
N-channel transistor provides a MUTE output during tone
generation.
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Direct microprocessor interface
Binary data inputs with latches
Generates 16 standard tone pairs
On-chip 3.579545 MHz crystal-controlled oscillator
Better than 0.64% frequency accuracy
High group pre-emphasis
Low harmonic distortion
MUTE output interfaces to speech network
Low power idle mode
3.5V – 8V operation
Block Diagram
TL/H/5004 – 1
*Crystal Specification: Parallel Resonant 3.579545 MHz, RS s 150X, L e 100 mH, C0 e 5 pF, C1 e 0.02 pF.
C1995 National Semiconductor Corporation
TL/H/5004
RRD-B30M115/Printed in U. S. A.
TP5088 DTMF Generator for Binary Data
October 1991
Absolute Maximum Ratings
Operating Temperature, TA
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Supply Voltage (VDDbVSS)
MUTE Voltage
Maximum Voltage at
Any Other Pin
b 30§ C to a 70§ C
Storage Temperature
b 55§ C to a 150§ C
Maximum Power Dissipation
12V
12V
500 mW
VDD a 0.3V to VSS b 0.3V
Electrical Characteristics
Unless otherwise noted, limits printed in BOLD characters are guaranteed for VDD e 3.5V to 8V, TA e 0§ C to a 70§ C by
correlation with 100% electrical testing at TA e 25§ C. All other limits are assured by correlation with other production tests and/
or product design and characterization.
Parameter
Minimum Supply Voltage, VDD (min)
Conditions
Generating Tones
Minimum Supply Voltage for Data Input,
TONE ENABLE and MUTE Logic Functions
Operating Current
Idle
Generating Tones
Min
Typ
2
V
RL e % , D0 – D3 Open
VDD e 3.5V, Mute Open
55
1.5
350
2.5
100
50
Input Low Level
TONE ENABLE, D0–D3
MUTE OUT Sink Current
(TONE ENABLE LOW)
VDD e 3.5V
Vo e 0.5V
MUTE OUT Leakage Current
(TONE ENABLE HIGH)
VDD e 3.5V
Vo e VDD
Output Amplitudes
Low Group
High Group
RL e 240 X
VDD e 3.5V
TA e 25§ C
Mean Output DC Offset
VDD e 3.5V
VDD e 8V
V
0.4
mA
130
180
170
230
mA
220
310
1.2
3.6
2.2
1 MHz Bandwidth, VDD e 5V
RL e 240X
V
0.8 VDD
1
High Group Pre-Emphasis
mA
mA
kX
kX
0.2 VDD
Input High Level
TONE ENABLE, D0–D3
Units
V
Input Pull-Up Resistance
D0 – D3
TONE ENABLE
Dual Tone/Total Harmonic Distortion Ratio
Max
3.5
2.7
b 20
Start-Up Time (to 90% Amplitude), tOSC
mVrms
mVrms
V
V
3.2
dB
dB
4
ms
Data Set-Up Time, tS (Figure 2 )
VDD e 5V
100
ns
Data Hold Time, tH
VDD e 5V
280
ns
Data Duration tW
VDD e 5V
600
ns
Note 1: RL is the external load resistor connected from TONE OUT to VSS.
2
Connection Diagram
Dual-In-Line Package
TL/H/5004 – 2
Top View
Order Number TP5088WM or TP5088N
See NS Package M14B or N14A
3.579545 MHz A-cut crystal (NTSC TV color-burst) is needed between pins 6 and 7. Load capacitors and a feedback
resistor are included on-chip for good start-up and stability.
The oscillator is stopped when the TONE ENABLE input is
pulled to logic low.
TONE ENABLE Input (Pin 2): This input has an internal
pull-up resistor. When TONE ENABLE is pulled to logic low,
the oscillator is inhibited and the tone generators and output
transistor are turned off. A low to high transition on TONE
ENABLE latches in data from D0 – D3. The oscillator starts,
and tone generation continues until TONE ENABLE is
pulled low again.
MUTE (Pin 8): This output is an open-drain N-channel device that sinks current to VSS when TONE ENABLE is low
and no tones are being generated. The device turns off
when TONE ENABLE is high.
D0, D1, D2, D3 (Pins 9, 10, 11, 12): These are the inputs for
binary-coded data, which is latched in on the rising edge of
TONE ENABLE. Data must meet the timing specifications of
Figure 2 . At all other times these inputs are ignored and may
be multiplexed with other system functions.
TONE OUT (Pin 14): This output is the open emitter of an
NPN transistor, the collector of which is connected internally to VDD. When an external load resistor is connected from
TONE OUT to VSS, the output voltage on this pin is the sum
of the high and low group tones superimposed on a DC
offset. When not generating tones, this output transistor is
turned off to minimize the device idle current.
SINGLE TONE ENABLE (Pin 3): This input has an internal
pull-up resistor. When pulled to VSS, the device is in single
tone mode and only a single tone will be generated at pin 14
(for testing purposes). For normal operation, leave this pin
open-circuit or pull to VDD.
GROUP SELECT (Pin 4): This pin is used to select the high
group or low group frequency when the device is in single
tone mode. It has an internal pull-up resistor. Leaving this
pin open-circuit or pulling it to VDD will generate the high
group, while pulling to VSS will generate the low group frequency at the TONE OUT pin.
Functional Description
With the TONE ENABLE pin pulled low, the device is in a
low power idle mode, with the oscillator inhibited and the
output transistor turned off. Data on inputs D0–D3 is ignored until a rising transition on TONE ENABLE. Data meeting the timing specifications is latched in, the oscillator and
output stage are enabled, and tone generation begins. The
decoded data sets the high group and low group programmable counters to the appropriate divide ratios. These
counters sequence two ratioed-capacitor D/A converters
through a series of 28 equal duration steps per sine wave
cycle. On-chip regulators ensure good stability of tone amplitudes with variations in supply voltage and temperature.
The two tones are summed by a mixer amplifier, with preemphasis applied to the high group tone. The output is an
NPN emitter-follower requiring the addition of an external
load resistor to VSS.
Table I shows the accuracies of the tone output frequencies
and Table II is the Functional Truth Table.
TABLE I. Output Frequency Accuracy
Tone
Group
Standard
DTMF (Hz)
Tone Output
Frequency
% Deviation
from Standard
Low
Group
fL
697
770
852
941
694.8
770.1
852.4
940.0
b 0.32
a 0.02
a 0.03
b 0.11
High
Group
fH
1209
1336
1477
1633
1206.0
1331.7
1486.5
1639.0
b 0.24
b 0.32
a 0.64
a 0.37
Pin Descriptions
VDD (Pin 1): This is the positive supply to the device, referenced to VSS. The collector of the TONE OUT transistor is
also connected to this pin.
VSS (Pin 5): This is the negative voltage supply. All voltages
are referenced to this pin.
OSC IN, OSC OUT (Pins 6 and 7): All tone generation timing is derived from the on-chip oscillator circuit. A low-cost
3
TABLE II. Functional Truth Table
Keyboard
Equivalent
Data Inputs
X
1
2
3
4
5
6
7
8
9
0
*
Ý
A
B
C
D
D3
D2
D1
D0
TONE
ENABLE
X
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
X
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
X
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
X
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
0
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
Timing Diagram
TONES OUT
fL (Hz)
fH(Hz)
0V
697
697
697
770
770
770
852
852
852
941
941
941
697
770
852
941
0V
1209
1336
1477
1209
1336
1477
1209
1336
1477
1336
1209
1477
1633
1633
1633
1633
MUTE
0V
O/C
O/C
O/C
O/C
O/C
O/C
O/C
O/C
O/C
O/C
O/C
O/C
O/C
O/C
O/C
O/C
Typical Application
TL/H/5004 – 4
*Adjust RE for desired tone amplitude.
TL/H/5004 – 3
FIGURE 2
FIGURE 3
4
Physical Dimensions inches (millimeters)
Order Number TP5088WM
NS Package Number M14B
5
TP5088 DTMF Generator for Binary Data
Physical Dimensions inches (millimeters) (Continued)
Molded Dual-In-Line (N)
Order Number TP5088N
NS Package Number N14A
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