INTEGRATED CIRCUITS DATA SHEET TDA837x family I2C-bus controlled economy PAL/NTSC and NTSC TV-processors Preliminary specification File under Integrated Circuits, IC02 1997 Jul 01 Philips Semiconductors Preliminary specification I2C-bus controlled economy PAL/NTSC and NTSC TV-processors TDA837x family FEATURES Available in all ICs: • Vision IF amplifier with high sensitivity and good figures for differential phase and gain • PLL demodulator for the IF signal • Alignment-free sound demodulator GENERAL DESCRIPTION • Flexible source selection with a CVBS input for the internal signal and Y/C or CVBS input for the external signal • Luminance delay line integrated The various versions of the TDA837x series are I2C-bus controlled single-chip TV processors which are intended to be applied in PAL/NTSC (TDA8374 and TDA8375) and NTSC (TDA8373 and TDA8377) television receivers. All ICs are available in an SDIP56 package and some versions are also available in a QFP64 package. The ICs are pin compatible so that with one application board NTSC and PAL/NTSC (or multistandard together with the SECAM decoder TDA8395) receivers can be built. • A symmetrical peaking circuit in the luminance channel Functionally this IC series is split in to 2 categories: • Black stretching of non-standard CVBS or luminance signals • Versions intended to be used in economy TV receivers with all basic functions • RGB control circuit with black current stabilization and white point adjustment • Versions with additional functions such as E-W geometry control, horizontal and vertical zoom function and YUV interface which are intended for TV receivers with 110° picture tubes. • Audio switch • The output signal of the CVBS (Y/C) switch is externally available • Integrated chrominance trap and band-pass filters (auto-calibrated) • Linear RGB inputs and fast blanking • Horizontal synchronization with two control loops and alignment-free horizontal oscillator The various type numbers are given in Table 1. • Slow start and slow stop of the horizontal drive pulses The detailed differences between the various ICs are given in Table 2. • Vertical count-down circuit • Vertical driver optimized for DC-coupled vertical output stages • I2C-bus control of various functions • Low dissipation • Small amount of peripheral components compared with competition ICs. Table 1 TV receiver versions SDIP56 PACKAGE QFP64 PACKAGE TV RECEIVERS PAL only PAL/NTSC (SECAM) NTSC 1997 Jul 01 ECONOMY MID/HIGH END ECONOMY MID/HIGH END TDA8374B − TDA8374BH − TDA8374 and TDA8374A TDA8375 and TDA8375A TDA8374AH TDA8375AH TDA8373 TDA8377 and TDA8377A − − 2 Philips Semiconductors Preliminary specification I2C-bus controlled economy PAL/NTSC and NTSC TV-processors Table 2 TDA837x family Differences between the various ICs IC VERSION (TDA) CIRCUITS 8373 8374 8374A(H) 8374B(H) 8375 8375A(H) 8377 8377A Multistandard IF − X − − X X − − Automatic Volume Levelling (AVL) X X − − − − − − PAL decoder − X X X X X − − SECAM interface − X X X X X − − NTSC decoder X X X X Colour matrix PAL/NTSC (Japan) − X X X X X X X X X − − Colour matrix NTSC (USA/Japan) X − − − − − X X YUV interface − − − Horizontal geometry − − − − X X X X − X X X X Horizontal and vertical zoom − − − − X X X X MIN. TYP. MAX. UNIT QUICK REFERENCE DATA SYMBOL PARAMETER CONDITIONS Supplies VP supply voltage − 8.0 − V IP supply current − 110 − mA V48,49(rms) video IF amplifiers sensitivity (RMS value) − 70 − µV V1(rms) sound IF amplifiers sensitivity (RMS value) − 1.0 − mV V2(rms) external audio input voltage (RMS value) − 500 − mV V11(p-p) external CVBS/Y input voltage (peak-to-peak value) − 1.0 − V V10(p-p) external chrominance input voltage (burst amplitude) (peak-to-peak value) − 0.3 − V V23-25(p-p) RGB input voltage (peak-to-peak value) − 0.7 − V V6(p-p) IF video output voltage (peak-to-peak value) − 2.5 − V I54 tuner AGC output current range 0 − 5 mA VoVSW output signal level of video switch (peak-to-peak value) − 1.0 − V V30(p-p) −(R − Y) output voltage (peak-to-peak value) − 525 − mV Input voltages Output signals 1997 Jul 01 3 Philips Semiconductors Preliminary specification I2C-bus controlled economy PAL/NTSC and NTSC TV-processors SYMBOL PARAMETER TDA837x family CONDITIONS MIN. TYP. MAX. UNIT V29(p-p) −(B − Y) output voltage (peak-to-peak value) − 675 − mV V28(p-p) luminance output voltage (peak-to-peak value) − 1.4 − V V19-21(p-p) RGB output signal amplitudes (peak-to-peak value) − 2.0 − V I40 horizontal output current − 10 − mA I46,47(p-p) vertical output current (peak-to-peak value) − 1 − mA I45(peak) E-W output current (peak value) − 1.2 − mA TDA8375A, TDA8377A, TDA8375 and TDA8377 ORDERING INFORMATION TYPE NUMBER PACKAGE NAME DESCRIPTION VERSION TDA837xA SDIP56 plastic shrink dual in-line package; 56 leads (600 mil) SOT400-1 TDA837xH QFP64 plastic quad flat package; 64 leads (lead length 1.95 mm); body 14 × 20 × 2.7 mm; high stand-off height SOT319-1 1997 Jul 01 4 1997 Jul 01 5 AFC SW 6 SW I2C-BUS TRANSCEIVER 13 17 CVBS SWITCH CVBS Y/C SWITCH SW 38 10 BAND-PASS CONTROL DACs 1 × 8 BITS 14 × 6 BITS 1 × 4 BITS TRAP IDENT tuner take-over point 8 11 16 33 HUE 43 14 REF 9 36 3.6 MHz NTSC DECODER FILTER TUNING REF VERTICAL SYNC SEPARATOR 34 SYNC SEPARATOR AND 1st LOOP VCO AND CONTROL 44 30 R−Y B−Y 12 29 42 41 32 31 G - Y MATRIX AND SAT CONTROL SAT DELAY AND PEAKING BLACK STRETCHER HORIZONTAL/ VERTICAL DIVIDER 2nd LOOP AND HORIZONTAL OUTPUT 37 39 3 BLACK CURRENT STABILIZER VERTICAL GEOMETRY 23 24 25 RGB MATRIX RGB INPUT AND SWITCH 3 RGB CONTROL AND OUTPUT white CONTR point BRI TDA8373 Fig.1 Block diagram of bus-controlled economy NTSC TV-processor TDA8373. SOUND TRAP PLL DEMODULATOR PRE-AMPLIFIER AND MUTE MUTE VIDEO AMPLIFIER AND MUTE MUTE VIDEO IDENTIFICATION AGC FOR IF AND TUNER 7 ook, full pagewidth SOUND BAND-PASS LIMITER VOL AVL AND SWITCH AND VOLUME CONTROL AFC VIF AMPLIFIER AND PLL DEMODULATOR ADJ 53 26 MGK286 19 20 21 22 18 52 51 47 46 50 40 I2C-bus controlled economy PAL/NTSC and NTSC TV-processors The TDA8373 is only supplied in an SDIP package. 1 56 45 2 55 15 5 49 48 4 3 VCO ADJUSTMENT 54 +8 V Philips Semiconductors Preliminary specification TDA837x family BLOCK DIAGRAM 1997 Jul 01 6 AFC SW 6 PLL DEMODULATOR PRE-AMPLIFIER AND MUTE SW 13 17 CVBS SWITCH CVBS Y/C SWITCH SW 38 10 BAND-PASS CONTROL DACs 1 × 8 BITS 14 × 6 BITS 1 × 4 BITS TRAP IDENT 8 TRANSCEIVER I2C-BUS 7 11 16 33 HUE 43 14 44 4.4 MHz 36 3.6 MHz (51) 35 PAL/NTSC DECODER FILTER TUNING REF VERTICAL SYNC SEPARATOR 34 REF 9 SYNC SEPARATOR AND 1st LOOP VCO AND CONTROL 30 29 R−Y B−Y 12 42 41 TDA4665 32 31 G - Y MATRIX AND SAT CONTROL SAT DELAY AND PEAKING BLACK STRETCHER HORIZONTAL/ VERTICAL DIVIDER 2nd LOOP AND HORIZONTAL OUTPUT 37 39 3 BLACK CURRENT STABILIZER VERTICAL GEOMETRY 23 24 25 RGB MATRIX RGB INPUT AND SWITCH 3 RGB CONTROL AND OUTPUT white CONTR point BRI TDA8374 Fig.2 Block diagram of bus-controlled economy PAL/NTSC TV processor TDA8374. SOUND TRAP POL MUTE MUTE VIDEO AMPLIFIER AND MUTE POL VIDEO IDENTIFICATION AGC FOR IF AND TUNER tuner take-over point ok, full pagewidth SOUND BAND-PASS LIMITER VOL AVL AND SWITCH AND VOLUME CONTROL AFC VIF AMPLIFIER AND PLL DEMODULATOR ADJ 53 26 19 20 21 22 18 52 51 47 46 50 40 MGK287 I2C-bus controlled economy PAL/NTSC and NTSC TV-processors For most pins the QFP64 pinning is not indicated. 1 56 45 2 55 15 5 49 48 4 3 VCO ADJUSTMENT 54 +8 V Philips Semiconductors Preliminary specification TDA837x family 1997 Jul 01 7 1 (10) 56 (9) 2 (11) 55 (8) 15 (27) 5 (15) 49 (2) 48 (1) 4 (14) 3 (13) AFC SW (16) 6 SOUND TRAP PLL DEMODULATOR PRE-AMPLIFIER AND MUTE SW I2C-BUS TRANSCEIVER 8 (18) (24) 13 (29) (54) 17 38 CVBS SWITCH CVBS Y/C SWITCH SW HUE 43 (59) (20) (21) (28) (49) 10 11 16 33 BAND-PASS CONTROL DACs 1 × 8 BITS 18 × 6 BITS 1 × 4 BITS TRAP IDENT tuner take-over point POL MUTE MUTE VIDEO AMPLIFIER AND MUTE POL VIDEO IDENTIFICATION AGC FOR IF AND TUNER 7 (17) 4.4 MHz (52) 36 3.6 MHz (51) 35 PAL/NTSC DECODER FILTER TUNING REF VERTICAL SYNC SEPARATOR B−Y R−Y 42 (58) 41 (57) TDA4665 (48) (47) 32 31 G - Y MATRIX AND SAT CONTROL SAT DELAY PLUS PEAKING PLUS CORING BLACK STRETCHER HORIZONTAL/ VERTICAL DIVIDER 2nd LOOP AND HORIZONTAL OUTPUT (50) (46) (45) 34 30 29 REF SYNC SEPARATOR AND 1st LOOP VCO AND CONTROL 9 44 12 37 14 (25,26) (60,61) (19) (22,23) (53) BLACK CURRENT STABILIZER VERTICAL GEOMETRY E-W GEOMETRY (35) (36) (37) 23 24 25 RGB MATRIX RGB INPUT AND SWITCH 3 RGB CONTROL AND OUTPUT white CONTR point BRI (40) (39) (55) 28 27 39 3 TDA8375 40 (56) MGK288 (38) 26 (31) 19 (32) 20 (33) 21 (34) 22 (30) 18 (5) 52 (4) 51 (64) 47 (63) 46 (3) 50 (62) 45 I2C-bus controlled economy PAL/NTSC and NTSC TV-processors Fig.3 Block diagram of bus-controlled economy PAL/NTSC TV processor TDA8375. ADJ 53 (6) ook, full pagewidth SOUND BAND-PASS LIMITER VOL SWITCH AND VOLUME CONTROL AFC VIF AMPLIFIER AND PLL DEMODULATOR VCO ADJUSTMENT 54 (7) +8 V Philips Semiconductors Preliminary specification TDA837x family 1997 Jul 01 8 AFC SW 6 SOUND TRAP PLL DEMODULATOR PRE-AMPLIFIER AND MUTE MUTE VIDEO AMPLIFIER AND MUTE MUTE VIDEO IDENTIFICATION AGC FOR IF AND TUNER 13 17 CVBS SWITCH CVBS Y/C SWITCH SW 38 10 BAND-PASS 11 16 33 HUE 43 14 44 REF 9 36 3.6 MHz NTSC DECODER FILTER TUNING REF 34 VERTICAL SYNC SEPARATOR SYNC SEPARATOR AND 1st LOOP VCO AND CONTROL 42 41 BLACK STRETCHER HORIZONTAL/ VERTICAL DIVIDER 2nd LOOP AND HORIZONTAL OUTPUT 32 31 G - Y MATRIX AND SAT CONTROL SAT DELAY PLUS PEAKING PLUS CORING 37 30 29 R−Y B−Y 12 40 28 27 39 3 TDA8377 Fig.4 Block diagram of bus-controlled economy NTSC TV processor TDA8377. SW 8 I2C-BUS TRANSCEIVER 7 CONTROL DACs 1 × 8 BITS 18 × 6 BITS 1 × 4 BITS TRAP IDENT tuner take-over point full pagewidth SOUND BAND-PASS LIMITER VOL SWITCH AND VOLUME CONTROL AFC VIF AMPLIFIER AND PLL DEMODULATOR ADJ 53 23 24 25 RGB MATRIX RGB INPUT AND SWITCH 3 RGB CONTROL AND OUTPUT white CONTR point BRI BLACK CURRENT STABILIZER VERTICAL GEOMETRY E-W GEOMETRY 26 19 20 21 22 18 52 51 47 46 50 45 MGK289 I2C-bus controlled economy PAL/NTSC and NTSC TV-processors The TDA8377 is only supplied in an SDIP package. 1 56 2 55 15 5 49 48 4 3 VCO ADJUSTMENT 54 +8 V Philips Semiconductors Preliminary specification TDA837x family Philips Semiconductors Preliminary specification I2C-bus controlled economy PAL/NTSC and NTSC TV-processors TDA837x family PINNING PIN SYMBOL DESCRIPTION SDIP56 QFP64 SIF 1 10 sound IF input AUDI 2 11 external audio input VCO1 3 13 IF VCO 1 tuned circuit VCO2 4 14 IF VCO 2 tuned circuit PLL 5 15 PLL loop filter IFVO 6 16 IF video output SCL 7 17 serial clock input (I2C-bus) SDA 8 18 serial data input/output (I2C-bus) DECBG 9 19 band gap decoupling CHROMA 10 20 chrominance input CVBS/Y 11 21 CVBS/Y input VP1 12 22 and 23 CVBSint 13 24 GND1 14 25 and 26 AUDO 15 27 audio output DECFT 16 28 decoupling filter tuning CVBSext 17 29 external CVBS input BLKIN 18 30 black current input BO 19 31 blue output GO 20 32 green output RO 21 33 red output BCLIN 22 34 beam current input RI 23 35 red input GI 24 36 green input BI 25 37 blue input RGBIN 26 38 RGB insertion input 27(2) 39 luminance input YIN main supply voltage (+8 V) internal CVBS input ground YOUT 28 40 luminance output BYO 29 45 (B − Y) output RYO 30 46 (R − Y) output RYI 31 47 (R − Y) input 32 48 (B − Y) input SECref 33(1) 49 SECAM reference output XTAL1 34 50 3.58 MHz crystal connection XTAL2 35(1) 51 4.43 MHz crystal connection LFBP 36 52 loop filter burst phase detector VP2 37 53 horizontal oscillator supply voltage (+8 V) CVBSO 38 54 CVBS output BYI 1997 Jul 01 9 Philips Semiconductors Preliminary specification I2C-bus controlled economy PAL/NTSC and NTSC TV-processors TDA837x family PIN SYMBOL DESCRIPTION SDIP56 QFP64 BLPH 39 55 black peak hold capacitor HOUT 40 56 horizontal drive output FBI/SCO 41 57 flyback input and sandcastle output PH2 42 58 phase 2 filter/protection PH1 43 59 phase 1 filter GND2 44 60 and 61 EWD 45(2) 62 east-west drive output VDOB 46 63 vertical drive output B VDOA 47 64 vertical drive output A IFIN1 48 1 IF input 1 IFIN2 49 2 IF input 2 EHT/PRO 50 3 EHT/overvoltage protection input ground 2 VSAW 51 4 vertical sawtooth capacitor Iref 52 5 reference current input DECAGC 53 6 AGC decoupling capacitor AGCOUT 54 7 tuner AGC output AUDEEM 55 8 audio deemphasis DEC 56 9 decoupling sound demodulator i.c. − 12 internally connected i.c. − 41 internally connected i.c. − 42 internally connected i.c. − 43 internally connected i.c. − 44 internally connected Notes 1. In the TDA8373 and TDA8377 pin 35 (4.43 MHz crystal) is internally connected and pin 33 is just a subcarrier output which can be used as a reference signal for comb filter ICs. 2. In the TDA8373 and TDA8374 the following pins are different (SDIP56): Pin 27: not connected; Pin 45: AVL capacitor. 1997 Jul 01 10 Philips Semiconductors Preliminary specification I2C-bus controlled economy PAL/NTSC and NTSC TV-processors TDA837x family handbook, halfpage SIF 1 56 DEC AUDI 2 55 AUDEEM VCO1 3 54 AGCOUT VCO2 4 53 DECAGC PLL 5 52 Iref IFVO 6 51 VSAW SCL 7 50 EHT/PRO SDA 8 49 IFIN2 DECBG 9 48 IFIN1 CHROMA 10 47 VDOA CVBS/Y 11 46 VDOB VP1 12 45 EWD CVBSint 13 44 GND2 43 PH1 GND1 14 TDA837x 42 PH2 AUDO 15 DECFT 16 41 FBI/SCO CVBSext 17 40 HOUT BLKIN 18 39 BLPH BO 19 38 CVBSO GO 20 37 VP2 RO 21 36 LFBP BCLIN 22 35 XTAL2 RI 23 34 XTAL1 GI 24 33 SECref BI 25 32 BYI RGBIN 26 31 RYI YIN 27 30 RYO YOUT 28 29 BYO MGK284 Fig.5 Pin configuration (SDIP56). 1997 Jul 01 11 Philips Semiconductors Preliminary specification 49 SECref 50 XTAL1 51 XTAL2 52 LFBP 53 VP2 54 CVBSO TDA837x family 55 BLPH 56 HOUT 58 PH2 59 PH1 60 GND2 61 GND2 62 EWD 63 VDOB 64 VDOA handbook, full pagewidth 57 FBI/SCO I2C-bus controlled economy PAL/NTSC and NTSC TV-processors IFIN1 1 48 BYI IFIN2 2 47 RYI EHT/PRO 3 46 RYO VSAW 4 45 BYO Iref 5 44 i.c. DECAGC 6 43 i.c. AGCOUT 7 42 i.c. 41 i.c. AUDEEM 8 TDA837xH 40 YOUT DEC 9 39 YIN SIF 10 38 RGBIN AUDI 11 i.c. 12 37 BI VCO1 13 36 GI VCO2 14 35 RI 34 BCLIN PLL 15 33 RO Fig.6 Pin configuration (QFP64). 1997 Jul 01 12 GO 32 BO 31 BLKIN 30 CVBSext 29 DECFT 28 AUDO 27 GND1 26 GND1 25 CVBSint 24 VP1 23 VP1 22 CVBS/Y 21 CHROMA 20 DECBG 19 SDA 18 SCL 17 IFVO 16 MGK285 Philips Semiconductors Preliminary specification I2C-bus controlled economy PAL/NTSC and NTSC TV-processors to a gated black level AGC. Because a black level clamp pulse is required for this method of operation the circuit will only switch to black level AGC in the internal mode. FUNCTIONAL DESCRIPTION Vision IF amplifier The IF amplifier contains 3 AC-coupled control stages with a total gain control range which is higher than 66 dB. The sensitivity of the circuit is comparable with that of modern IF-ICs. The circuits contain a second fast video identification circuit which is independent of the synchronization identification circuit. Consequently, search tuning is also possible when the display section of the receiver is used as a monitor. However, this identification circuit cannot be made as sensitive as the slower sync identification circuit (SL) and it is recommended to use both identification outputs to obtain a reliable search system. The identification output is applied to the tuning system via the I2C-bus. The video signal is demodulated by a PLL carrier regenerator. This circuit contains a frequency detector and a phase detector. During acquisition the frequency detector will tune the VCO to the correct frequency. The initial adjustment of the oscillator is realized via the I2C-bus. The input of the identification circuit is connected to pin 13, the internal CVBS input (see Fig.1). This has the advantage that the identification circuit can also be made operative when a scrambled signal is received [descrambler connected between the IF video output (pin 6) and pin 13]. A second advantage is that the identification circuit can be used when the IF amplifier is not used (e.g. with built-in satellite tuners). The switching, between SECAM L and L’, can also be realized via the I2C-bus. After lock-in the phase detector controls the VCO so that a stable phase relationship between the VCO and the input signal is achieved. The VCO operates at twice the IF frequency. The reference signal for the demodulator is obtained by using a frequency divider circuit. The AFC output is obtained by using the VCO control voltage of the PLL and can be read via the I2C-bus. For fast search tuning systems the window of the AFC can be increased by a factor of 3. The setting is realized with the AFW bit. The video identification circuit can also be used to identify the selected CBVS or Y/C signal. The switching between the two modes can be realized with bit VIM. Video switches Depending on the device type the AGC detector operates on top-sync level (single standard versions) or on top-sync and top-white level (multistandard versions). The demodulation polarity is switched via the I2C-bus. The AGC detector time constant capacitor is connected externally. This is mainly because of the flexibility of the application. The time constant of the AGC system during positive modulation is rather long, this is to avoid visible variations of the signal amplitude. To improve the speed of the AGC system, a circuit has been included which detects whether the AGC detector is activated every frame period. When, during 3 frame periods, no action is detected the speed of the system is increased. For signals without peak-white information the system switches automatically 1997 Jul 01 TDA837x family The circuit has two CVBS inputs (CVBSint and CVBSext) and a Y/C input. When the Y/C input is not required pin 11 can be used as the third CVBS input. The switch configuration is illustrated in Fig.7. The selection of the various sources is made via the I2C-bus. The output signal of the CVBS switch is externally available and can be used to drive the teletext decoder, the SECAM add-on decoder and a comb filter. In applications with comb filters a Y/C input is only possible when additional switches are added. In applications without comb filters the Y/C input signal can be switched to the CVBS output. 13 Philips Semiconductors Preliminary specification I2C-bus controlled economy PAL/NTSC and NTSC TV-processors TDA837x family handbook, full pagewidth to luminance/ sync processing IDENT VIM to chrominance processing VIDEO IDENTIFICATION + S0 S0 S5 S1 S1 S6 S2 S3 S7 S4 S8 TDA837x 13 17 11 10 38 MGK301 CVBSint CVBSext CVBS/Y CHROMA CVBSO Fig.7 Configuration CVBS switch and interfacing of video identification. Sound circuit Synchronization circuit The sound band-pass and trap filters have to be connected externally. The filtered intercarrier signal is fed to a limiter circuit and is demodulated by a PLL demodulator. This PLL circuit automatically tunes to the incoming carrier signal, hence no adjustment is required. The sync separator is preceded by a controlled amplifier which adjusts the sync pulse amplitude to a fixed level. These pulses are fed to the slicing stage which operates at 50% of the amplitude. The separated sync pulses are fed to the first phase detector and to the coincidence detector. The coincidence detector is used to detect whether the line oscillator is synchronized and can also be used for transmitter identification. The circuit can be made less sensitive by using the STM bit. This mode can be used during search tuning to ensure that the tuning system will not stop at very weak input signals. The first PLL has a very high static steepness so that the phase of the picture is independent of the line frequency. The volume is controlled via the I2C-bus. The de-emphasis capacitor has to be connected externally. The non-controlled audio signal can be obtained from this pin (pin 55) (via a buffer stage). The FM demodulator can be muted via the I2C-bus. This function can be used to switch-off the sound during a channel change so that high output peaks are prevented (also on the de-emphasis output). The TDA8373 and TDA8374 contain an Automatic Volume Levelling (AVL) circuit which automatically stabilizes the audio output signal to a certain level which can be set by the user via the volume control. This function prevents big audio output fluctuations due to variations of the modulation depth of the transmitter. The AVL function can be activated via the I2C-bus. 1997 Jul 01 The line oscillator operates at twice the line frequency. The oscillator capacitor is internal. Because of the spread of internal components an automatic calibration circuit has been added to the IC. The circuit compares the oscillator frequency with that of the crystal oscillator in the colour decoder. 14 Philips Semiconductors Preliminary specification I2C-bus controlled economy PAL/NTSC and NTSC TV-processors For this reason this protection input can be used as ‘flash protection’. This results in a free-running frequency which deviates less than 2% from the typical value. When the IC is switched on the horizontal output signal is suppressed and the oscillator is calibrated as soon as all subaddress bytes have been sent. When the frequency of the oscillator is correct the horizontal drive signal is switched on. To obtain a smooth switching on and switching off behaviour of the horizontal output stage the horizontal output frequency is doubled during switch-on and switch-off (slow start/stop). During that time the duty cycle of the output pulse has such a value that maximum safety is obtained for the output stage. The drive pulses for the vertical sawtooth generator are obtained from a vertical countdown circuit. This countdown circuit has various windows depending on the incoming signal (50 or 60 Hz and standard or non-standard). The countdown circuit can be forced in various modes via the I2C-bus. To obtain short switching times of the countdown circuit during a channel change the divider can be forced in the search window using the NCIN bit. The vertical deflection can be set in the de-interlace mode via the I2C-bus. To protect the horizontal output transistor, the horizontal drive is immediately switched off (via the slow stop procedure) when a power-on reset is detected. The drive signal is switched on again when the normal switch-on procedure is followed, i.e. all subaddress bytes must be sent and, after calibration, the horizontal drive signal will be released again via the slow start procedure. To avoid damage of the picture tube when the vertical deflection fails, the guard output current of the TDA8350 and TDA8351 can be supplied to the beam current limiting input. When a failure is detected the RGB outputs are blanked and a bit is set (NDF) in the status byte of the I2C-bus. When no vertical deflection output stage is connected this guard circuit will also blank the output signals. This can be overruled using the EVG bit. When the coincidence detector indicates an out-of-lock situation the calibration procedure is repeated. The circuit has a second control loop to generate the drive pulses for the horizontal driver stage. The horizontal output is gated with the flyback pulse so that the horizontal output transistor cannot be switched on during the flyback time. Chrominance and luminance processing The circuit contains a chrominance band-pass and trap circuit. The filters are realized by using gyrator circuits. They are automatically calibrated by comparing the tuning frequency with the crystal frequency of the decoder. The luminance delay line and the delay for the peaking circuit are also realized by using gyrator circuits. The centre frequency of the chrominance band-pass filter is 10% higher than the subcarrier frequency. This compensates for the high frequency attenuation of the IF saw filter. During SECAM reception the centre frequency of the chrominance trap is reduced to obtain a better suppression of the SECAM carrier frequencies. All ICs have a black stretcher circuit which corrects the black level for incoming video signals which have a deviation between the black level and the blanking level (back porch). Adjustments can be made to the horizontal shift, vertical shift, vertical slope, vertical amplitude and the S-correction via the I2C-bus. In the TDA8375A, TDA8377A, TDA8375 and TDA8377 the E-W drive can also be adjusted via the I2C-bus. The TDA8375 and TDA8377 have a flexible zoom adjustment possibility for the vertical and horizontal deflection. When the horizontal scan is reduced to display 4 : 3 pictures on a 16 : 9 picture tube an accurate video blanking can be switched on to obtain well defined edges on the screen. The geometry processor has a differential output for the vertical drive signal and a single-ended output for the E-W drive (TDA8375A, TDA8377A, TDA8375 and TDA8377). Overvoltage conditions (X-ray protection) can be detected via the EHT tracking pin. When an overvoltage condition is detected the horizontal output drive signal will be switched off via the slow stop procedure. However, it is also possible that the drive is not switched off and that just a protection indication is given in the I2C-bus output byte. The choice is made via the input bit PRD. The ICs have a second protection input on the phase-2 filter capacitor pin. When this input is activated the drive signal is switched off immediately (without slow stop) and switched on again via the slow start procedure. 1997 Jul 01 TDA837x family The TDA8375A, TDA8377A, TDA8375 and TDA8377 have a defeatable coring function in the peaking circuit. Some of the ICs have a YUV interface so that picture improvement ICs such as the TDA9170 (contrast improvement), TDA9177 (sharpness improvement) and TDA4556 and TDA4566 (CTI) can be applied. When the TDA4556 or TDA4566 is applied it is possible to increase the gain of the luminance channel by using the GAI bit in subaddress 03 so that the resulting RGB output signals will not be affected. 15 Philips Semiconductors Preliminary specification I2C-bus controlled economy PAL/NTSC and NTSC TV-processors For a reliable calibration of the horizontal oscillator it is very important that the crystal indication bits (XA and XB) are not corrupted. For this reason the crystal bits can be read in the output bytes so that the software can check the I2C-bus transmission. Colour decoder Depending on the IC type the colour decoder can decode NTSC signals (TDA8373 and TDA8377) or PAL/NTSC signals (TDA8374 and TDA8375). The circuit contains an alignment-free crystal oscillator, a killer circuit and two colour difference demodulators. The 90° phase shift for the reference signal is made internally. RGB output circuit and black current stabilization The colour difference signals are matrixed with the luminance signal to obtain the RGB signals. Linear amplifiers have been chosen for the RGB inputs so that the circuit is suited for signals that are input from the SCART connector. The insertion blanking can be switched on or off using the IE1 bit. To ascertain whether the insertion pin has a (continuous) HIGH level or not can be read via the IN1 bit. The contrast and brightness control operate on internal and external signals. The TDA8373 and TDA8377 contain an Automatic Colour Limiting (ACL) circuit which prevents over saturation occurring when signals with a high chroma-to-burst ratio are received. This ACL function is also available in the TDA8374 and TDA8375, however, it is only active during the reception of NTSC signals. The TDA8373 and TDA8377 have a switchable colour difference matrix (via the I2C-bus) so that the colour reproduction can be adapted to the market requirements. The output signal has an amplitude of approximately 2 V (black-to-white) at nominal input signals and nominal settings of the controls. To increase the flexibility of the IC it is possible to add OSD and/or teletext signals directly at the RGB outputs. This insertion mode is controlled via the insertion input. The action to switch the RGB outputs to black has some delay which must be compensated for externally. In the TDA8374 and TDA8375 the colour difference matrix switches automatically between PAL and NTSC, however, it is also possible to fix the matrix in the PAL standard. The TDA8374 and TDA8375 can operate in conjunction with the SECAM decoder TDA8395 so that an automatic multistandard decoder can be realized. The subcarrier reference output for the SECAM decoder can also be used as a reference signal for a comb filter. Consequently, the reference signal is continuously available when PAL or NTSC signals are detected and only present during the vertical retrace period when a SECAM signal is detected. The black current stabilization is realized by using a feedback from the video output amplifiers to the RGB control circuit. The black current of the 3 guns of the picture tube is internally measured and stabilized. The black level control is active during 4 lines at the end of the vertical blanking. The vertical blanking is adapted to the incoming CVBS signal (50 or 60 Hz). When the flyback time of the vertical output stage is longer than the 60 Hz blanking time, or when additional lines need to be blanked (e.g. for close captioning lines) the blanking can be increased to the same value as that of the 50 Hz blanking. This can be set using the LBM bit. The leakage current is measured during the first line and, during the following 3 lines, the 3 guns are adjusted to the required level. The maximum acceptable leakage current is ±100 µA. The nominal value of the black current is 10 µA. The ratio of the currents for the various guns automatically tracks with the white point adjustment so that the background colour is the same as the adjusted white point. Which standard the TDA8374 and TDA8375 can decode depends on the external crystals. The crystal to be connected to pin 34 must have a frequency of 3.5 MHz (NTSC-M, PAL-M or PAL-N). Pin 35 can handle crystals with a frequency of 4.4 and 3.5 MHz. Because the crystal frequency is used to tune the line oscillator, the value of the crystal frequency must be communicated to the IC via the I2C-bus. It is also possible to use the IC in the so called ‘3-norma’ mode for South America. In that event one crystal must be connected to pin 35 and the other two to pin 34. Switching between the 2 latter crystals must be performed externally. Consequently, the search loop of the decoder must be controlled by the microcontroller. To prevent calibration problems of the horizontal oscillator the external switching between the two crystals should be performed when the oscillator is forced to pin 35. 1997 Jul 01 TDA837x family 16 Philips Semiconductors Preliminary specification I2C-bus controlled economy PAL/NTSC and NTSC TV-processors The input impedance of the black current measuring pin is 14 kΩ. To prevent the voltage on this pin exceeding the supply voltage during scan an internal protection diode has been included. TDA837x family to ascertain whether the picture tube is warming up. As soon as the current supplied to the measuring input exceeds a value of 190 µA the stabilization circuit will be activated. After a waiting time of approximately 0.8 s the blanking and beam current limiting input pins are released. The remaining switch-on behaviour of the picture is determined by the external time constant of the beam current limiting network. When the TV receiver is switched on the black current stabilization circuit is not active, the RGB outputs are blanked and the beam current limiting input pin is short-circuited. Only during the measuring lines will the outputs supply a voltage of 4.2 V to the video output stage I2C-bus specification Table 3 Slave address (8A) A6 A5 A4 A3 A2 A1 A0 R/W 1 0 0 0 1 0 1 I/O on when the oscillator is calibrated. Each time before the data in the IC is refreshed, the status bytes must be read. If POR = 1, then the procedure given above must be carried out to restart the IC. When this procedure is not followed the horizontal frequency in the TDA8374 and TDA8375 may be incorrect after power-up or a power dip. The slave address is identical for all types. The subaddresses of the various types are slightly different. The list of subaddresses for each type is given in Tables 4, 6, 8 and 10. START-UP PROCEDURE Read the status bytes until POR = 0 and send all subaddress bytes. The horizontal output signal is switched 1997 Jul 01 17 Philips Semiconductors Preliminary specification I2C-bus controlled economy PAL/NTSC and NTSC TV-processors TDA837x family TDA8373 Valid subaddresses: 00 to 16 (subaddresses 04 to 07 are not used), subaddress FE is reserved for test purposes. Auto-increment mode available for subaddresses. Table 4 Inputs DATA BYTE SUB ADDRESS D7 D6 D5 D4 D3 D2 D1 D0 Control 0 00 INA INB INC 0 FOA FOB 0 0 Control 1 01 0 0 DL STB POC 0 1 1 Hue 02 AVL AKB A5 A4 A3 A2 A1 A0 Horizontal Shift (HS) 03 VIM GAI A5 A4 A3 A2 A1 A0 Vertical Slope (VS) 08 NCIN STM A5 A4 A3 A2 A1 A0 Vertical Amplitude (VA) 09 VID LBM A5 A4 A3 A2 A1 A0 S-Correction (SC) 0A 0 EVG A5 A4 A3 A2 A1 A0 Vertical shift (VSH) 0B SBL PRD A5 A4 A3 A2 A1 A0 White point R 0C 0 0 A5 A4 A3 A2 A1 A0 White point G 0D 0 0 A5 A4 A3 A2 A1 A0 White point B 0E MAT 0 A5 A4 A3 A2 A1 A0 Peaking 0F 0 0 0 0 A3 A2 A1 A0 Brightness 10 RBL 0 A5 A4 A3 A2 A1 A0 Saturation 11 IE1 0 A5 A4 A3 A2 A1 A0 Contrast 12 AFW IFS A5 A4 A3 A2 A1 A0 FUNCTION AGC takeover 13 0 VSW A5 A4 A3 A2 A1 A0 Volume control 14 SM FAV A5 A4 A3 A2 A1 A0 Adjustment IF-PLL 15 L’FA A6 A5 A4 A3 A2 A1 A0 Spare 16 0 0 0 0 0 0 0 0 OUTPUT ADDRESS D7 D6 D5 D4 D3 D2 D1 D0 00 POR X X SL XPR CD2 CD1 CD0 01 NDF IN1 X IFI AFA AFB SXA SXB 02 X X X IVW X ID2 ID1 ID0 Table 5 Output status bytes (note 1) Note 1. X = don’t care. 1997 Jul 01 18 Philips Semiconductors Preliminary specification I2C-bus controlled economy PAL/NTSC and NTSC TV-processors TDA837x family TDA8374, TDA8374AH and TDA8374BH Valid subaddresses: 00 to 16 (subaddresses 04 to 07 are not used), subaddress FE is reserved for test purposes. Auto-increment mode available for subaddresses. Table 6 Inputs (notes 1 and 2) DATA BYTE SUB ADDRESS D7 D6 D5 D4 D3 D2 D1 D0 Control 0 00 INA INB INC 0 FOA FOB XA XB Control 1 01 FORF FORS DL STB POC CM2 CM1 CM0 Hue 02 AVL AKB A5 A4 A3 A2 A1 A0 Horizontal Shift (HS) 03 VIM GAI A5 A4 A3 A2 A1 A0 Vertical Slope (VS) 08 NCIN STM A5 A4 A3 A2 A1 A0 Vertical Amplitude (VA) 09 VID LBM A5 A4 A3 A2 A1 A0 S-Correction (SC) 0A 0 EVG A5 A4 A3 A2 A1 A0 Vertical shift (VSH) 0B SBL PRD A5 A4 A3 A2 A1 A0 White point R 0C 0 0 A5 A4 A3 A2 A1 A0 White point G 0D 0 0 A5 A4 A3 A2 A1 A0 White point B 0E MAT 0 A5 A4 A3 A2 A1 A0 Peaking 0F 0 0 0 0 A3 A2 A1 A0 Brightness 10 RBL 0 A5 A4 A3 A2 A1 A0 Saturation 11 IE1 0 A5 A4 A3 A2 A1 A0 Contrast 12 AFW IFS A5 A4 A3 A2 A1 A0 AGC takeover 13 MOD VSW A5 A4 A3 A2 A1 A0 Volume control 14 SM FAV A5 A4 A3 A2 A1 A0 Adjustment IF-PLL 15 L’FA A6 A5 A4 A3 A2 A1 A0 Spare 16 0 0 0 0 0 0 0 0 FUNCTION Notes 1. The AVL and MOD bit are not available in the TDA8374A. 2. In the TDA8374B the AVL and MOD bit is also missing and the CM0 to CM2 and CD0 to CD2 bits have less possibilities because this IC can only decode PAL or PAL/SECAM signals (when the TDA8395 is applied). Table 7 Output status bytes (note 1) OUTPUT ADDRESS D7 D6 D5 D4 D3 D2 D1 D0 00 POR FSI X SL XPR CD2 CD1 CD0 01 NDF IN1 X IFI AFA AFB SXA SXB 02 X X X IVW X ID2 ID1 ID0 Note 1. X = don’t care. 1997 Jul 01 19 Philips Semiconductors Preliminary specification I2C-bus controlled economy PAL/NTSC and NTSC TV-processors TDA837x family TDA8375 and TDA8375AH Valid subaddresses: 00 to 16, subaddress FE is reserved for test purposes. Auto-increment mode available for subaddresses. Table 8 Inputs DATA BYTE SUB ADDRESS D7 D6 D5 D4 D3 D2 D1 D0 Control 0 00 INA INB INC 0 FOA FOB XA XB Control 1 01 FORF FORS DL STB POC CM2 CM1 CM0 Hue 02 HBL AKB A5 A4 A3 A2 A1 A0 Horizontal Shift (HS) 03 VIM GAI A5 A4 A3 A2 A1 A0 E-W width (EW) 04 0 0 A5 A4 A3 A2 A1 A0 FUNCTION E-W Parabola/Width (PW) 05 0 0 A5 A4 A3 A2 A1 A0 E-W Corner Parabola (CP) 06 0 0 A5 A4 A3 A2 A1 A0 E-W trapezium (TC) 07 0 0 A5 A4 A3 A2 A1 A0 Vertical Slope (VS) 08 NCIN STM A5 A4 A3 A2 A1 A0 Vertical Amplitude (VA) 09 VID LBM A5 A4 A3 A2 A1 A0 S-Correction (SC) 0A HCO EVG A5 A4 A3 A2 A1 A0 Vertical shift (VSH) 0B SBL PRD A5 A4 A3 A2 A1 A0 White point R 0C 0 0 A5 A4 A3 A2 A1 A0 White point G 0D 0 0 A5 A4 A3 A2 A1 A0 White point B 0E MAT 0 A5 A4 A3 A2 A1 A0 Peaking 0F 0 0 0 0 A3 A2 A1 A0 Brightness 10 RBL COR A5 A4 A3 A2 A1 A0 Saturation 11 IE1 0 A5 A4 A3 A2 A1 A0 Contrast 12 AFW IFS A5 A4 A3 A2 A1 A0 AGC takeover 13 MOD VSW A5 A4 A3 A2 A1 A0 Volume control 14 SM FAV A5 A4 A3 A2 A1 A0 Adjustment IF-PLL 15 L’FA A6 A5 A4 A3 A2 A1 A0 Vertical zoom (VX)(1) 16 0 0 A5 A4 A3 A2 A1 A0 Note 1. The vertical zoom byte and the HBL bit are active only in the TDA8375. Table 9 Output status bytes (note 1) OUTPUT ADDRESS D7 D6 D5 D4 D3 D2 D1 D0 00 POR FSI X SL XPR CD2 CD1 CD0 01 NDF IN1 X IFI AFA AFB SXA SXB 02 X X X IVW X ID2 ID1 ID0 Note 1. X = don’t care. 1997 Jul 01 20 Philips Semiconductors Preliminary specification I2C-bus controlled economy PAL/NTSC and NTSC TV-processors TDA837x family TDA8377 and TDA8377A Valid subaddresses: 00 to 16, subaddress FE is reserved for test purposes. Auto-increment mode available for subaddresses. Table 10 Inputs DATA BYTE SUB ADDRESS D7 D6 D5 D4 D3 D2 D1 D0 Control 0 00 INA INB INC 0 FOA FOB 0 1 Control 1 01 0 0 DL STB POC 0 1 1 Hue 02 HBL AKB A5 A4 A3 A2 A1 A0 Horizontal Shift (HS) 03 VIM GAI A5 A4 A3 A2 A1 A0 E-W width (EW) 04 0 0 A5 A4 A3 A2 A1 A0 FUNCTION E-W Parabola/Width (PW) 05 0 0 A5 A4 A3 A2 A1 A0 E-W Corner Parabola (CP) 06 0 0 A5 A4 A3 A2 A1 A0 E-W trapezium (TC) 07 0 0 A5 A4 A3 A2 A1 A0 Vertical Slope (VS) 08 NCIN STM A5 A4 A3 A2 A1 A0 Vertical Amplitude (VA) 09 VID 0 A5 A4 A3 A2 A1 A0 S-Correction (SC) 0A HCO EVG A5 A4 A3 A2 A1 A0 Vertical shift (VSH) 0B SBL PRD A5 A4 A3 A2 A1 A0 White point R 0C 0 0 A5 A4 A3 A2 A1 A0 White point G 0D 0 0 A5 A4 A3 A2 A1 A0 White point B 0E MAT 0 A5 A4 A3 A2 A1 A0 Peaking 0F 0 0 0 0 A3 A2 A1 A0 Brightness 10 RBL COR A5 A4 A3 A2 A1 A0 Saturation 11 IE1 0 A5 A4 A3 A2 A1 A0 Contrast 12 AFW IFS A5 A4 A3 A2 A1 A0 AGC takeover 13 0 VSW A5 A4 A3 A2 A1 A0 Volume control 14 SM FAV A5 A4 A3 A2 A1 A0 Adjustment IF-PLL 15 L’FA A6 A5 A4 A3 A2 A1 A0 Vertical zoom (VX)(1) 16 0 0 A5 A4 A3 A2 A1 A0 Note 1. The vertical zoom byte and the HBL bit are active only in the TDA8377. Table 11 Output status bytes (note 1) OUTPUT ADDRESS D7 D6 D5 D4 D3 D2 D1 D0 00 POR X X SL XPR CD2 CD1 CD0 01 NDF IN1 X IFI AFA AFB SXA SXB 02 X X X IVW X ID2 ID1 ID0 Note 1. X = don’t care. 1997 Jul 01 21 Philips Semiconductors Preliminary specification I2C-bus controlled economy PAL/NTSC and NTSC TV-processors TDA837x family INPUT CONTROL BITS Table 12 Source select INA INB INC SELECTED SIGNALS (DECODER AND AUDIO) SWITCH OUTPUT 0 0 0 internal CVBS plus audio internal CVBS 0 0 1 external CVBS plus audio external CVBS 0 1 0 Y/C plus external audio Y/C (Y plus C) 0 1 1 CVBS3 plus external audio CVBS3 1 0 0 Y/C plus internal audio internal CVBS 1 1 0 Y/C plus external audio external CVBS Table 13 Phase 1 (ϕ-1) time constant FOA FOB MODE 0 0 normal 0 1 slow and gated 1 0 slow/fast and gated 1 1 fast XA XB CRYSTAL 0 0 two 3.6 MHz crystals 0 1 one 3.6 MHz crystal (pin 34) 1 0 one 4.4 MHz crystal (pin 35) 1 1 3.6 MHz and 4.4 MHz crystals (pins 34 and 35) Table 14 Crystal indication Table 15 Forced field frequency TDA8374 and TDA8375 FORF FORS FIELD FREQUENCY 0 0 auto (60 Hz when line not synchronized) 0 1 60 Hz; note 1 1 0 keep last detected field frequency 1 1 auto (50 Hz when line not synchronized) Note 1. When switched to this mode while locked to a 50 Hz signal, the divider will only switch to forced 60 Hz when an out-of-sync is detected in the horizontal PLL. 1997 Jul 01 22 Philips Semiconductors Preliminary specification I2C-bus controlled economy PAL/NTSC and NTSC TV-processors Table 16 Interlace TDA837x family Table 22 Black current stabilization DL AKB STATUS STABILIZATION 0 interlace 0 black-current stabilization on 1 de-interlace 1 black-current stabilization off Table 17 Standby Table 23 Video identification mode STB VIM MODE 0 standby 1 normal 0 video identification coupled to the internal CVBS input (pin 13) 1 video identification coupled to the selected CVBS input Table 18 Synchronization mode POC MODE 0 synchronization active 1 synchronization not active Table 24 Gain of luminance channel GAI CM1 CM0 DECODER MODE 0 0 0 not forced, own intelligence, two crystals 0 0 1 forced crystal pin 34 (PAL/NTSC) 0 1 0 forced crystal pin 34 (PAL) GAIN 0 normal gain of luminance channel [V27 = 1.0 V (b-w)] 1 high gain of luminance channel [V27 = 0.45 V (p-p)] Table 19 Colour decoder mode CM2 VIDEO IDENT MODE Table 25 Vertical divider mode NCIN VERTICAL DIVIDER MODE 0 normal operation of the vertical divider 1 vertical divider switched to search window 0 1 1 forced crystal pin 34 (NTSC) 1 0 0 forced crystal pin 35 (PAL/NTSC) 1 0 1 forced crystal pin 35 (PAL) 1 1 0 forced crystal pin 35 (NTSC) 0 normal operation 1 1 1 forced SECAM crystal pin 35 1 reduced sensitivity of the coincidence detector (bit SL) Table 26 Search tuning mode STM Table 20 Automatic volume levelling (TDA8373 and TDA8374) AVL Table 27 Video identification mode LEVEL 0 automatic volume levelling not active 1 automatic volume levelling active SEARCH TUNING MODE VID VIDEO IDENT MODE 0 video identification switches phase 1 loop on and off 1 video identification not active Table 21 RGB blanking mode (TDA8375 and TDA8377) Table 28 Long blanking mode (TDA8374 and TDA8375) HBL 0 1 MODE LBM normal blanking with horizontal blanking pulse wider blanking to obtain well defined edges 1997 Jul 01 23 BLANKING MODE 0 blanking adapted to standard (50 or 60 Hz) 1 fixed blanking in accordance with 50 Hz standard Philips Semiconductors Preliminary specification I2C-bus controlled economy PAL/NTSC and NTSC TV-processors Table 29 EHT tracking mode (TDA8375 and TDA8377) HCO Table 36 Noise coring peaking (TDA8375 and TDA8377)) TRACKING MODE 0 EHT tracking only on vertical 1 EHT tracking on vertical and E-W TDA837x family COR MODE 0 noise coring off 1 noise coring on Table 30 Enable vertical guard (RGB blanking) EVG Table 37 Enable fast blanking VERTICAL GUARD MODE 0 vertical guard not active 1 vertical guard active IE1 FAST BLANKING 0 fast blanking not active 1 fast blanking active Table 31 Service blanking SBL Table 38 AFC window SERVICE BLANKING MODE 0 service blanking off AFW AFC WINDOW 1 service blanking on 0 normal window 1 enlarged window Table 32 Overvoltage input mode PRD Table 39 IF sensitivity OVERVOLTAGE MODE 0 overvoltage detection mode IFS 1 overvoltage protection mode 0 normal sensitivity 1 reduced sensitivity Table 33 PAL/NTSC or NTSC matrix (TDA8374 and TDA8375) MAT 0 1 IF SENSITIVITY Table 40 Modulation standard (TDA8374 and TDA8375) MATRIX MOD matrix adapted to standard (NTSC = Japanese) MODULATION 0 negative modulation 1 positive modulation PAL matrix Table 41 Video mute Table 34 PAL/NTSC or NTSC matrix (TDA8373 and TDA8377) MAT VSW MATRIX 0 Japanese matrix 1 USA matrix blanking not active 1 blanking active 1997 Jul 01 normal operation 1 IF video signal switched off SM MODE 0 0 Table 42 Sound mute Table 35 RGB blanking RBL STATE 24 STATE 0 normal operation 1 sound muted Philips Semiconductors Preliminary specification I2C-bus controlled economy PAL/NTSC and NTSC TV-processors Table 43 Fixed audio volume FAV TDA837x family Table 50 Output vertical guard STATE NDF VERTICAL OUTPUT STAGE 0 normal volume control 0 vertical output stage OK 1 audio output level fixed 1 failure in vertical output stage Table 44 Demodulator frequency adjustment L’FA Table 51 Indication RGB insertion STATE IN1 RGB INSERTION 0 normal IF frequency 0 no insertion 1 frequency shift for L’ standard 1 insertion OUTPUT CONTROL BITS Table 52 Output video identification Table 45 Power-on-reset IFI POR MODE 0 normal mode 1 power-down mode no video signal identified 1 video signal identified AFA AFB 0 0 outside window; too low 50 Hz 0 1 outside window; too high 60 Hz 1 0 inside window; below reference 1 1 inside window; above reference FSI 1 0 Table 53 AFC output Table 46 Field frequency (TDA8374 and TDA8375) 0 VIDEO SIGNAL FREQUENCY CONDITION Table 47 Phase 1 lock indication SL Table 54 Crystal indication INDICATION 0 not locked 1 locked Table 48 X-ray protection XPR OVERVOLTAGE 0 no overvoltage detected 1 overvoltage detected SXA SXB 0 0 two 3.6 MHz crystals 0 1 one 3.6 MHz crystal 1 0 one 4.4 MHz crystal 1 1 3.6 MHz and 4.4 MHz crystals Table 55 Condition vertical divider IVW Table 49 Colour decoder mode (TDA8374 and TDA8375) CD2 CD1 CD0 0 0 0 no colour standard identified 0 0 1 NTSC with crystal at pin 34 0 1 0 PAL with crystal at pin 35 0 1 1 SECAM 1 0 0 NTSC with crystal at pin 35 1 0 1 PAL with crystal at pin 34 1 1 0 spare 1 1 1 spare 1997 Jul 01 CRYSTAL STANDARD 25 VIDEO SIGNAL 0 no standard video signal detected 1 standard video signal detected (525 or 625 lines) Philips Semiconductors Preliminary specification I2C-bus controlled economy PAL/NTSC and NTSC TV-processors TDA837x family Table 56 IC version indication ID2 ID1 ID0 STANDARD 0 0 0 TDA8373 0 0 1 TDA8377 0 1 0 TDA8374B 0 1 1 TDA8374A 1 0 0 TDA8374 1 0 1 TDA8377A 1 1 0 TDA8375A 1 1 1 TDA8375 LIMITING VALUES In accordance with the Absolute Maximum Rating System (IEC 134). SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT VP supply voltage − 9.0 V Tstg storage temperature −25 +150 °C Tamb operating ambient temperature 0 70 °C Tsld soldering temperature − 260 °C Tj operating junction temperature − 150 °C Ves electrostatic handling for 5 s HBM; all pins; notes 1 and 2 −2000 +2000 V MM; all pins; notes 1 and 3 −200 +200 V Notes 1. All pins are protected against ESD by means of internal clamping diodes. 2. Human Body Model (HBM): R = 1.5 kΩ; C = 100 pF. 3. Machine Model (MM): R = 0 Ω; C = 200 pF. QUALITY SPECIFICATION In accordance with “SNW-FQ-611E”. The number of the quality specification can be found in the “Quality Reference Handbook”. The handbook can be ordered using the code 9397 750 00192. Latch-up • Itrigger ≥ 100 mA or ≥1.5VP(max) • Itrigger ≤ −100 mA or ≤−0.5VP(max). 1997 Jul 01 26 Philips Semiconductors Preliminary specification I2C-bus controlled economy PAL/NTSC and NTSC TV-processors TDA837x family CHARACTERISTICS VP = 8 V; Tamb = 25 °C; the pin numbers given refer to the SDIP56 package; unless otherwise specified. SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT Supplies MAIN SUPPLY (PIN 12) VP1 supply voltage 7.2 8.0 8.8 V IP1 supply current − 110 − mA Ptot total power dissipation − 900 − mW HORIZONTAL OSCILLATOR SUPPLY (PIN 37) VP2 supply voltage 7.2 8.0 8.8 V IP2 supply current − 6 − mA IF circuit VISION IF AMPLIFIER INPUTS (PINS 48 AND 49) Vi(rms) input sensitivity (RMS value) note 1 fi = 38.90 MHz − 70 100 µV fi = 45.75 MHz − 70 100 µV fi = 58.75 MHz − 70 100 µV 2 − kΩ Ri input resistance (differential) note 2 − Ci input capacitance (differential) note 2 − 3 − pF ∆Gv voltage gain control range 64 − − dB Vi(max)(rms) maximum input signal (RMS value) 100 150 − mV PLL DEMODULATOR (PLL FILTER ON PIN 5); note 3 fPLL PLL frequency range 32 − 60 MHz fcr(PLL) PLL catching range − 2 − MHz tacq(PLL) PLL acquisition time − − 20 ms ∆fVCO(T) VCO frequency variation with temperature note 4 − tbf − kHz/K ftune(VCO) VCO tuning range via the I2C-bus − 2.5 − MHz ∆fDAC frequency variation per step of the DAC (A0 to A6) − 20 − kHz fshift(L’) frequency shift with the L’ FA bit − 5.5 − MHz 1997 Jul 01 27 Philips Semiconductors Preliminary specification I2C-bus controlled economy PAL/NTSC and NTSC TV-processors SYMBOL PARAMETER TDA837x family CONDITIONS MIN. TYP. MAX. UNIT VIDEO AMPLIFIER OUTPUT (PIN 6); note 5 Vo zero signal output level − 4.7 − V positive modulation; note 6 − 2.0 − V negative modulation; note 6 V6(ts) top sync level negative modulation 1.9 2.0 2.1 V V6(w) white level positive modulation when available − 4.5 − V ∆V6 difference in amplitude between negative and positive modulation − 0 15 % Zo video output impedance − 50 − Ω Ibias internal bias current of NPN emitter follower output transistor 1.0 − − mA Isource(max) maximum source current − − 5 mA B bandwidth of demodulated output signal at −3 dB 6 9 − MHz Gdiff differential gain note 7 − 2 5 % ϕdiff differential phase notes 4 and 7 − − 5 deg NLvid video non-linearity note 8 − − 5 % Vclamp white spot clamp level − 5.3 − V Nth(clamp) noise inverter threshold clamp level note 9 − 1.7 − V Nins noise inverter insertion level note 9 − 2.6 − V δ intermodulation notes 4 and 10 Vo = 0.92 or 1.1 MHz 60 66 − dB Vo = 2.66 or 3.3 MHz 60 66 − dB Vo = 0.92 or 1.1 MHz 56 62 − dB Vo = 2.66 or 3.3 MHz 60 66 − dB blue yellow S/N signal-to-noise ratio notes 4 and 11 Vi = 10 mV 52 60 − dB at end of control range 52 61 − dB V6(rc) residual carrier signal note 4 − 5.5 − mV V6(2H) residual 2nd harmonic of carrier signal note 4 − 2.5 − mV 1997 Jul 01 28 Philips Semiconductors Preliminary specification I2C-bus controlled economy PAL/NTSC and NTSC TV-processors SYMBOL PARAMETER TDA837x family CONDITIONS MIN. TYP. MAX. UNIT IF AND TUNER AGC; note 12 Timing of IF-AGC with a 2.2 µF capacitor (pin 53) modulated video interference 30% AM for 1 to 100 mV; 0 to 200 Hz (system B/G) − − 10 % tres(IFinc) response time to an IF input signal amplitude increase of 52 dB positive (when available) and negative modulation − 2 − ms tres(IFdec) response to an IF input signal amplitude decrease of 52 dB negative modulation − 50 − ms positive modulation (when available) − 100 − ms negative modulation − − 10 µA positive modulation (when available) − − 200 nA I53 allowed leakage current of the AGC capacitor Tuner take-over adjustment (via I2C-bus) Vi(min)(rms) minimum starting level for tuner take-over (RMS value) − 0.4 0.8 mV Vi(max)(rms) maximum starting level for tuner take-over (RMS value) 40 80 − mV Tuner control output (pin 54) VoAGC(max) maximum tuner AGC output voltage maximum tuner gain; note 2 − − VP + 1 V Vo(sat) output saturation voltage minimum tuner gain; I54 = 2 mA − − 300 mV IoAGC(max) maximum tuner AGC output swing 5 − − mA ILI(RF) leakage current RF AGC − − 1 µA ∆Vi input signal variation for a control current variation of 1 mA 0.5 2 4 dB AFC OUTPUT (VIA I2C-BUS); note 13 RESAFC AFC resolution − 2 − bits wsen window sensitivity 65 80 100 kHz wsenL window sensitivity in large window mode 195 240 300 kHz − − 10 ms VIDEO IDENTIFICATION OUTPUT (VIA I2C-BUS) td 1997 Jul 01 delay time of identification after the AGC has stabilized on a new transmitter 29 Philips Semiconductors Preliminary specification I2C-bus controlled economy PAL/NTSC and NTSC TV-processors SYMBOL PARAMETER TDA837x family CONDITIONS MIN. TYP. MAX. UNIT Sound circuit DEMODULATOR PART − 1 2 mV note 14 4.2 − 6.8 MHz note 2 − 8.5 − kΩ input capacitance note 2 − − 5 pF AM rejection Vi = 50 mV (RMS); note 15 60 66 − dB Vo(rms) output signal amplitude (RMS value) note 14 − 500 − mV Ro output resistance − 15 − kΩ VO DC output voltage − 3 − V Vi(crPLL)(rms) input limiting voltage for PLL catching range (RMS value) fcr(PLL) PLL catching range Ri input resistance Ci AMR DE-EMPHASIS AUDIO ATTENUATOR CIRCUIT Vo(rms) controlled output signal amplitude (RMS value) at −6 dB; note 14 500 700 900 mV VoAVL(rms) output signal level when AVL is activated (RMS value) note 16 300 400 500 mV VoFAV(rms) output signal level when FAV is activated (RMS value) note 14 − 500 − mV Ro output resistance − 500 − Ω VO DC output voltage − 3.3 − V THD total harmonic distortion note 17 − − 0.5 % FAV = 1; note 18 − − tbf % PSRR power supply ripple rejection note 4 − tbf − dB S/Nint internal signal-to-noise ratio notes 4 and 19 − 60 − dB S/Next external signal-to-noise ratio notes 4 and 19 − 80 − dB Tdep(out) temperature dependancy of output level notes 4 and 20 − − tbf dB CR control range tbf 80 tbf dB VCstep step size volume control − 1.5 − dB control curve see Fig.8 OSS suppression of output signal when the mute is active − 80 − dB Vshift DC shift of the output level when the mute is activated − 10 50 mV EXTERNAL AUDIO INPUT Vi(rms) input signal amplitude (RMS value) − 500 1500 mV Ri input resistance − 25 − kΩ 1997 Jul 01 30 Philips Semiconductors Preliminary specification I2C-bus controlled economy PAL/NTSC and NTSC TV-processors SYMBOL PARAMETER Gv(in-out) voltage gain between input and output αct crosstalk between audio signals TDA837x family CONDITIONS maximum volume MIN. TYP. MAX. − 12 − 60 − − UNIT dB AUTOMATIC VOLUME LEVELLING CIRCUIT (TDA8373 AND TDA8374 ONLY; CAPACITOR CONNECTED TO PIN 45) Gmax gain maximum boost; note 16 − 6 − dB Gmin gain minimum boost − −14 − dB Iatt attack charge current − 1 − mA Idec decay discharge current − 200 − nA Vctrl(max) control voltage maximum boost − 1 − V Vctrl(min) control voltage minimum boost − 5 − V − 1.0 1.4 V CVBS, Y/C, RGB, CD inputs and luminance input and output CVBS AND Y/C SWITCH (PINS 11, 13, 17 AND 38) V11(p-p) CVBS or Y input voltage (peak-to-peak value) I17 CVBS input current − 4 − µA SSCVBS suppression of non-selected CVBS input signal notes 4 and 22 50 − − dB V10(p-p) chrominance input voltage (burst amplitude) (peak-to-peak value) notes 2 and 23 − 0.3 0.45 V V38(p-p) output signal amplitude (peak-to-peak value) − 1.0 − V Zo output impedance − − 250 Ω Vsync top sync level − 2.5 − V note 21 RGB INPUTS (PINS 23, 24 AND 25) V23-25(p-p) input signal amplitude for an output signal of 2 V (black-to-white) (peak-to-peak value) note 24 − 0.7 0.8 V V23-25(p-p) input signal amplitude before clipping occurs (peak-to-peak value) note 4 1.0 − − V ∆Vo difference between black level of internal and external signals at the outputs − − 20 mV I23-25 input currents note 2 − 0.1 1 µA ∆td delay difference for the three channels note 4 − 0 − ns FAST BLANKING (PIN 26) Vi V26(max) 1997 Jul 01 input voltage maximum input pulse no data insertion − − 0.3 V data insertion 0.9 − − V insertion − − 3.0 V 31 Philips Semiconductors Preliminary specification I2C-bus controlled economy PAL/NTSC and NTSC TV-processors SYMBOL PARAMETER ∆td(blank,RGB) delay difference of blanking and RGB signals tsw TDA837x family CONDITIONS MIN. TYP. MAX. UNIT − − 50 ns switching speed of blanking circuit − 10 − ns I26 input current − − 0.2 mA SSint suppression of internal RGB signals insertion; fi = 0 to 5 MHz; notes 4 and 22 − 55 − dB SSext suppression of external RGB signals no insertion; fi = 0 to 5 MHz; notes 4 and 22 − 55 − dB Vi input voltage to insert black level at the RGB outputs to facilitate ‘On Screen Display’ signals being applied to the outputs 4 − − V td(blank-RGB) delay between blanking input and RGB outputs − − 80 ns note 4 COLOUR DIFFERENCE INPUT SIGNALS (PINS 31 AND 32) V31(p-p) input signal amplitude (R − Y) (peak-to-peak value) note 2 − 1.05 − V V32(p-p) input signal amplitude (B − Y) (peak-to-peak value) note 2 − 1.35 − V I31,32 input current for both inputs note 2 − 0.1 1.0 µA − 1 − V − fosc − MHz − 2 − 20 − − dB − 4.3 − MHz MHz LUMINANCE INPUTS AND OUTPUTS (PINS 27 AND 28); note 25 V27,28 output signal amplitude (black-to-white) Chrominance filters CHROMINANCE TRAP CIRCUIT; note 26 ftrap trap frequency QF trap quality factor CSR colour subcarrier rejection ftrap(SECAM) trap frequency note 27 during SECAM reception CHROMINANCE BAND-PASS CIRCUIT fc centre frequency − 1.1fosc − Qbp band-pass quality factor − 3 − Luminance processing Y DELAY LINE td(Y) delay time note 4 − 480 − ns Bdel(int) bandwidth of internal delay line note 4 8 − − MHz at 50% of pulse; note 8 − 160 − ns PEAKING CONTROL; note 28 tW 1997 Jul 01 width of preshoot or overshoot 32 Philips Semiconductors Preliminary specification I2C-bus controlled economy PAL/NTSC and NTSC TV-processors SYMBOL PARAMETER Sc(th) peaking signal compression threshold OS overshoot at maximum peaking neg/pos CONDITIONS MIN. TYP. MAX. UNIT − 50 − IRE positive − 45 − % negative − 80 − % − 1.8 − ratio of negative and positive overshoots peaking control curve TDA837x family 16 steps see Fig.9 NOISE CORING STAGE S − 15 − IRE 15 21 27 IRE at 100% of peak white −1 0 +1 IRE at 50% of peak white −1 − +3 IRE at 15% of peak white 6 8 10 IRE note 2 50 300 350 mV coring range BLACK LEVEL STRETCHER; note 29 BLshift(max) maximum black level shift BLshift level shift Horizontal and vertical synchronization and drive circuits SYNC VIDEO INPUT (PINS 11, 13 AND 17) V11,13,17 sync pulse amplitude SLHS slicing level for horizontal sync note 30 − 50 − % SLVS slicing level for vertical sync note 30 − 30 − % HORIZONTAL OSCILLATOR ffr free running frequency − 15625 − Hz ∆ffr spread on free running frequency − − ±2 % ∆f/∆VP frequency variation with respect to the supply voltage VP = 8.0 V ±10%; note 4 − 0.2 0.5 % ∆f(max)(T) maximum frequency variation with temperature Tamb = 0 to 70 °C; note 4 − − 80 Hz − ±0.9 ±1.2 kHz ±0.6 ±0.9 − kHz FIRST CONTROL LOOP (FILTER CONNECTED TO PIN 43); note 31 fhr(PLL) holding range PLL fcr(PLL) catching range PLL S/N signal-to-noise ratio of the video input signal at which the time constant is switched − 20 − dB HYS hysteresis at the switching point − 1 − dB note 4 SECOND CONTROL LOOP (CAPACITOR CONNECTED TO PIN 42) ∆ϕi/∆ϕo control sensitivity − 150 − µs/µs tcr control range from start of horizontal output to flyback at nominal shift position 11 12 − µs tshift horizontal shift range ±2 − − µs 1997 Jul 01 63 steps 33 Philips Semiconductors Preliminary specification I2C-bus controlled economy PAL/NTSC and NTSC TV-processors SYMBOL PARAMETER ∆ϕ control sensitivity for dynamic phase compensation Vprot voltage to switch-on the flash protection Ii(prot) input current during protection TDA837x family CONDITIONS note 32 MIN. TYP. MAX. UNIT − 5.3 − µs/V 6 − − V − − 1 mA HORIZONTAL OUTPUT (PIN 40); note 33 VOL LOW level output voltage − − 0.3 V Io(max) maximum allowed output current 10 − − mA Vo(max) maximum allowed output voltage − − VP V δ duty factor note 4 − 50 − % Vo = HIGH − 75 − % Io = 10 mA fsw frequency during switch-on and switch-off − 2fH − Hz tsw switch-on time − 50 − ms maximum RGB drive − 100 − ms minimum RGB drive − 50 − ms 100 − 300 µA FLYBACK PULSE INPUT AND SANDCASTLE OUTPUT (PIN 41) Ii(fb) required input current during the note 4 flyback pulse V41 output voltage Vi(clamp) clamped input voltage during flyback tW pulse width td(bk-sync) during burst key 4.8 5.3 5.8 V during blanking 1.8 2.0 2.2 V 2.6 3.0 3.4 V burst key pulse 3.3 3.5 3.7 µs vertical blanking; note 34 − 14 − lines 5.2 5.4 5.6 µs delay of start of burst key to start of sync VERTICAL OSCILLATOR; TDA8373 AND TDA8377 OPERATING AT 60 HZ; note 35 ffr free running frequency − 50/60 − Hz flock frequency locking range 45 − 64.5 Hz divider value not locked − 625/525 − lines LR locking range 488 − 722 lines/ frame − 3.5 − V − 1 − mA VERTICAL RAMP GENERATOR (PINS 51 AND 52) V51(p-p) sawtooth amplitude (peak-to-peak value) Idch discharge current Ich charge current set by external resistor note 36 − 19 − µA Vslope vertical slope control range (63 steps) −20 − +20 % 1997 Jul 01 VS = 1FH; C = 100 nF; R = 39 kΩ 34 Philips Semiconductors Preliminary specification I2C-bus controlled economy PAL/NTSC and NTSC TV-processors SYMBOL PARAMETER ∆Ich charge current increase VrampL LOW voltage level of ramp in the normal or expand mode TDA837x family CONDITIONS f = 60 Hz MIN. TYP. MAX. UNIT − 20 − % − 2.07 − V − 0.95 − mA VERTICAL DRIVE OUTPUTS (PINS 46 AND 47) Io(dif)(p-p) differential output current (peak-to-peak value) VA = 1FH ICM common mode current − 400 − µA V46,47 output voltage range 0 − 4.0 V EHT TRACKING/OVERVOLTAGE PROTECTION (PIN 50) ∆V50 input voltage range 1.2 − 2.8 V mscan scan modulation range −5 − +5 % − 6.3 − %/V − −6.3 − %/V +100 − −100 µA − 3.9 − V − 0.5H − 100 − 65 % vsen vertical sensitivity EWsen E-W sensitivity Ieq E-W equivalent output current V50 overvoltage detection level when switched on note 32 DE-INTERLACE ffd first field delay E-W WIDTH (TDA8375A, TDA8377A, TDA8375 AND TDA8377); note 37 CR control range 63 steps Ieq equivalent E-W output current 0 − 700 µA VoEW E-W output voltage range 1.0 − 8.0 V IoEW E-W output current range 0 − 1200 µA E-W PARABOLA/WIDTH (TDA8375A, TDA8377A, TDA8375 AND TDA8377) CR control range 63 steps 0 − 22 % Ieq equivalent E-W output current E-W = 3FH 0 − 440 µA E-W CORNER/PARABOLA (TDA8375A, TDA8377A, TDA8375 AND TDA8377) CR control range 63 steps −43 − 0 % Ieq equivalent E-W output current PW = 3FH; E-W = 3FH −190 − 0 µA −5 − +5 % −100 − +100 µA E-W TRAPEZIUM (TDA8375A, TDA8377A, TDA8375 AND TDA8377) CR control range Ieq equivalent E-W output current 63 steps VERTICAL AMPLITUDE CR control range 63 steps; SC = 00H 80 − 120 % Ieq(dif)(p-p) equivalent differential vertical drive output current (peak-to-peak value) SC = 00H 760 − 1140 µA CR control range 63 steps −5 − +5 % Ieq(dif) equivalent differential vertical drive output current −50 − +50 µA VERTICAL SHIFT 1997 Jul 01 35 Philips Semiconductors Preliminary specification I2C-bus controlled economy PAL/NTSC and NTSC TV-processors SYMBOL PARAMETER TDA837x family CONDITIONS MIN. TYP. MAX. UNIT S-CORRECTION CR control range 63 steps 0 − 30 % 1.38 A VERTICAL EXPAND (ZOOM) MODE (TDA8375 AND TDA8377); note 38 Output current variation compared with nominal scan ∆Io vertical expand factor Io(lim) output current limiting and RGB blanking 0.75 1.08 A Colour demodulation part CHROMINANCE AMPLIFIER CRACC ACC control range 26 − − dB ∆VACC change in amplitude of the output signals over the ACC range − − 2 dB thon threshold colour killer ON −30 − − dB hysoff hysteresis colour killer OFF at strong signal conditions; − S/N ≥ 40 dB; note 4 +3 − dB − +1 − dB − 3.0 − ±360 ±600 − Hz note 39 at noisy input signals; note 4 ACL CIRCUIT; note 40 chrominance burst ratio at which the ACL starts to operate REFERENCE PART Phase-locked loop; note 41 fcr frequency catching range ∆ϕ phase shift for a ±400 Hz deviation of the oscillator frequency note 4 − − 2 deg TCosc temperature coefficient of the oscillator frequency note 4 − 2.0 2.5 Hz/K ∆fosc oscillator frequency deviation with respect to the supply VP = 8 V ±10%; note 4 − − 250 Hz Rneg(min) minimum negative resistance − − 1 kΩ CL(max) maximum load capacitance − − 15 pF ±35 ±40 − deg Oscillator HUE CONTROL CRhue hue control range 63 steps hue control curve 1997 Jul 01 see Fig.10 36 Philips Semiconductors Preliminary specification I2C-bus controlled economy PAL/NTSC and NTSC TV-processors SYMBOL PARAMETER TDA837x family CONDITIONS MIN. TYP. MAX. UNIT ∆hue hue variation for ±10% VP note 4 − 0 − deg ∆hue(T) hue variation with temperature Tamb = 0 to 70 °C; note 4 − 0 − deg DEMODULATORS (PINS 29 AND 30) V30(p-p) (R − Y) output signal amplitude (peak-to-peak value) TDA8374 and TDA8375; note 42 − 0.525 − V V29(p-p) (B − Y) output signal amplitude (peak-to-peak value) TDA8374 and TDA8375; note 42 − 0.675 − V G gain ratio between both demodulators G(B − Y) and G(R − Y) 1.60 1.78 1.96 ∆V spread of signal amplitude ratio PAL/NTSC TDA8374 and TDA8375; note 4 −1 − +1 dB Zo output impedance between (R − Y) and (B − Y) note 2 − 500 − Ω B bandwidth of demodulators −3 dB; note 43 − 650 − kHz V29,30(p-p) residual carrier output (peak-to-peak value) fc; (R − Y) output 5 mV − − 5 mV 5 mV fc; (B − Y) output 2fc; (R − Y) output 2fc; (B − Y) output − − 5 mV − − 25 mV note 4 − 0.1 − %/K change of output signal amplitude with supply voltage note 4 − − ±0.1 dB phase error in the demodulated signals note 4 − − ±5 deg V30(p-p) H/2 ripple at (R − Y) output (peak-to-peak value) ∆Vo(T) change of output signal amplitude with temperature ∆Vo/VP Eϕ COLOUR DIFFERENCE MATRICES (IN CONTROL CIRCUIT) TDA8374 AND TDA8375 PAL or (SECAM when TDA8395 is applied); (R − Y) and (B − Y) not affected (G − Y)/ (R − Y) ratio of demodulated signals − −0.51 ±10% − (G − Y)/ (B − Y) ratio of demodulated signals − −0.19 ±25% − NTSC mode; the colour-difference matrix results in the following signals (nominal hue setting) (B − Y) (B − Y) signal 2.03/0° 2.03UR (R − Y) (R − Y) signal 1.59/95° −0.14UR + 1.58VR (G − Y) (G − Y) signal 0.61/240° −0.31UR − 0.53VR 1997 Jul 01 37 Philips Semiconductors Preliminary specification I2C-bus controlled economy PAL/NTSC and NTSC TV-processors SYMBOL PARAMETER TDA837x family CONDITIONS MIN. TYP. MAX. UNIT COLOUR DIFFERENCE MATRICES (IN CONTROL CIRCUIT) TDA8373 AND TDA8377 MAT = 0; the colour-difference matrix results in the following signals (nominal hue setting) (B − Y) (B − Y) signal 2.03/0° 2.03UR (R − Y) (R − Y) signal 1.59/95° −0.14UR + 1.58VR (G − Y) (G − Y) signal 0.61/240° −0.31UR − 0.53VR MAT = 1; the colour-difference matrix results in the following signals (nominal hue setting) (B − Y) (B − Y) signal 1.14/−10° 1.12UR − 0.20VR (R − Y) (R − Y) signal 1.14/100° −0.20UR + 1.12VR (G − Y) (G − Y) signal 0.30/235° −0.17UR − 0.25VR REFERENCE SIGNAL OUTPUT (PIN 33); note 44 fref reference frequency − 3.58 or 4.43 − MHz V33(p-p) output signal amplitude (peak-to-peak value) 0.2 0.25 0.3 V PAL/NTSC identified − 1.5 − V no PAL/NTSC identified; SECAM (by TDA8395) identified − 5.0 − V 150 − − µA 63 steps 52 − − dB 63 steps − 15 − dB − − 0.5 dB − ±0.7 − V COMMUNICATION WITH THE TDA8395 (TDA8374 AND TDA8375 ONLY) Vo I31 output level required current to stop PAL/NTSC identification circuit during SECAM Control part SATURATION CONTROL; note 24 (SEE Fig.11) CRsat saturation control range CONTRAST CONTROL; note 24 (SEE Fig.12) CRcon contrast control range tracking between the three channels over a control range of 10 dB BRIGHTNESS CONTROL (SEE Fig.13) CRbri brightness control range 63 steps RGB OUTPUT SIGNALS (PINS 19 TO 21) V19-21(p-p) output signal amplitude at note 24 nominal luminance input signal, nominal contrast and white point adjustment (peak-to-peak value) 1.8 2.1 2.4 V Vo(max)(p-p) output signal at maximum white point setting (peak-to-peak value) − 3.0 − V 1997 Jul 01 38 Philips Semiconductors Preliminary specification I2C-bus controlled economy PAL/NTSC and NTSC TV-processors SYMBOL PARAMETER TDA837x family CONDITIONS MIN. TYP. MAX. UNIT − 2.6 − V maximum signal amplitude at maximum white point setting (peak-to-peak value) − 3.6 − V Vred(p-p) output signal amplitude for the ‘red’ channel at nominal settings for contrast and saturation control and no luminance signal to the input (R − Y, PAL) (peak-to-peak value) tbf 2.1 tbf V ∆Vblank difference between blanking level measuring pulse 0.7 0.8 0.9 V tW(blank) width of the video blanking pulse TDA8375, TDA8377, when the HBL bit is active TDA8375A and TDA8377A; note 46 14.4 14.7 15.0 µs Ibias internal bias current of NPN emitter follower output transistor − 1.5 − mA Io available output current − 5 − mA Zo output impedance − 150 − Ω CRbl control range of the black current stabilization at Vbl = 2.5 V and nominal − brightness and white-point adjustment (with respect to the measuring pulse) − ±1 V Vbl black level shift with picture content note 4 − − 20 mV Vo(4L) output voltage of the 4-L pulse after switch-on − 4.2 − V ∆bl(T) variation of black level with temperature note 4 − 1.0 − mV/K ∆bl relative variation in black level between the three channels during variations of note 4 VBW(max)(p-p) maximum signal amplitude (black-to-white) VWP(max)(p-p) note 45 supply voltage (±10%) nominal controls − − 20 mV saturation (50 dB) nominal contrast − − 20 mV contrast (15 dB) nominal saturation − − 20 mV brightness (±0.5 V) nominal controls − − 20 mV temperature (range 40 °C) S/N Vr(p-p) 1997 Jul 01 signal-to-noise ratio of the output signals residual voltage at the RGB outputs (peak-to-peak value) − − 20 mV RGB input; note 47 60 − − dB CVBS input; note 47 50 − − dB at fosc − − 15 mV at 2fosc plus higher harmonics in RGB outputs − − 15 mV 39 Philips Semiconductors Preliminary specification I2C-bus controlled economy PAL/NTSC and NTSC TV-processors SYMBOL PARAMETER TDA837x family CONDITIONS MIN. TYP. MAX. UNIT RGB input at −3 dB 8 − − MHz CVBS input at −3 dB; fosc = 3.6 MHz − 2.8 − MHz CVBS input at −3 dB; fosc = 4.44 MHz − 3.5 − MHz S-VHS input; at −3 dB 5 − − MHz I2C-bus setting for nominal gain HEX code − 20H − Ginc(max) maximum increase of the gain HEX code 3FH 40 50 60 % Gdec(max) maximum decrease of the gain HEX code 00H 35 45 55 % 10 − µA B bandwidth of output signals WHITE-POINT ADJUSTMENT BLACK CURRENT STABILIZATION (PIN 18); note 48 nominal white point setting − Ibias bias current for the picture tube cathode IL acceptable leakage current − ±100 − µA Iscan(max) maximum current during scan − 0.3 − mA Zi input impedance − 15 − kΩ BEAM CURRENT LIMITING/VERTICAL GUARD INPUT (PIN 22); note 49 VCR contrast reduction starting voltage − 3.1 − V VdifCR voltage difference for full contrast reduction − 2 − V VBR brightness reduction starting voltage − 1.6 − V VdifBR voltage difference for full brightness reduction − 1 − V Vbias internal bias voltage − 3.3 − V Zint internal impedance − 40 − kΩ Vdet detection level for vertical guard − 3.65 − V Ii(min) minimum input current to activate the guard circuit − 100 − µA Ii(max) maximum allowable input current − 1 − mA Notes 1. On set AGC. 2. This parameter is not tested during production and is just given as application information for the designer of the television receiver. 3. Loop bandwidth BL = 60 kHz (natural frequency fn = 15 kHz; damping factor d = 2; calculated with sync level as FPLL input signal level). LC-VCO circuit: Q0 ≥ 60, Cext = 12 pF, Cint = 20 pF. 4. This parameter is not tested during production but is guaranteed by the design and qualified by means of matrix batches which are made in the pilot production period. 5. Measured at 10 mV (RMS) top sync input signal. 6. So called projected zero point, i.e. with switched demodulator. 1997 Jul 01 40 Philips Semiconductors Preliminary specification I2C-bus controlled economy PAL/NTSC and NTSC TV-processors TDA837x family 7. Measured in accordance with the test line given in Fig.14. For the differential phase test the peak white setting is reduced to 87%. a) The differential gain is expressed as a percentage of the difference in peak amplitudes between the largest and smallest value relative to the subcarrier amplitude at blanking level. b) The phase difference is defined as the difference in degrees between the largest and smallest phase angle. 8. This figure is valid for the complete video signal amplitude (peak white-to-black), see Fig.15. 9. The noise inverter is only active in the ‘strong signal mode’ (no noise detected in the incoming signal). 10. The test set-up and input conditions are given in Fig.16. The figures are measured with an input signal of 10 mV (RMS). V O(b-w) 11. Measured with a source impedance of 75 Ω, where: S/N = 20 log --------------------------------------------------------V m ( rms ) ( B = 5 MHz ) 12. The AGC response time is also dependent on the acquisition time of the PLL demodulator. The values given are valid when the PLL is in lock. 13. The AFC control voltage is obtained from the control voltage of the VCO of the PLL demodulator. The tuning information is supplied to the tuning system via the I2C-bus. Two bits are reserved for this function. The AFC value is valid only when the SL bit = 1. 14. Vi = 100 mV (RMS), FM: 1 kHz, ∆f = ±50 kHz. 15. Vi = 50 mV (RMS), f = 4.5 to 5.5 MHz; FM: 70 Hz, ±50 kHz deviation; AM: 1 kHz, 30% modulation. 16. The Automatic Volume Levelling (AVL) circuit automatically stabilizes the audio output signal to a certain level which can be set by means of the volume control. This AVL function prevents big audio output fluctuations due to variation of the modulation depth of the transmitter. The AVL can be switched on and off via the I2C-bus. For the TDA8373 the AVL is active over an input voltage range (measured at the de-emphasis output) between 75 and 750 mV (RMS). For the TDA8374 this input level is dependent on the crystals which are connected to the colour decoder. When only 3.5 MHz crystals are connected (indicated via the XA/XB bits) the active input level is identical to that of the TDA8373. When a 4.4 MHz crystal is connected the input signal range is increased to 150 to 1500 mV (RMS), this to cope with the larger FM swing of European transmitters. The AVL control curve for the 2 standards is given in Fig.29 and Fig.30. The control range of +6 to −14 dB is valid for input signals with 50% of the maximum frequency deviation. 17. Vi = 100 mV (RMS), f = 5.5 MHz; FM: 1 kHz, ±17.5 kHz deviation, 15 kHz bandwidth; audio attenuator at −6 dB. 18. Vi = 100 mV (RMS), f = 4.5 to 5.5 MHz, FM: 1 kHz, ±100 kHz deviation. 19. Unweighted RMS value, Vi = 100 mV (RMS), FM: 1 kHz, ±50 kHz deviation, volume control: −6 dB. 20. Audio attenuator at −20 dB; temperature range = 10 to 50 °C. 21. Signal with negative-going sync. Amplitude includes sync pulse amplitude. 22. This parameter is measured at nominal settings of the various controls. 23. Indicated as a signal for a colour bar with 75% saturation (chroma-to-burst ratio = 2.2 : 1). 24. Nominal contrast is specified with the DAC in position 20H. Nominal saturation as maximum −10 dB. At nominal settings of brightness and white point the black level at the outputs is 300 mV lower than the level of the black current measuring pulses. 25. The luminance output and input of the TDA8375A, TDA8377A, TDA8375 and TDA8377 can be connected directly. When additional picture improvement ICs (such as the TDA9170) are applied the inputs of these ICs must be AC-coupled because of the black level clamp requirement. The output of the picture improvement ICs can be directly coupled to the luminance input as long as the DC level of the signal has a value between 1 and 7 V. To be able to apply CTI ICs such as the TDA4565 and TDA4566 the gain of the luminance channel can be increased via the setting of the GAI bit in the I2C-bus subaddress 03. 1997 Jul 01 41 Philips Semiconductors Preliminary specification I2C-bus controlled economy PAL/NTSC and NTSC TV-processors TDA837x family 26. When the colour decoder is forced to a fixed subcarrier frequency (via the XA/XB or the CM bits) the chroma trap is always switched on, also when no colour signal is identified. When 2 crystals are active the chroma trap is switched off when no colour signal is identified. 27. The −3 dB bandwidth of the circuit can be calculated using the following equation: 1 f –3 dB = f osc 1 – -------- 2Q 28. Valid for a signal amplitude on the Y input of 0.7 V (black-to-white) (100 IRE) with a rise time (10% to 90%) of 70 ns and the video switch in the Y/C mode. During production the peaking function is not tested by measuring the overshoots but by measuring the frequency response of the Y output. 29. For video signals with a black level which deviates from the back porch blanking level the signal is ‘stretched’ to the blanking level. The amount of correction depends on the IRE value of the signal (see Fig.17). The black level is detected by means of an external capacitor. The black level stretcher can be made inoperative by connecting the pin to ground. The values given are valid only when the luminance input signal has an amplitude of 1 V (p-p). 30. The slicing level is independent of sync pulse amplitude. The given percentage is the distance between the slicing level and the black level (back porch). When the amplitude of the sync pulse exceeds the value of 350 mV the sync separator will slice the sync pulse at a level of 175 mV above top sync. The maximum sync pulse amplitude is 4 V (p-p). 31. To obtain a good performance for both weak signal and VCR playback the time constant of the first control loop is switched depending on the input signal condition and the condition of the bus. Therefore the circuit contains a noise detector and the time constant is switched to ‘slow’ when too much noise is present in the signal. In the ‘fast’ mode, during the vertical retrace time, the phase detector current is increased by 50% so that phase errors due to the head switching of the VCR are corrected as soon as possible. Switching between the two modes can be made automatically or overruled by the bus (see Tables 4, 6, 8 and 10). The circuit contains a video identification circuit which is independent of first loop. This identification circuit can be used to close or open the first control loop when a video signal is present or not on the input. This ensures a stable On-Screen-Display (OSD) when just noise is present at the input. The coupling of the video identification circuit with the first loop can be overruled via the I2C-bus. The coupling between the phase 1 detector and the video identification circuit is only active for ‘internal’ CVBS signals. To prevent the horizontal synchronization being disturbed by anti-copy guard signals, such as Macrovision, the phase detector is gated during the vertical retrace period so that pulses during scan have no effect on the output voltage. The width of the gate pulse is approximately 22 µs. Furthermore the phase detector is gated during the lower part of the picture (pulse width = 12 µs) to prevent disturbances due to overmodulated subtitles. The latter gating is active only with standard signals (number of lines per frame 625 or 525). During weak signal conditions (noise detector active) the gating is active during the complete scan period and the width of the gate pulse is reduced to 5.7 µs so that the effect of the noise is reduced to a minimum. The output current of the phase detector in the various conditions are given in Table 57. 32. The ICs have 2 protection inputs. The protection at pin 42 is intended to be used as ‘flash’ protection. When this protection is activated the horizontal drive is switched off immediately and then switched on again via the slow start procedure. The protection on pin 50 is intended for overvoltage (X-ray) protection. When this protection is activated the horizontal drive can be switched off directly (via the slow stop procedure). It is also possible to continue the horizontal drive and to set the protection bit (XPR) in the output bytes of the I2C-bus. The choice between the 2 modes of operation is made with the PRD bit. 1997 Jul 01 42 Philips Semiconductors Preliminary specification I2C-bus controlled economy PAL/NTSC and NTSC TV-processors TDA837x family 33. During switch-on the horizontal output starts with twice the frequency and with a duty cycle of 75% (Vo = HIGH). After approximately 50 ms the frequency is changed to the normal value. Because of the high frequency the peak currents in the horizontal output transistor are limited. Also during switch-off the frequency is switched to twice the value and the RGB drive is set to maximum so that the EHT capacitor is discharged. This switching to maximum drive occurs only when RBL = 0, for RBL = 1 the drive voltage remains minimum during switch-off. After approximately 100 ms the RGB drive is set to minimum and 50 ms later the horizontal drive is switched off. The horizontal output is gated with the flyback pulse so that the horizontal output transistor cannot be switched on during the flyback time. 34. The vertical blanking pulse in the RGB outputs has a width of 26 or 21 lines (50 or 60 Hz system). The width of the vertical sync pulse in the sandcastle pulse has a width of 14 lines. This to prevent a phase distortion on top of the picture due to timing modulation of the incoming flyback pulse. 35. The timing pulses for the vertical ramp generator are obtained from the horizontal oscillator via a divider circuit. This divider circuit has 3 modes of operation. A brief explanation is given below. For the TDA8373 and TDA8377 only the 60 Hz figures are valid. a) Search mode ‘large window’: This mode is switched on when the circuit is not synchronized or when a non-standard signal (number of lines per frame in the 50 Hz mode is between 311 and 314 and in the 60 Hz mode between 261 and 264) is received. In the search mode the divider can be triggered between line 244 and line 361 (approximately 45 to 64.5 Hz). b) Standard mode ‘narrow window’: This mode is switched on when more than 15 succeeding vertical sync pulses are detected in the narrow window. When the circuit is in the standard mode and a vertical sync pulse is missing the retrace of the vertical ramp generator is started at the end of the window. Consequently, the disturbance of the picture is very small. The circuit will switch back to the search window when, for 6 successive vertical periods, no sync pulses are found within the window. c) Standard TV-norm (divider ratio 525 (60 Hz) or 625 (50 Hz): When the system is switched to the narrow window it is checked whether the incoming vertical sync pulses are in accordance with the TV-norm. When 15 standard TV-norm pulses are counted the divider system is switched to the standard divider ratio mode. In this mode the divider is always reset at the standard value even if the vertical sync pulse is missing. When 3 vertical sync pulses are missed the system switches back to the narrow window and when also in this window no sync pulses are found (condition 3 missing pulses) the system switches over to the search window. The vertical divider needs some waiting time during channel-switching of the tuner. When a fast reaction of the divider is required during channel-switching the system can be forced to the search window by means of the NCIN bit in subaddress 08. 36. Conditions: frequency is 60 Hz; normal mode; VS = 1F. 37. The output range percentages mentioned for E-W control parameters are based on the assumption that 400 µA variation in E-W output current is equivalent to 20% variation in picture width. Because of the horizontal and vertical zoom feature in the TDA8375 and TDA8377 (see also note 38) the E-W width control range is increased compared with previous ICs such as the TDA8366. The increased E-W width control is also available in the TDA8375A and TDA8377A although these devices do not have the vertical zoom feature. 38. The TDA8375 and TDA8377 have a zoom adjustment possibility for the vertical and horizontal deflection. For this reason an extra DAC has been added in the vertical amplitude control which controls the vertical scan amplitude between 0.75 and 1.38 of the nominal scan. At an amplitude of 1.08 of the nominal scan the output current is limited and the blanking of the RGB outputs is activated (see Fig.28). In addition to the variation of the vertical amplitude the vertical slope control range is also increased. This gives the possibility to vary the position of the bottom part of the picture independent from the upper part. The nominal scan height must be adjusted at a position of 19H of the vertical ‘zoom’ DAC 1997 Jul 01 43 Philips Semiconductors Preliminary specification I2C-bus controlled economy PAL/NTSC and NTSC TV-processors TDA837x family 39. At a chrominance input voltage of 660 mV (p-p) [colour bar with 75% saturation i.e. burst signal amplitude 300 mV (p-p)] the dynamic range of the ACC is +6 and −20 dB. 40. The ACL function is available in the NTSC devices and is active in the PAL/NTSC devices when NTSC signals are received. The ACL circuit reduces the gain of the chroma amplifier for input signals with a chroma-to-burst ratio which exceeds a value of 3.0. 41. All frequency variations are referenced to 3.58 or 4.43 MHz carrier frequency. All oscillator specifications are measured with the Philips crystal series 9922 520 with a series capacitor of 18 pF. The oscillator circuit is rather insensitive to the spurious responses of the crystal. As long as the resonance resistance of the 3rd overtone is higher than that of the fundamental frequency the oscillator will operate at the correct frequency. Typical parameters for the above mentioned crystals are as follows: a) Load resonance frequency f0 = 4.433619 or 3.579545 MHz (CL = 20 pF). b) Motional capacitance Cmot = 20.6 fF (4.43 MHz crystal) or 14.7 fF (3.58 MHz crystal). c) Parallel capacitance Cpar = 5 pF for both crystals. The minimum detuning range can only be specified if both the IC and the crystal tolerances are known and the figures given are therefore valid for the specified crystal series. In this figure tolerances of the crystal with respect to nominal frequency, motional capacitance and ageing have been taken into account and have been counted for gaussian addition. Whenever different typical crystal parameters are used the following equation might be helpful for calculating the impact on the detuning capabilities: C mot The detuning range divided by ------------------------------2 C par 1 + ---------- CL The resulting detuning range should be corrected for temperature shift and supply deviation of both the IC and the crystal. The actual series capacitance in the application should be CL = 18 pF to account for parasitic capacitances on and off chip. For 3-norma applications with 2 crystals connected to one pin the maximum parasitic capacitance of the crystal pin should not exceed 15 pF. 42. The (R − Y) and (B − Y) signals are demodulated with a phase difference of the reference carrier of 90° and a gain ( B – Y) ratio --------------------- = 1.78. ( R – Y) The output signal amplitudes of the TDA8373 and TDA8377A have twice the value. This is necessary to compensate for the gain of the baseband delay line (TDA4665). The matrixing to the required signals is realized in the control part. 43. This parameter indicates the bandwidth of the complete chrominance circuit including the chrominance band-pass filter. The bandwidth of the low-pass filter of the demodulator is approximately 1 MHz. 44. The sub-carrier output signal can be used as reference signal of external comb filter ICs (all ICs) and as a reference signal for the SECAM decoder TDA8395 (only TDA8374 and TDA8375). In the latter types the output signal is continuously available when PAL or NTSC signals are detected. When the system identifies a SECAM signal the reference signal is only present in the vertical retrace period. This to prevent interference between the reference signal and the SECAM input signal. For comb filter applications the DC load on this pin should be limited to 50 µA to avoid problems with SECAM identification. 45. At nominal setting of the gain control. When this amplitude is exceeded the signal will be clipped. 46. When the reproduction of 4 : 3 pictures on a 16 : 9 picture tube is realized by means of a reduction of the horizontal scan amplitude, the edges of the picture may be slightly disturbed. This effect can be prevented by adding additional blanking to the RGB signals. This blanking pulse is derived from the horizontal oscillator and is directly related to the incoming video signal (independent of the flyback pulse). The additional blanking overlaps the normal blanking signal with approximately 1 µs on both sides. This blanking is activated with the HBL bit (only in the TDA8375 and TDA8377). 47. Signal-to-noise ratio (S/N) is specified as a peak-to-peak signal with respect to RMS noise (bandwidth 5 MHz). 1997 Jul 01 44 Philips Semiconductors Preliminary specification I2C-bus controlled economy PAL/NTSC and NTSC TV-processors TDA837x family 48. This is a current input. The indicated value of the nominal bias current is obtained at the nominal setting of the gain (white point) control. The actual value of the bias current depends on the gain control setting of each channel. As a result the ‘black current’ of each gun is adapted to the white point setting so that the background colour will follow the white point adjustment. 49. The beam current limiting and the vertical guard function have been combined on this pin. The beam current limiting function is active during the vertical scan period. Table 57 Output current of the phase detector in the various conditions I2C-BUS COMMANDS ϕ-1 CURRENT/MODE IC CONDITIONS VID POC FOA FOB IDENT COIN NOISE SCAN V-RETR GATING MODE − 0 0 0 yes yes no 180 270 yes(1) auto − 0 0 0 yes yes yes 30 30 yes auto − 0 0 0 yes no − 180 270 no auto − 0 0 1 yes yes − 30 30 yes slow − 0 0 1 yes no − 180 270 no slow − 0 1 0 yes yes no 180 270 yes fast − 0 1 0 yes yes yes 30 30 yes slow − − 1 1 − − − 180 270 no fast 0 0 − − no − − 6 6 no OSD − 1 − − − − − − − − off Note 1. During vertical retrace the width is 22 µs and during the lower part of the picture 12 µs. In the other conditions the width is 5.7 µs and the gating is continuous. MGK290 handbook, halfpage MGK291 handbook, halfpage 0 40 (dB) (%) −20 30 −40 20 −60 10 −80 −100 0 0 10 20 30 DAC (HEX) 0 40 4 8 C F 10 DAC (HEX) Positive overshoot. Fig.8 Volume control curve. 1997 Jul 01 Fig.9 Peaking control curve. 45 Philips Semiconductors Preliminary specification I2C-bus controlled economy PAL/NTSC and NTSC TV-processors MGK292 handbook, halfpage TDA837x family MGK293 handbook, halfpage (deg) 300 (%) 250 40 20 200 0 150 −20 100 50 −40 0 0 10 20 30 DAC (HEX) 40 0 Fig.10 Hue control curve. 20 30 DAC (HEX) 40 Fig.11 Saturation control curve. MGK294 handbook, halfpage 10 MGK295 handbook, halfpage 0.7 100 (%) (V) 80 0.35 60 0 40 −0.35 20 −0.7 0 0 10 20 30 DAC (HEX) 40 0 10 20 30 DAC (HEX) 40 Relative variation with respect to the measuring pulse. Fig.12 Contrast control curve. 1997 Jul 01 Fig.13 Brightness control curve. 46 Philips Semiconductors Preliminary specification I2C-bus controlled economy PAL/NTSC and NTSC TV-processors TDA837x family MBC212 100% 92% 16 % 30% for negative modulation 100% = 10% rest carrier Fig.14 Video output signal. handbook, full pagewidth MBC211 100% 86% 72% 58% 44% 30% 10 12 22 26 32 36 40 44 48 52 Fig.15 Test signal waveform. 1997 Jul 01 47 56 60 64 µs Philips Semiconductors Preliminary specification I2C-bus controlled economy PAL/NTSC and NTSC TV-processors TDA837x family 3.2 dB handbook, full pagewidth 10 dB 13.2 dB 13.2 dB 30 dB 30 dB SC CC PC SC CC PC MBC213 BLUE YELLOW PC SC Σ ATTENUATOR TEST CIRCUIT SPECTRUM ANALYZER gain setting adjusted for blue CC MBC210 Input signal conditions: SC = Sound Carrier; CC = Colour Carrier; PC = Picture Carrier. All amplitudes with respect to top sync level. V O at 3.58 or 4.4 MHz Value at 0.92 or 1.1 MHz = 20 log ------------------------------------------------------------ + 3.6 dB V O at 0.92 or 1.1 MHz V O at 3.58 or 4.4 MHz Value at 2.66 or 3.3 MHz = 20 log -----------------------------------------------------------V O at 2.66 or 3.3 MHz Fig.16 Test set-up intermodulation. 1997 Jul 01 48 Philips Semiconductors Preliminary specification I2C-bus controlled economy PAL/NTSC and NTSC TV-processors TDA837x family MGK297 100 handbook, halfpage out (IRE) 80 60 40 20 B 0 −20 A B A 0 20 40 60 80 100 in (IRE) A-A = maximum black level shift; B-B = level shift at 15% of peak white. Fig.17 Input/output relationship of the black level stretcher. TEST AND APPLICATION INFORMATION handbook, full pagewidth BANDPASS from tuner SAW FILTER 58 4 3 16 10 35 36 37 38 11 27 17 18 33 32 59 31 TRAP 30 24 TDA837x 34 62 29 63 21 20 64 54 50 46 45 51 4.4 MHz 39 47 48 57 56 3.5 MHz TDA8395 TDA4665 MGK302 Fig.18 Simplified application diagram. 1997 Jul 01 49 Philips Semiconductors Preliminary specification I2C-bus controlled economy PAL/NTSC and NTSC TV-processors TDA837x family East-West output stage In order to obtain correct tracking of the vertical and horizontal EHT correction, the E-W output stage should be dimensioned as illustrated in Fig.19. Resistor Rew determines the gain of the E-W output stage. Resistor Rc determines the reference current for both the vertical sawtooth generator and the geometry processor. The preferred value of Rc is 39 kΩ which results in a reference current of 100 µA (Vref = 3.9 V). V scan The value of Rew must be: R ew = R c × ----------------------18 × V ref Example: With Vref = 3.9 V; Rc = 39 kΩ and Vscan = 120 V then Rew ≈ 68 kΩ. Vsupply handbook, full pagewidth Rew TDA8375 TDA8377 45 52 Rc 39 kΩ (2%) Vref E-W drive 51 Csaw 100 nF (5%) HORIZONTAL DEFLECTION STAGE Vscan DIODE MODULATOR VEW E-W OUTPUT STAGE MGK300 Fig.19 East-West output stage. Control ranges of geometry control parameters Typical case curves; Rc = 39 kΩ, CSAW = 100 nF. Figures 20 to 23 are valid for all types. Figures 24 to 27 are valid for TDA8375 and TDA8377. 1997 Jul 01 50 Philips Semiconductors Preliminary specification I2C-bus controlled economy PAL/NTSC and NTSC TV-processors TDA837x family MGH367 MGH366 (µA) 400 500 vert (µA) 300 200 100 0 −100 −200 −300 −400 −500 600 Ivert handbook, halfpage I handbook, halfpage −600 0 1/2 t −700 0 t time VA = 0, 31H and 63H; VSH = 31H; SC = 0. 1/2 t VS = 0, 31H and 63H; VA = 31H; VHS = 31H; SC = 0. Fig.20 Control range of vertical amplitude. Fig.21 Control range of vertical slope. MGH368 600 vert (µA) 400 handbook, halfpage I 200 200 0 0 −200 −200 −400 −400 0 1/2 t −600 time t 0 1/2 t time SC = 0, 31H and 63H; VA = 31H; VHS = 31H. Picture height does not change with S-correction for nominal vertical amplitude (VA = 31). VSH = 0, 31H and 63H; VA = 31H; SC = 0. Fig.22 Control range of vertical shift. 1997 Jul 01 MGH369 600 vert (µA) 400 handbook, halfpage I −600 t time Fig.23 Control range of S-correction. 51 t Philips Semiconductors Preliminary specification I2C-bus controlled economy PAL/NTSC and NTSC TV-processors MBK039 1200 ew (µA) 1000 TDA837x family MBK040 900 ew (µA) 800 handbook, halfpage I handbook, halfpage I 800 700 600 600 400 500 200 400 300 0 1/2 t 0 t time 0 EW = 0, 31H and 63H; PW = 31H; CP = 31H. 1/2 t t time PW = 0, 31H and 63H; EW = 31H; CP = 31H. Fig.24 Control range of E-W width. Fig.25 Control range of E-W parabola/width ratio. MBK041 MBK042 700 900 ew (µA) 800 handbook, halfpage handbook, halfpage I Iew (µA) 600 700 500 600 500 400 400 300 300 0 1/2 t time 0 t 1/2 t time t CP = 0, 31H and 63H; EW = 31H; PW = 63H. TC = 0, 31H and 63H; EW = 31H; PW = 31H; CP = 0. Fig.26 Control range of E-W corner/parabola ratio. Fig.27 Control range of E-W trapezium correction. 1997 Jul 01 52 Philips Semiconductors Preliminary specification I2C-bus controlled economy PAL/NTSC and NTSC TV-processors shift alignment depends on the expected off-sets in vertical output stage and picture tube, on the required value of the S-correction and on the demands upon vertical linearity. Adjustment of geometry control parameters The deflection processor of the TDA8373 and TDA8374 offers 5 control parameters for picture alignment: For adjustment of the vertical shift and vertical slope independent of each other, a special service blanking mode can be entered by setting the SBL bit HIGH. In this mode the RGB outputs are blanked during the second half of the picture. There are 2 different methods for alignment of the picture in vertical direction. Both methods make use of the service blanking mode. • Vertical picture alignment – S-correction – vertical amplitude – vertical slope – vertical shift – Horizontal shift alignment. The first method is recommended for picture tubes that have a marking for the middle of the screen. With the vertical shift control the last line of the visible picture is positioned exactly in the middle of the screen. After this adjustment the vertical shift should not be changed. The top of the picture is placed by adjusting the vertical amplitude and the bottom by adjusting the vertical slope. The TDA8375, TDA8377, TDA8375A and TDA8377A offer in addition the following functions for horizontal alignment: • E-W width • E-W parabola/width • E-W corner/parabola • E-W trapezium correction. The second method is recommended for picture tubes that have no marking for the middle of the screen. For this method a video signal is required in which the middle of the picture is indicated (e.g. the white line in the circle test pattern). With the vertical slope control the beginning of the blanking is positioned exactly on the middle of the picture. Then the top and bottom of the picture are placed symmetrically with respect to the middle of the screen by adjustment of the vertical amplitude and vertical shift. After this adjustment the vertical shift has the correct setting and should not be changed. It is important to notice that the ICs are designed for use with a DC-coupled vertical deflection stage. This is the reason why a vertical linearity alignment is not necessary (and, therefore, not available). For a particular combination of picture tube type and vertical output stage and E-W output stage, it is determined which are the required values for the settings of S-correction. These parameters can be preset via the I2C-bus and do not need any additional adjustment. The remainder of the parameters are preset with the mid-value of their control range (i.e. 1FH), or with the values obtained by previous TV set adjustments. If the vertical shift alignment is not required VSH should be set to its mid-value (i.e. VSH = 1FH). The top of the picture is then placed by adjusting the vertical amplitude and the bottom by adjusting the vertical slope. After the vertical picture alignment the picture is positioned in the horizontal direction by adjusting the horizontal shift. The vertical shift control is intended for compensation of off-sets in the external vertical output stage or in the picture tube. It can be shown that without compensation these off-sets will result in a certain linearity error, especially with picture tubes that need large S-correction. The total linearity error is in 1st order approximation proportional to the value of the off-set and to the square of the S-correction needed. The necessity to use the vertical 1997 Jul 01 TDA837x family To obtain the full range of the vertical zoom function with the TDA8375 and TDA8377 the adjustment of the vertical geometry should be carried out at a nominal setting of the zoom DAC at position 19H. 53 Philips Semiconductors Preliminary specification I2C-bus controlled economy PAL/NTSC and NTSC TV-processors handbook, full pagewidth 70 vertical position (%) TDA837x family MGK296 top picture 60 50 138% 40 100% 30 20 75% 10 t 1/2 t 0 time −10 −20 −30 −40 −50 bottom picture −60 blanking for exponential 138% Fig.28 Sawtooth waveform and blanking pulse of the TDA8375 and TDA8377. MGK298 104 handbook, halfpage AVL on AVL off audio output (mV) (RMS) 14 dB 103 25 kHz (norm) 6 dB A 102 10 B 102 C D 103 de-emphasis (mV) (RMS) 104 See Table 58. Fig.29 AVL characteristics of the TDA8373 and TDA8374 for 3.5 MHz standard. 1997 Jul 01 54 Philips Semiconductors Preliminary specification I2C-bus controlled economy PAL/NTSC and NTSC TV-processors TDA837x family MGK299 104 handbook, halfpage AVL on AVL off audio output (mV) (RMS) 14 dB 103 50 kHz (norm) 6 dB A 102 10 102 BC D E 103 de-emphasis (mV) (RMS) 104 See Table 59. Fig.30 AVL characteristics of the TDA8374 for 4.4 MHz standard. Table 58 Explanation to Fig.29 A B C D DESCRIPTION 50 100 250 500 de-emphasis pin 55 [mV (RMS)] 5 10 25 50 FM swing (kHz) 50 100 250 500 AVL input [mV (RMS)] 100 200 500 1000 external input [mV (RMS)] Table 59 Explanation to Fig.30 A B C D DESCRIPTION 100 200 250 1000 de-emphasis pin 55 [mV (RMS)] 10 20 25 100 FM swing (kHz) 50 100 125 500 AVL input [mV (RMS)] 100 200 250 1000 external input [mV (RMS)] 1997 Jul 01 55 Philips Semiconductors Preliminary specification I2C-bus controlled economy PAL/NTSC and NTSC TV-processors TDA837x family INTERNAL PIN CONFIGURATION sound limiter plus demodulator TSTCON 1 300 Ω 2.2 kΩ + 10 pF sound switch plus amplifier 100 Ω 15 pF 15 kΩ 25 kΩ 2 15 kΩ 4V MGK304 MGK303 Fig.32 Pin 2. Fig.31 Pin 1. 3 + 4 + + + 5 6 kΩ 6 kΩ MGK305 Fig.33 Pins 3, 4 and 5. + + 200 Ω 5V 7 300 Ω 6 MGK343 MGK306 Fig.34 Pin 6. 1997 Jul 01 Fig.35 Pin 7. 56 Philips Semiconductors Preliminary specification I2C-bus controlled economy PAL/NTSC and NTSC TV-processors TDA837x family 5V + + 300 Ω 8 9 30 Ω MGK307 MGK308 Fig.36 Pin 8. TSTCON 10 300 Ω Fig.37 Pin 9. + + 100 kΩ 10 pF 100 Ω 30 kΩ 100 kΩ Vref TXT DECODER PIP MGK309 decoder switch chroma output switch control decoder sync luma MGK310 Fig.38 Pin 10. Fig.39 Pins 11, 13 and 17. + + 12, 37 14 analog supply MGK344 GND1 MGK333 Fig.40 Pins 12 and 37. 1997 Jul 01 DUMMY CLAMP 11, 13, 17 Fig.41 Pin 14. 57 Philips Semiconductors Preliminary specification I2C-bus controlled economy PAL/NTSC and NTSC TV-processors TDA837x family + 2 kΩ + −100 µA/ +100 µA filter tuning + sound amplifier 300 Ω 50 kΩ 16 300 Ω 15 10 pF 100 µA MGK313 MGK312 Fig.42 Pin 15. Fig.43 Pin 16. + V/I + 10 pF IL 14 kΩ + Vref = 4 V 18 200 µA 10 µA 100 Ω 19, 20, 21 2 mA MGK315 MGK314 Fig.44 Pin 18. Fig.45 Pins 19, 20 and 21. + Vref1 + vertical guard 1 kΩ contrast control 4V + 40 kΩ Vref2 22 peak white limiting brightness control 200 µA MGK316 Fig.46 Pin 22. 1997 Jul 01 58 Philips Semiconductors Preliminary specification I2C-bus controlled economy PAL/NTSC and NTSC TV-processors TDA837x family + + + + insertion + + + 6V 300 Ω 300 Ω 26 23, 24, 25 4V 50 µA blanking MGK317 MGK318 Fig.47 Pins 23, 24 and 25. + + Fig.48 Pin 26. + + + 500 Ω 6V 50 pF + 10 Ω 27 10 Ω 28 500 µA 0.2 µA MGK320 MGK319 Fig.49 Pin 27. Fig.50 Pin 28. + + + + 31, 32 100 Ω + 100 Ω 2.5 V 29, 30 MGK322 MGK321 Fig.51 Pins 29 and 30. 1997 Jul 01 Fig.52 Pins 31 and 32. 59 Philips Semiconductors Preliminary specification I2C-bus controlled economy PAL/NTSC and NTSC TV-processors TDA837x family + + + + 34, 35 R 30 Ω 33 250 µA 3.7 V 2.7 V R MGK323 MGK324 Fig.53 Pin 33. pin 34: crystal = 3.58 MHz; R = 1 kΩ pin 35: crystal = 4.43 MHz; R = 1 kΩ Fig.54 Pins 34 and 35. + + 36 + + 400 Ω 100 Ω + TSTCON 38 100 Ω 600 µA 3.8 V MGK326 MGK325 Fig.55 Pin 36. Fig.56 Pin 38. + 39 + 30 Ω 40 protection MGK327 Fig.57 Pin 39. 1997 Jul 01 Fig.58 Pin 40. 60 MGK328 Philips Semiconductors Preliminary specification I2C-bus controlled economy PAL/NTSC and NTSC TV-processors TDA837x family + + J 5.3 V burstkey 3V + 30 Ω 2.9 V 41 V blank 2 µA burstkey MGK329 Fig.59 Pin 41. + + + 5.3 V flash level 300 Ω 42 MGK330 Fig.60 Pin 42. + + J 300 Ω 300 Ω 43 4V 3.3 V 4.7 V dF HOSC 4V MGK331 (NC plus POR) Fig.61 Pin 43. 1997 Jul 01 61 Philips Semiconductors Preliminary specification I2C-bus controlled economy PAL/NTSC and NTSC TV-processors TDA837x family + 45 GND2, connected to substrate 44 600 Ω MGK311 MGK332 Fig.62 Pin 44. Fig.63 Pin 45. + + + 100 Ω 48 + 1 kΩ + 46, 47 2.4 pF to IF amplifier 1 kΩ 100 Ω 49 MGK334 MGK335 Fig.64 Pins 46 and 47. Fig.65 Pins 48 and 49. + + J + J 300 Ω + 50 3.9 V 51 XPR 2V MGK336 J MGK337 Fig.66 Pin 50. 1997 Jul 01 Fig.67 Pin 51. 62 Philips Semiconductors Preliminary specification I2C-bus controlled economy PAL/NTSC and NTSC TV-processors TDA837x family Iref + 52 Vref MGK338 Fig.68 Pin 52. + 1.5 mA AGC det LSPEED NEGMOD + + 53 gating 50 µA 500 nA clamp 600 µA MGK339 Fig.69 Pin 53. + + 55 sound switch plus amplifier sound demodulator TSTCON 54 20 kΩ MGK340 3V MGK341 Fig.70 Pin 54. 1997 Jul 01 Fig.71 Pin 55. 63 Philips Semiconductors Preliminary specification I2C-bus controlled economy PAL/NTSC and NTSC TV-processors TDA837x family + 100 µA 56 DC stabilisation −50/50 µA MGK342 Fig.72 Pin 56. 1997 Jul 01 64 Philips Semiconductors Preliminary specification I2C-bus controlled economy PAL/NTSC and NTSC TV-processors TDA837x family PACKAGE OUTLINES QFP64: plastic quad flat package; 64 leads (lead length 1.95 mm); body 14 x 20 x 2.7 mm; high stand-off height SOT319-1 c y X 51 A 33 52 32 ZE Q e E HE A A2 (A 3) A1 θ wM Lp pin 1 index bp L 20 64 detail X 19 1 w M bp e ZD v M A D B HD v M B 0 5 10 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (1) e HD HE L Lp Q v w y mm 3.3 0.36 0.10 2.87 2.57 0.25 0.50 0.35 0.25 0.13 20.1 19.9 14.1 13.9 1 24.2 23.6 18.2 17.6 1.95 1.0 0.6 1.43 1.23 0.2 0.2 0.1 Z D (1) Z E (1) 1.2 0.8 1.2 0.8 θ Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION REFERENCES IEC JEDEC EIAJ ISSUE DATE 92-11-17 95-02-04 SOT319-1 1997 Jul 01 EUROPEAN PROJECTION 65 o 7 0o Philips Semiconductors Preliminary specification I2C-bus controlled economy PAL/NTSC and NTSC TV-processors TDA837x family seating plane SDIP56: plastic shrink dual in-line package; 56 leads (600 mil) SOT400-1 ME D A2 A L A1 c e Z b1 (e 1) w M MH b 29 56 pin 1 index E 1 28 0 5 10 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max. A1 min. A2 max. b b1 c D (1) E (1) e e1 L ME MH w Z (1) max. mm 5.08 0.51 4.0 1.3 0.8 0.53 0.40 0.32 0.23 52.4 51.6 14.0 13.6 1.778 15.24 3.2 2.8 15.80 15.24 17.15 15.90 0.18 2.3 Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION REFERENCES IEC JEDEC EIAJ ISSUE DATE 95-12-06 SOT400-1 1997 Jul 01 EUROPEAN PROJECTION 66 Philips Semiconductors Preliminary specification I2C-bus controlled economy PAL/NTSC and NTSC TV-processors TDA837x family Reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. SOLDERING Introduction There is no soldering method that is ideal for all IC packages. Wave soldering is often preferred when through-hole and surface mounted components are mixed on one printed-circuit board. However, wave soldering is not always suitable for surface mounted ICs, or for printed-circuits with high population densities. In these situations reflow soldering is often used. Several techniques exist for reflowing; for example, thermal conduction by heated belt. Dwell times vary from 50 to 300 seconds depending on heating method. Typical reflow temperatures range from 215 to 250 °C. Preheating is necessary to dry the paste and evaporate the binding agent. Preheat for 45 minutes at 45 °C. This text gives a very brief insight to a complex technology. A more in-depth account of soldering ICs can be found in our “IC Package Databook” (order code 9398 652 90011). WAVE SOLDERING Wave soldering is not recommended for QFP packages. This is because of the likelihood of solder bridging due to closely-spaced leads and the possibility of incomplete solder penetration in multi-lead devices. SDIP SOLDERING BY DIPPING OR BY WAVE The maximum permissible temperature of the solder is 260 °C; solder at this temperature must not be in contact with the joint for more than 5 seconds. The total contact time of successive solder waves must not exceed 5 seconds. If wave soldering cannot be avoided, the following conditions must be observed: The device may be mounted up to the seating plane, but the temperature of the plastic body must not exceed the specified maximum storage temperature (Tstg max). If the printed-circuit board has been pre-heated, forced cooling may be necessary immediately after soldering to keep the temperature within the permissible limit. • The footprint must be at an angle of 45° to the board direction and must incorporate solder thieves downstream and at the side corners. • A double-wave (a turbulent wave with high upward pressure followed by a smooth laminar wave) soldering technique should be used. Even with these conditions, do not consider wave soldering the following packages: QFP52 (SOT379-1), QFP100 (SOT317-1), QFP100 (SOT317-2), QFP100 (SOT382-1) or QFP160 (SOT322-1). REPAIRING SOLDERED JOINTS During placement and before soldering, the package must be fixed with a droplet of adhesive. The adhesive can be applied by screen printing, pin transfer or syringe dispensing. The package can be soldered after the adhesive is cured. Maximum permissible solder temperature is 260 °C, and maximum duration of package immersion in solder is 10 seconds, if cooled to less than 150 °C within 6 seconds. Typical dwell time is 4 seconds at 250 °C. Apply a low voltage soldering iron (less than 24 V) to the lead(s) of the package, below the seating plane or not more than 2 mm above it. If the temperature of the soldering iron bit is less than 300 °C it may remain in contact for up to 10 seconds. If the bit temperature is between 300 and 400 °C, contact may be up to 5 seconds. QFP REFLOW SOLDERING A mildly-activated flux will eliminate the need for removal of corrosive residues in most applications. Reflow soldering techniques are suitable for all QFP packages. REPAIRING SOLDERED JOINTS The choice of heating method may be influenced by larger plastic QFP packages (44 leads, or more). If infrared or vapour phase heating is used and the large packages are not absolutely dry (less than 0.1% moisture content by weight), vaporization of the small amount of moisture in them can cause cracking of the plastic body. For more information, refer to the Drypack chapter in our “Quality Reference Handbook” (order code 9397 750 00192). 1997 Jul 01 Fix the component by first soldering two diagonallyopposite end leads. Use only a low voltage soldering iron (less than 24 V) applied to the flat part of the lead. Contact time must be limited to 10 seconds at up to 300 °C. When using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 °C. 67 Philips Semiconductors Preliminary specification I2C-bus controlled economy PAL/NTSC and NTSC TV-processors TDA837x family DEFINITIONS Data sheet status Objective specification This data sheet contains target or goal specifications for product development. Preliminary specification This data sheet contains preliminary data; supplementary data may be published later. Product specification This data sheet contains final product specifications. Short-form specification The data in this specification is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook. Limiting values Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Where application information is given, it is advisory and does not form part of the specification. LIFE SUPPORT APPLICATIONS These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such improper use or sale. PURCHASE OF PHILIPS I2C COMPONENTS Purchase of Philips I2C components conveys a license under the Philips’ I2C patent to use the components in the I2C system provided the system conforms to the I2C specification defined by Philips. This specification can be ordered using the code 9398 393 40011. 1997 Jul 01 68 Philips Semiconductors Preliminary specification I2C-bus controlled economy PAL/NTSC and NTSC TV-processors NOTES 1997 Jul 01 69 TDA837x family Philips Semiconductors Preliminary specification I2C-bus controlled economy PAL/NTSC and NTSC TV-processors NOTES 1997 Jul 01 70 TDA837x family Philips Semiconductors Preliminary specification I2C-bus controlled economy PAL/NTSC and NTSC TV-processors NOTES 1997 Jul 01 71 TDA837x family Philips Semiconductors – a worldwide company Argentina: see South America Australia: 34 Waterloo Road, NORTH RYDE, NSW 2113, Tel. +61 2 9805 4455, Fax. +61 2 9805 4466 Austria: Computerstr. 6, A-1101 WIEN, P.O. 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No. 5, 80640 GÜLTEPE/ISTANBUL, Tel. +90 212 279 2770, Fax. +90 212 282 6707 Ukraine: PHILIPS UKRAINE, 4 Patrice Lumumba str., Building B, Floor 7, 252042 KIEV, Tel. +380 44 264 2776, Fax. +380 44 268 0461 United Kingdom: Philips Semiconductors Ltd., 276 Bath Road, Hayes, MIDDLESEX UB3 5BX, Tel. +44 181 730 5000, Fax. +44 181 754 8421 United States: 811 East Arques Avenue, SUNNYVALE, CA 94088-3409, Tel. +1 800 234 7381 Uruguay: see South America Vietnam: see Singapore Yugoslavia: PHILIPS, Trg N. Pasica 5/v, 11000 BEOGRAD, Tel. +381 11 625 344, Fax.+381 11 635 777 For all other countries apply to: Philips Semiconductors, Marketing & Sales Communications, Building BE-p, P.O. Box 218, 5600 MD EINDHOVEN, The Netherlands, Fax. +31 40 27 24825 Internet: http://www.semiconductors.philips.com © Philips Electronics N.V. 1997 SCA54 All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights. Printed in The Netherlands 547047/1200/01/pp72 Date of release: 1997 Jul 01 Document order number: 9397 750 01808