PHILIPS TDA9964

INTEGRATED CIRCUITS
DATA SHEET
TDA9964
12-bit, 3.0 V, 30 Msps
analog-to-digital interface for CCD
cameras
Objective specification
File under Integrated Circuits, IC02
2000 May 02
Philips Semiconductors
Objective specification
12-bit, 3.0 V, 30 Msps analog-to-digital
interface for CCD cameras
TDA9964
FEATURES
APPLICATIONS
• Correlated Double Sampling (CDS), Programmable
Gain Amplifier (PGA), 12-bit Analog-to-Digital
Converter (ADC) and reference regulator included
• Low-power, low-voltage CCD camera systems.
GENERAL DESCRIPTION
• Fully programmable via a 3-wire serial interface
The TDA9964 is a 12-bit analog-to-digital interface for
CCD cameras. The device includes a correlated double
sampling circuit, PGA, clamp loops and a low-power 12-bit
ADC together with its reference voltage regulator.
• Sampling frequency up to 30 MHz
• PGA gain range of 24 dB (in steps of 0.1 dB)
• Low power consumption of only 205 mW at 2.7 V
• Power consumption in standby mode of 4.5 mW (typ.)
The PGA gain and the ADC input clamp level are
controlled via the serial interface.
• 3.0 V operation and 2.5 to 3.6 V operation for the digital
outputs
An additional DAC is provided for additional system
controls; its output voltage range is 1.0 V p-p, which is
available at pin OFDOUT.
• All digital inputs accept 5 V signals
• Active control pulses polarity selectable via serial
interface
• 8-bit DAC included for analog settings
• TTL compatible inputs, CMOS compatible outputs.
QUICK REFERENCE DATA
SYMBOL
PARAMETER
CONDITIONS
MIN. TYP. MAX. UNIT
VCCA
analog supply voltage
2.7
3.0
3.6
V
VCCD
digital supply voltage
2.7
3.0
3.6
V
VCCO
digital outputs supply voltage
2.5
2.7
3.6
V
ICCA
analog supply current
−
71
−
mA
ICCD
digital supply current
−
4
−
mA
ICCO
digital outputs supply current
−
1
−
mA
ADCres
ADC resolution
all clamps active
fpix = 30 MHz; CL = 10 pF; input
ramp response time is 800 µs
Vi(CDS)(p-p) maximum CDS input voltage (peak-to-peak VCC = 2.85 V
value)
VCC ≥ 3.0 V
−
12
−
bits
650
−
−
mV
800
−
−
mV
fpix(max)
maximum pixel frequency
30
−
−
MHz
fpix(min)
minimum pixel frequency
tbf
−
−
MHz
DRPGA
PGA dynamic range
−
24
−
dB
Ntot(rms)
total noise from CDS input to ADC output
PGA gain = 0 dB; see Fig.8
−
1.5
−
LSB
Ein(rms)
equivalent input noise (RMS value)
gain = 24 dB
−
70
−
µV
Ptot
total power consumption
VCCA = VCCD = VCCO = 3 V
−
230
−
mW
VCCA = VCCD = VCCO = 2.7 V
−
205
−
mW
ORDERING INFORMATION
PACKAGE
TYPE NUMBER
NAME
TDA9964HL
2000 May 02
LQFP48
DESCRIPTION
plastic low profile quad flat package; 48 leads; body 7 × 7 × 1.4 mm
2
VERSION
SOT313-2
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45
46
AGND1
1
VCCA4
2
41
BLK
AGND6 CLPOB CLPDM
40
44
43
48
CLK
47
OE
39
22
21
CDS CLOCK GENERATOR
37
CPCDS1
38
8
TDA9964
36
CLAMP
CPCDS2
VCCA2
AGND2
IN
35
9
34
7
33
3
32
PGA
CORRELATED
DOUBLE
SAMPLING
4
BLACK
LEVEL
SHIFT
SHIFT
3
BLANKING
DATA
FLIPFLOP
31
OUTPUT
BUFFER
30
29
12-bit ADC
28
CLAMP
27
26
VCCA3
AGND3
25
Vref
14
8-BIT
REGISTER
5
7-BIT
REGISTER
24
OFD DAC
11
SERIAL
INTERFACE
8-BIT
REGISTER
12
6
13
15
16
OPGA
OPGAC
19
18
17
REGULATOR
20
10
VCCD1
OGND2
VCCO2
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
OGND1
VCCO1
DCLPC
42
FCE515
TEST
AGND5
SEN
STDBY
TDA9964
Fig.1 Block diagram.
SCLK SDATA VSYNC
Objective specification
AGND4
handbook, full pagewidth
OFDOUT
23
DGND1
Philips Semiconductors
VCCA1
SHD
12-bit, 3.0 V, 30 Msps analog-to-digital
interface for CCD cameras
BLOCK DIAGRAM
2000 May 02
SHP
Philips Semiconductors
Objective specification
12-bit, 3.0 V, 30 Msps analog-to-digital
interface for CCD cameras
TDA9964
PINNING
SYMBOL
PIN
DESCRIPTION
VCCA1
1
analog supply voltage 1
AGND1
2
analog ground 1
AGND2
3
analog ground 2
IN
4
input signal from CCD
AGND3
5
analog ground 3
AGND4
6
analog ground 4
VCCA2
7
analog supply voltage 2
CPCDS1
8
clamp storage capacitor pin 1
CPCDS2
9
clamp storage capacitor pin 2
DCLPC
10
regulator decoupling pin
OFDOUT
11
analog output of the additional 8-bit control DAC
TEST
12
test mode input pin (should be connected to AGND5)
AGND5
13
analog ground 5
VCCA3
14
analog supply 3
OPGA
15
PGA output (test pin)
OPGAC
16
PGA complementary output (test pin)
SDATA
17
serial data input for serial interface control
SCLK
18
serial clock input for serial interface
SEN
19
strobe pin for serial interface
VSYNC
20
vertical sync pulse input
VCCD1
21
digital supply voltage 1
DGND1
22
digital ground 1
VCCO1
23
output supply voltage 1
OGND1
24
digital output ground 1
D0
25
ADC digital output 0 (LSB)
D1
26
ADC digital output 1
D2
27
ADC digital output 2
D3
28
ADC digital output 3
D4
29
ADC digital output 4
D5
30
ADC digital output 5
D6
31
ADC digital output 6
D7
32
ADC digital output 7
D8
33
ADC digital output 8
D9
34
ADC digital output 9
D10
35
ADC digital output 10
D11
36
ADC digital output 11 (MSB)
OGND2
37
output digital ground 2
VCCO2
38
output supply voltage 2
OE
39
output enable control input (LOW: outputs active; HIGH: outputs are high impedance)
AGND6
40
analog ground 6
2000 May 02
4
Philips Semiconductors
Objective specification
12-bit, 3.0 V, 30 Msps analog-to-digital
interface for CCD cameras
SYMBOL
TDA9964
PIN
DESCRIPTION
45
preset sample-and-hold pulse input
SHD
46
data sample-and-hold pulse input
CLK
47
data clock input
CLPDM
48
clamp pulse input at dummy pixel
43 BLK
48
handbook, full pagewidth
37 OGND2
SHP
38 VCCO2
clamp pulse input at optical black
39 OE
44
40 AGND6
CLPOB
41 VCCA4
blanking control input
42 STDBY
standby mode control input (LOW: TDA9964 active; HIGH: TDA9964 standby)
43
44 CLPOB
42
BLK
45 SHP
STDBY
46 SHD
analog supply voltage 4
47 CLK
41
CLPDM
VCCA4
VCCA1
1
36 D11
AGND1
2
35 D10
AGND2
3
34 D9
IN
4
33 D8
AGND3
5
32 D7
AGND4 6
31 D6
TDA9964HL
VCCA2
7
30 D5
CPCDS1
8
29 D4
CPCDS2
9
28 D3
Fig.2 Pin configuration.
2000 May 02
5
OGND1 24
VCCO1 23
DGND1 22
VCCD1 21
VSYNC 20
SEN 19
SCLK 18
SDATA 17
25 D0
OPGA 15
TEST 12
OPGAC 16
26 D1
VCCA3 14
27 D2
AGND5 13
DCLPC 10
OFDOUT 11
FCE516
Philips Semiconductors
Objective specification
12-bit, 3.0 V, 30 Msps analog-to-digital
interface for CCD cameras
TDA9964
LIMITING VALUES
In accordance with the Absolute Maximum Rating System (IEC 60134).
SYMBOL
PARAMETER
CONDITIONS
MIN.
MAX.
UNIT
VCCA
analog supply voltage
note 1
−0.3
+7.0
V
VCCD
digital supply voltage
note 1
−0.3
+7.0
V
VCCO
digital outputs supply voltage
note 1
−0.3
+7.0
V
∆VCC
supply voltage difference:
between VCCA and VCCD
−0.5
+0.5
V
between VCCA and VCCO
−0.5
+1.2
V
−0.5
+1.2
V
−0.3
+7.0
V
data output current
−
±10
mA
between VCCD and VCCO
Vi
input voltage
Io
referenced to AGND
Tstg
storage temperature
−55
+150 °C
Tamb
ambient temperature
−20
+75
°C
Tj
junction temperature
−
150
°C
Note
1. The supply voltages VCCA, VCCD and VCCO may have any value between −0.3 and +7.0 V provided that the supply
voltage difference ∆VCC remains as indicated.
HANDLING
Inputs and outputs are protected against electrostatic discharges in normal handling. However, to be totally safe, it is
desirable to take normal precautions appropriate to handling integrated circuits.
THERMAL CHARACTERISTICS
SYMBOL
Rth(j-a)
PARAMETER
CONDITIONS
VALUE
UNIT
76
K/W
thermal resistance from junction to ambient in free air
CHARACTERISTICS
VCCA = VCCD = 3.0 V; VCCO = 2.7 V; fpix = 30 MHz; Tamb = 25 °C; unless otherwise specified.
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
Supplies
VCCA
analog supply voltage
2.7
3.0
3.6
V
VCCD
digital supply voltage
2.7
3.0
3.6
V
VCCO
digital outputs supply voltage
2.5
2.7
3.6
V
ICCA
analog supply current
−
71
−
mA
ICCD
digital supply current
−
4
−
mA
ICCO
digital outputs supply current
−
1
−
mA
2000 May 02
all clamps active
CL = 10 pF on all data
outputs; input ramp
response time is 800 µs
6
Philips Semiconductors
Objective specification
12-bit, 3.0 V, 30 Msps analog-to-digital
interface for CCD cameras
SYMBOL
PARAMETER
TDA9964
CONDITIONS
MIN.
TYP.
MAX.
UNIT
Digital inputs
PINS: SHP, SHD AND CLK (REFERENCED TO DGND)
0
−
VIL
LOW-level input voltage
0.6
V
VIH
HIGH-level input voltage
2.2
−
5.5
V
Ii
input current
0 ≤ Vi ≤ 5.5 V
−3
−
+3
µA
Zi
input impedance
fCLK = 30 MHz
−
50
−
kΩ
Ci
input capacitance
fCLK = 30 MHz
−
−
2
pF
0
−
0.6
V
PINS: CLPDM, CLPOB, SEN, SCLK, SDATA, STBY, OE, BLK, VSYNC
VIL
LOW-level input voltage
VIH
HIGH-level input voltage
Ii
input current
0 ≤ Vi ≤ 5.5 V
2.2
−
5.5
V
−2
−
+2
µA
12
−
−
pixels
−
20
−
mS
650
−
−
mV
800
−
−
mV
500
−
−
mV
tbf
−
tbf
µA
Clamps
GLOBAL CHARACTERISTICS OF THE CLAMP LOOPS
tW(clamp)
clamp active pulse width in
number of pixels
PGA code = 255 for
maximum 4 LSB error
INPUT CLAMP (DRIVEN BY CLPDM)
gm(CDS)
CDS input clamp
transconductance
Correlated Double Sampling (CDS)
Vi(CDS)(p-p)
maximum peak-to-peak CDS VCC = 2.85 V
input amplitude (video signal) VCC ≥ 3.0 V
Vreset(max)
maximum CDS input reset
pulse amplitude
Ii(IN)
input current into pin IN
Ci
input capacitance
−
2
−
pF
tCDS(min)
CDS control pulses minimum Vi(CDS)(p-p) = 800 mV
−
active time
black to white transition in
1 pixel with 99% Vi recovery
8
−
ns
th(IN;SHP)
CDS input hold time (pin IN)
compared to control pulse
SHP
VCCA = VCCD = 3.0 V;
Tamb = 25 °C;
see Figs 3 and 4
−
1
2
ns
th(IN;SHD)
CDS input hold time (pin IN)
compared to control pulse
SHD
VCCA = VCCD = 3.0 V;
Tamb = 25 °C;
see Figs 3 and 4
−
1
2
ns
at floating gate level
Amplifier
DRPGA
PGA dynamic range
−
24
−
dB
∆GPGA
PGA gain step
0.08
0.10
0.12
dB
−
±0.5
±0.9
LSB
Analog-to-Digital Converter (ADC)
DNL
2000 May 02
differential non linearity
fpix = 30 MHz; ramp input
7
Philips Semiconductors
Objective specification
12-bit, 3.0 V, 30 Msps analog-to-digital
interface for CCD cameras
SYMBOL
PARAMETER
TDA9964
CONDITIONS
MIN.
TYP.
MAX.
UNIT
Total chain characteristics (CDS + PGA + ADC)
fpix(max)
maximum pixel frequency
30
−
−
MHz
fpix(min)
minimum pixel frequency
tbf
−
−
MHz
tCLKH
CLK pulse width HIGH
12
−
−
ns
tCLKL
CLK pulse width LOW
12
−
−
ns
td(SHD;CLK)
time delay between
SHD and CLK
10
−
−
ns
tsu(BLK;SHD)
set-up time of BLK compared see Figs 3 and 4
to SHD
5
−
−
ns
Vi(IN)
video input dynamic signal
for ADC full-scale output
PGA code = 00
800
−
−
mV
PGA code = 255
50
−
−
mV
total noise from CDS input to
ADC output (RMS value)
see Fig.8
PGA gain = 0 dB
−
1.5
−
LSB
PGA gain = 9 dB
−
2.2
−
LSB
PGA gain = 24 dB
−
70
−
µV
PGA gain = 9 dB
−
140
−
µV
−100
−
+100 mV
−
1.0
−
V
−
AGND
−
V
VOFDOUT(255) DC output voltage for
code 255
−
AGND + 1.0 −
V
TCDAC
DAC output range
temperature coefficient
−
250
−
ppm/°C
ZOFDOUT
DAC output impedance
−
2000
−
Ω
IOFDOUT
OFD output current drive
−
−
100
µA
Ntot(rms)
Ein(rms)
equivalent input noise
voltage (RMS value)
OCCD(max)
maximum offset between
CCD floating level and CCD
dark pixel level
see Figs 3 and 4
Digital-to-analog converter (OFDOUT DAC)
VOFDOUT(p-p) additional 8-bit control DAC
(OFD) output voltage
(peak-to-peak value)
VOFDOUT(0)
Ri = 1 MΩ
DC output voltage for code 0
static
Digital outputs (fpix = 30 MHz; CL = 10 pF); see Figs 3 and 4
IOH = −1 mA
VCCO − 0.5 −
VOH
HIGH-level output voltage
VOL
LOW-level output voltage
IOL = 1 mA
0
−
0.5
V
IOZ
output current in 3-state
mode
0.5 V < Vo < VCCO
−20
−
+20
µA
th(o)
output hold time
5
−
−
ns
td(o)
output delay time
CL = 10 pF; VCCO = 3.0 V
−
12
tbf
ns
CL = 10 pF; VCCO = 2.7 V
−
14
tbf
ns
−
−
15
pF
10
−
−
MHz
CL
output load capacitance
VCCO V
Serial interface
fSCLK(max)
2000 May 02
maximum frequency of serial
interface
8
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N+1
N
N+2
N+3
N+4
N+5
t CDS(min)
2.2 V
SHP
0.6 V
t h(IN;SHP)
t CDS(min)
2.2 V
2.2 V
SHD
0.6 V
0.6 V
t h(IN;SHD)
9
tCLKH
2.2 V
2.2 V
CLK
Philips Semiconductors
12-bit, 3.0 V, 30 Msps analog-to-digital
interface for CCD cameras
2000 May 02
IN
0.6 V
0.6 V
t d(SHD;CLK)
DATA
N−4
N−3
50%
N−2
N−1
N
ADC CLAMP
CODE
th(o)
td(o)
2.2 V
Fig.3 Pixel frequency timing diagram; all polarities active HIGH.
TDA9964
handbook, full pagewidth
FCE517
t su(BLK;SHD)
Objective specification
BLK
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N+1
N
N+2
N+3
N+4
N+5
2.2 V
SHP
0.6 V
t CDS(min)
t h(IN;SHP)
2.2 V
2.2 V
SHD
0.6 V
0.6 V
t CDS(min)
t h(IN;SHD)
10
2.2 V
2.2 V
Philips Semiconductors
12-bit, 3.0 V, 30 Msps analog-to-digital
interface for CCD cameras
2000 May 02
IN
CLK
0.6 V
0.6 V
tCLKL
DATA
N−4
t d(SHD;CLK)
N−3
50%
N−2
N−1
N
ADC CLAMP
CODE
th(o)
td(o)
BLK
Fig.4 Pixel frequency timing diagram; all polarities active LOW.
FCE518
Objective specification
t su(BLK;SHD)
TDA9964
handbook, full pagewidth
0.6 V
Philips Semiconductors
Objective specification
12-bit, 3.0 V, 30 Msps analog-to-digital
interface for CCD cameras
TDA9964
FCE519
handbook, halfpage
1.0
OFDOUT
DAC voltage
output
(V)
0
255
0
OFDOUT control DAC input code
Fig.5 DAC voltage output as a function of DAC input code.
handbook, full pagewidth
CLPOB
WINDOW
AGCOUT
VIDEO
OPTICAL BLACK
CLPDM
WINDOW
HORIZONTAL FLYBACK
DUMMY
VIDEO
CLPOB
(active HIGH)
CLPDM
(active HIGH)
BLK
(active HIGH)
BLK window
FCE520
Fig.6 Line frequency timing diagram.
2000 May 02
11
Philips Semiconductors
Objective specification
12-bit, 3.0 V, 30 Msps analog-to-digital
interface for CCD cameras
TDA9964
FCE521
30
handbook, halfpage
TOTAL
gain
(dB)
25.9
24
18
12
6
1.9
0
0
64
128
192
255
PGA input code
Fig.7 Total gain from CDS input to ADC input as a function of PGA input code.
FCE522
6
handbook, halfpage
Ntot(rms)
(LSB)
5
4
3
2
1
0
0
64
128
192
255
PGA code
Noise measurement at ADC outputs: Coupling capacitor at input is grounded, so only noise contribution of the front-end is evaluated. Front-end works
at 30 Mpixels with line of 1024 pixels of which the first 40 lines are used to run CLPOB and the last 40 lines for CLPDM. Data at the ADC outputs is
measured during the other pixels. As a result, the standard deviation of the codes statistic is computed, resulting in the noise. No quantization noise is
taken into account as there is no input.
Fig.8 Typical total noise performance as a function of PGA gain.
2000 May 02
12
Philips Semiconductors
Objective specification
12-bit, 3.0 V, 30 Msps analog-to-digital
interface for CCD cameras
handbook, full
pagewidth
SDATA
TDA9964
SHIFT REGISTER
SD0 SD1
SD2 SD3
SD4 SD5 SD6
SCLK
SD7 SD8 SD9 SD10 SD11 A0
12
8
OFDOUT DAC
LATCHES
A2
A3
LATCH
SELECTION
SEN
SCLK
A1
MSB
LSB
8
7
PGA GAIN
LATCHES
ADC CLAMP
LATCHES
10
CONTROL PULSE
POLARITY
LATCHES
VSYNC
FLIP-FLOP
FLIP-FLOP
FLIP-FLOP
8-bit DAC
PGA control
ADC clamp
control
control pulses
polarity settings
FCE523
Fig.9 Serial interface block diagram.
tsu2
handbook, full pagewidth
thd4
MSB
SDATA
A3
A2
A1
A0
SD11 SD10 SD9
SD8
SD7
SD6
LSB
SD5
SD4
SD3
SD2
SD1
SD0
SCLK
SEN
tsu1
tsu3
thd3
FCE524
tsu1 = tsu2 = tsu3 = 10 ns (min.); thd3 = thd4 = 10 ns (min.)
Fig.10 Loading sequence of control input data via the serial interface.
2000 May 02
13
Philips Semiconductors
Objective specification
12-bit, 3.0 V, 30 Msps analog-to-digital
interface for CCD cameras
Table 1
TDA9964
Serial interface programming
ADDRESS BITS
DATA BITS D9 TO D0
A3
A2
A1
A0
0
0
0
0
PGA gain control (SD7 to SD0)
0
0
0
1
DAC OFDOUT output control (SD7 to SD0)
0
0
1
0
ADC clamp reference control (SD6 to SD0); from code 0 to 127
0
0
1
1
control pulses (pins SHP, SHD, CLPDM, CLPOB, BLK and CLK) polarity settings;
SD2, SD6, SD7 and SD9 should be set to logic 1; for SD6 and SD7 see Tables 3 4, 5, and 6
0
1
0
0
SD7 = 0 by default; SD7 = 1 PGA gain up to 36 dB but noise and clamp behaviour are not
guaranteed
1
1
1
1
initialization (SD8 = 1; SD11 to SD9 = 0 and SD7 to SD0 = 0)
other addresses
Table 2
test modes
Polarity settings
SYMBOL
SHP and SHD
PIN
SERIAL CONTROL BIT
ACTIVE EDGE OR LEVEL
45 and 46
SD4
1 = HIGH; 0 = LOW
CLK
47
SD5
1 = rising; 0 = falling
CLPDM
48
SD0
1 = HIGH; 0 = LOW
CLPOB
44
SD1
1 = HIGH; 0 = LOW
BLK
43
SD3
1 = HIGH; 0 = LOW
VSYNC
20
SD8
0 = rising; 1 = falling
Table 3
Standby control using pin STDBY
BIT SD7 OF
REGISTER 0011
STDBY
ADC DIGITAL OUTPUTS D11 TO D0
ICCA + ICCO + ICCD (typ.)
1
1
last logic state
1.5 mA
0
active
72 mA
1
active
72 mA
0
test logic state
1.5 mA
0
Table 4
Output enable selection using output enable pin (OE)
BIT SD6 OF
REGISTER 0011
OE
ADC DIGITAL OUTPUTS D11 TO D0
1
0
active, binary
1
high impedance
0
high impedance
1
active binary
0
2000 May 02
14
Philips Semiconductors
Objective specification
12-bit, 3.0 V, 30 Msps analog-to-digital
interface for CCD cameras
Table 5
Table 6
TDA9964
Standby control by serial interface (register address A3 = 0, A2 = 0, A1 = 1 and A0 = 1); pin STDBY
connected to ground
SD7
ADC DIGITAL OUTPUTS D11 TO D0
ICCA + ICCO + ICCD (typ.)
0
last logic state
1.5 mA
1
active
72 mA
Output enable control by serial interface (register address A3 = 0, A2 = 0, A1 = 1 and A0 = 1); output enable
pin (OE) connected to ground
2000 May 02
SD6
ADC DIGITAL OUTPUTS D11 TO D0
0
high impedance
1
active binary
15
Philips Semiconductors
Objective specification
12-bit, 3.0 V, 30 Msps analog-to-digital
interface for CCD cameras
TDA9964
APPLICATION DIAGRAM
VCCD
andbook, full pagewidth
VCCA
VCCD
VCCO
100 nF
100 nF
OGND2
VCCO2
OE
AGND6
VCCA4
STDBY
BLK
CLPOB
(2)
SHP
1 µF
CLK
CLPDM
CCD(2)
SHD
(2)
48 47 46 45 44 43 42 41 40 39 38 37
VCCA1
VCCA
AGND1
AGND2
IN
AGND3
AGND4
VCCA2
VCCA
100
nF
CPCDS1
1
µF
CPCDS2
1
µF
DCLPC
1
µF
OFDOUT
TEST
1
36
2
35
3
34
4
33
5
32
6
31
TDA9964
7
30
8
29
9
28
10
27
11
26
12
25
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
100 nF
OGND1
VCCO1
DGND1
100 nF
serial
interface
VCCA
VCCD1
VSYNC
SEN
SCLK
SDATA
OPGA
OPGAC
VCCA3
AGND5
13 14 15 16 17 18 19 20 21 22 23 24
100 nF
(1)
VCCD
VCCO
FCE525
(1) Pins SEN and VSYNC should be interconnected when the vertical sync signal is not available.
(2) Input signals IN, SHD and SHP must be adjusted to comply with timing signals th(IN;SHP) and th(IN;SHD) (see Chapter “Characteristics”).
Fig.11 Application diagram.
2000 May 02
16
Philips Semiconductors
Objective specification
12-bit, 3.0 V, 30 Msps analog-to-digital
interface for CCD cameras
Power and grounding recommendations
To minimise the noise caused by package and die
parasitics in a two-ground system, the following
recommendation must be implemented:
When designing a printed-circuit board for applications
such as PC cameras, surveillance cameras, camcorders
and digital still cameras, care should be taken to minimise
the noise.
All analog and digital supply pins must be decoupled to the
analog ground plane. Only the ground pin associated with
the digital outputs must be connected to the digital ground
plane. All other ground pins should be connected to the
analog ground plane. The analog and digital ground
planes must be connected together at one point as closely
as possible to the ground pin associated with the digital
outputs.
For the front end integrated circuit, the basic rules of
printed-circuit board design and implementation of analog
components (such as classical operational amplifiers)
must be respected, particularly with respect to power and
ground connections.
The following additional recommendation is given for the
CDS input pin(s) which is (are) internally connected to the
programmable gain amplifier:
The digital output pins and their associated lines should be
shielded by the digital ground plane, which can then be
used as return path for digital signals.
The connections between CCD interface and CDS input
should be as short as possible and a ground ring
protection around these connections can be beneficial.
Separate analog and digital supplies provide the best
solution. If it is not possible to do this on the board, the
analog supply pins must be decoupled effectively from the
digital supply pins. If the same power supply and ground
are used for all the pins, the decoupling capacitors must be
placed as closely as possible to the IC package.
2000 May 02
TDA9964
17
Philips Semiconductors
Objective specification
12-bit, 3.0 V, 30 Msps analog-to-digital
interface for CCD cameras
TDA9964
PACKAGE OUTLINE
LQFP48: plastic low profile quad flat package; 48 leads; body 7 x 7 x 1.4 mm
SOT313-2
c
y
X
36
25
A
37
24
ZE
e
E HE
A A2
(A 3)
A1
w M
pin 1 index
θ
bp
Lp
L
13
48
detail X
12
1
ZD
e
v M A
w M
bp
D
B
HD
v M B
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
UNIT
A
max.
A1
A2
A3
bp
c
D (1)
E (1)
e
HD
HE
L
Lp
v
w
y
mm
1.60
0.20
0.05
1.45
1.35
0.25
0.27
0.17
0.18
0.12
7.1
6.9
7.1
6.9
0.5
9.15
8.85
9.15
8.85
1.0
0.75
0.45
0.2
0.12
0.1
Z D (1) Z E (1)
θ
0.95
0.55
7
0o
0.95
0.55
o
Note
1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.
REFERENCES
OUTLINE
VERSION
IEC
JEDEC
SOT313-2
136E05
MS-026
2000 May 02
EIAJ
EUROPEAN
PROJECTION
ISSUE DATE
99-12-27
00-01-19
18
Philips Semiconductors
Objective specification
12-bit, 3.0 V, 30 Msps analog-to-digital
interface for CCD cameras
SOLDERING
TDA9964
If wave soldering is used the following conditions must be
observed for optimal results:
Introduction to soldering surface mount packages
• Use a double-wave soldering method comprising a
turbulent wave with high upward pressure followed by a
smooth laminar wave.
This text gives a very brief insight to a complex technology.
A more in-depth account of soldering ICs can be found in
our “Data Handbook IC26; Integrated Circuit Packages”
(document order number 9398 652 90011).
• For packages with leads on two sides and a pitch (e):
– larger than or equal to 1.27 mm, the footprint
longitudinal axis is preferred to be parallel to the
transport direction of the printed-circuit board;
There is no soldering method that is ideal for all surface
mount IC packages. Wave soldering is not always suitable
for surface mount ICs, or for printed-circuit boards with
high population densities. In these situations reflow
soldering is often used.
– smaller than 1.27 mm, the footprint longitudinal axis
must be parallel to the transport direction of the
printed-circuit board.
Reflow soldering
The footprint must incorporate solder thieves at the
downstream end.
Reflow soldering requires solder paste (a suspension of
fine solder particles, flux and binding agent) to be applied
to the printed-circuit board by screen printing, stencilling or
pressure-syringe dispensing before package placement.
• For packages with leads on four sides, the footprint must
be placed at a 45° angle to the transport direction of the
printed-circuit board. The footprint must incorporate
solder thieves downstream and at the side corners.
Several methods exist for reflowing; for example,
infrared/convection heating in a conveyor type oven.
Throughput times (preheating, soldering and cooling) vary
between 100 and 200 seconds depending on heating
method.
During placement and before soldering, the package must
be fixed with a droplet of adhesive. The adhesive can be
applied by screen printing, pin transfer or syringe
dispensing. The package can be soldered after the
adhesive is cured.
Typical reflow peak temperatures range from
215 to 250 °C. The top-surface temperature of the
packages should preferable be kept below 230 °C.
Typical dwell time is 4 seconds at 250 °C.
A mildly-activated flux will eliminate the need for removal
of corrosive residues in most applications.
Wave soldering
Manual soldering
Conventional single wave soldering is not recommended
for surface mount devices (SMDs) or printed-circuit boards
with a high component density, as solder bridging and
non-wetting can present major problems.
Fix the component by first soldering two
diagonally-opposite end leads. Use a low voltage (24 V or
less) soldering iron applied to the flat part of the lead.
Contact time must be limited to 10 seconds at up to
300 °C.
To overcome these problems the double-wave soldering
method was specifically developed.
When using a dedicated tool, all other leads can be
soldered in one operation within 2 to 5 seconds between
270 and 320 °C.
2000 May 02
19
Philips Semiconductors
Objective specification
12-bit, 3.0 V, 30 Msps analog-to-digital
interface for CCD cameras
TDA9964
Suitability of surface mount IC packages for wave and reflow soldering methods
SOLDERING METHOD
PACKAGE
WAVE
BGA, LFBGA, SQFP, TFBGA
not suitable
suitable(2)
HBCC, HLQFP, HSQFP, HSOP, HTQFP, HTSSOP, SMS
not
PLCC(3), SO, SOJ
suitable
LQFP, QFP, TQFP
SSOP, TSSOP, VSO
REFLOW(1)
suitable
suitable
suitable
not
recommended(3)(4)
suitable
not
recommended(5)
suitable
Notes
1. All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the maximum
temperature (with respect to time) and body size of the package, there is a risk that internal or external package
cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). For details, refer to the
Drypack information in the “Data Handbook IC26; Integrated Circuit Packages; Section: Packing Methods”.
2. These packages are not suitable for wave soldering as a solder joint between the printed-circuit board and heatsink
(at bottom version) can not be achieved, and as solder may stick to the heatsink (on top version).
3. If wave soldering is considered, then the package must be placed at a 45° angle to the solder wave direction.
The package footprint must incorporate solder thieves downstream and at the side corners.
4. Wave soldering is only suitable for LQFP, TQFP and QFP packages with a pitch (e) equal to or larger than 0.8 mm;
it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm.
5. Wave soldering is only suitable for SSOP and TSSOP packages with a pitch (e) equal to or larger than 0.65 mm; it is
definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm.
2000 May 02
20
Philips Semiconductors
Objective specification
12-bit, 3.0 V, 30 Msps analog-to-digital
interface for CCD cameras
TDA9964
DATA SHEET STATUS
DATA SHEET STATUS
PRODUCT
STATUS
DEFINITIONS (1)
Objective specification
Development
This data sheet contains the design target or goal specifications for
product development. Specification may change in any manner without
notice.
Preliminary specification
Qualification
This data sheet contains preliminary data, and supplementary data will be
published at a later date. Philips Semiconductors reserves the right to
make changes at any time without notice in order to improve design and
supply the best possible product.
Product specification
Production
This data sheet contains final specifications. Philips Semiconductors
reserves the right to make changes at any time without notice in order to
improve design and supply the best possible product.
Note
1. Please consult the most recently issued data sheet before initiating or completing a design.
DEFINITIONS
DISCLAIMERS
Short-form specification  The data in a short-form
specification is extracted from a full data sheet with the
same type number and title. For detailed information see
the relevant data sheet or data handbook.
Life support applications  These products are not
designed for use in life support appliances, devices, or
systems where malfunction of these products can
reasonably be expected to result in personal injury. Philips
Semiconductors customers using or selling these products
for use in such applications do so at their own risk and
agree to fully indemnify Philips Semiconductors for any
damages resulting from such application.
Limiting values definition  Limiting values given are in
accordance with the Absolute Maximum Rating System
(IEC 60134). Stress above one or more of the limiting
values may cause permanent damage to the device.
These are stress ratings only and operation of the device
at these or at any other conditions above those given in the
Characteristics sections of the specification is not implied.
Exposure to limiting values for extended periods may
affect device reliability.
Right to make changes  Philips Semiconductors
reserves the right to make changes, without notice, in the
products, including circuits, standard cells, and/or
software, described or contained herein in order to
improve design and/or performance. Philips
Semiconductors assumes no responsibility or liability for
the use of any of these products, conveys no licence or title
under any patent, copyright, or mask work right to these
products, and makes no representations or warranties that
these products are free from patent, copyright, or mask
work right infringement, unless otherwise specified.
Application information  Applications that are
described herein for any of these products are for
illustrative purposes only. Philips Semiconductors make
no representation or warranty that such applications will be
suitable for the specified use without further testing or
modification.
2000 May 02
21
Philips Semiconductors
Objective specification
12-bit, 3.0 V, 30 Msps analog-to-digital
interface for CCD cameras
NOTES
2000 May 02
22
TDA9964
Philips Semiconductors
Objective specification
12-bit, 3.0 V, 30 Msps analog-to-digital
interface for CCD cameras
NOTES
2000 May 02
23
TDA9964
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Internet: http://www.semiconductors.philips.com
SCA 69
© Philips Electronics N.V. 2000
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner.
The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed
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under patent- or other industrial or intellectual property rights.
Printed in The Netherlands
753504/01/pp24
Date of release: 2000
May 02
Document order number:
9397 750 06823