PHILIPS HEF4017BF

INTEGRATED CIRCUITS
DATA SHEET
For a complete data sheet, please also download:
• The IC04 LOCMOS HE4000B Logic
Family Specifications HEF, HEC
• The IC04 LOCMOS HE4000B Logic
Package Outlines/Information HEF, HEC
HEF4017B
MSI
5-stage Johnson counter
Product specification
File under Integrated Circuits, IC04
January 1995
Philips Semiconductors
Product specification
HEF4017B
MSI
5-stage Johnson counter
A HIGH on MR resets the counter to zero
(Oo = O5-9 = HIGH; O1 to O9 = LOW) independent of the
clock inputs (CP0, CP1).
DESCRIPTION
The HEF4017B is a 5-stage Johnson decade counter with
ten spike-free decoded active HIGH outputs (Oo to O9), an
active LOW output from the most significant flip-flop (O5-9),
active HIGH and active LOW clock inputs (CP0, CP1) and
an overriding asynchronous master reset input (MR).
Automatic code correction of the counter is provided by an
internal circuit: following any illegal code the counter
returns to a proper counting mode within 11 clock pulses.
Schmitt-trigger action in the clock input makes the circuit
highly tolerant to slower clock rise and fall times.
The counter is advanced by either a LOW to HIGH
transition at CP0 while CP1 is LOW or a HIGH to LOW
transition at CP1 while CP0 is HIGH (see also function
table).
When cascading counters, the O5-9 output, which is LOW
while the counter is in states 5, 6, 7, 8 and 9, can be used
to drive the CP0 input of the next counter.
Fig.1 Functional diagram.
PINNING
CP0
clock input (LOW to HIGH triggered)
CP1
clock input (HIGH to LOW triggered)
MR
master reset input
O0 to O9
decoded outputs
O5-9
carry output (active LOW)
FAMILY DATA, IDD LIMITS category MSI
Fig.2 Pinning diagram.
HEF4017BP(N):
16-lead DIL; plastic (SOT38-1)
HEF4017BD(F):
16-lead DIL; ceramic (cerdip) (SOT74)
HEF4017BT(D):
16-lead SO; plastic (SOT109-1)
See Family Specifications
( ): Package Designator North America
January 1995
2
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Philips Semiconductors
5-stage Johnson counter
January 1995
3
Product specification
HEF4017B
MSI
Fig.3 Logic diagram.
Philips Semiconductors
Product specification
HEF4017B
MSI
5-stage Johnson counter
Notes
FUNCTION TABLE
1. H = HIGH state (the more positive voltage)
MR
CP0
CP1
OPERATION
H
X
X
O0 = O5-9 = H; O1 to O9 = L
L
H
L
3. X = state is immaterial
Counter advances
L
Counter advances
L
L
X
No change
L
X
H
No change
L
H
L
2. L = LOW state (the less positive voltage)
4.
= positive-going transition
5.
= negative-going transition
No change
L
No change
AC CHARACTERISTICS
VSS = 0 V; Tamb = 25 °C; CL = 50 pF; input transition times ≤ 20 ns
VDD
V
SYMBOL
MIN.
TYPICAL EXTRAPOLATION
FORMULA
TYP.
MAX.
140
280
ns
113 ns + (0,55 ns/pF) CL
Propagation delays
CP0, CP1 → O0 to O9
HIGH to LOW
LOW to HIGH
CP0, CP1 → O5-9
HIGH to LOW
LOW to HIGH
MR → O1 to O9
HIGH to LOW
MR → O5-9
LOW to HIGH
MR → O0
LOW to HIGH
5
55
110
ns
44 ns + (0,23 ns/pF) CL
15
40
80
ns
32 ns + (0,16 ns/pF) CL
5
125
250
ns
98 ns + (0,55 ns/pF) CL
10
tPHL
50
100
ns
39 ns + (0,23 ns/pF) CL
15
40
80
ns
32 ns + (0,16 ns/pF) CL
5
145
290
ns
118 ns + (0,55 ns/pF) CL
10
tPLH
55
110
ns
44 ns + (0,23 ns/pF) CL
15
40
80
ns
32 ns + (0,16 ns/pF) CL
5
125
250
ns
98 ns + (0,55 ns/pF) CL
10
tPHL
50
100
ns
39 ns + (0,23 ns/pF) CL
15
40
80
ns
32 ns + (0,16 ns/pF) CL
5
115
230
ns
88 ns + (0,55 ns/pF) CL
50
100
ns
39 ns + (0,23 ns/pF) CL
10
10
tPLH
tPHL
15
35
70
ns
27 ns + (0,16 ns/pF) CL
5
110
220
ns
83 ns + (0,55 ns/pF) CL
45
90
ns
34 ns + (0,23 ns/pF) CL
10
tPLH
15
35
70
ns
27 ns + (0,16 ns/pF) CL
5
130
260
ns
103 ns + (0,55 ns/pF) CL
55
105
ns
44 ns + (0,23 ns/pF) CL
40
75
ns
32 ns + (0,16 ns/pF) CL
10
tPLH
15
January 1995
4
Philips Semiconductors
Product specification
HEF4017B
MSI
5-stage Johnson counter
VDD
V
SYMBOL
MIN.
TYP.
MAX.
TYPICAL EXTRAPOLATION
FORMULA
Output transition
times
HIGH to LOW
5
10
tTHL
15
5
LOW to HIGH
10
tTLH
15
10 ns + (1,0 ns/pF) CL
60
120
ns
30
60
ns
9 ns + (0,42 ns/pF) CL
20
40
ns
6 ns + (0,28 ns/pF) CL
10 ns + (1,0 ns/pF) CL
60
120
ns
30
60
ns
9 ns + (0,42 ns/pF) CL
20
40
ns
6 ns + (0,28 ns/pF) CL
AC CHARACTERISTICS
VSS = 0 V; Tamb = 25 °C; CL = 50 pF; input transition times ≤ 20 ns
VDD
V
Hold times
CP0 →CP1
SYMBOL
5
10
thold
15
5
CP1 → CP0
10
thold
15
MIN.
TYP.
MAX.
90
45
ns
40
20
ns
20
10
ns
80
40
ns
40
20
ns
30
10
ns
80
40
ns
40
20
ns
see also waveforms
30
15
ns
Figs 4 and 5
50
25
ns
30
15
ns
Minimum clock
pulse width:
5
CP0 = LOW;
10
CP1 = HIGH
15
Minimum MR
pulse width; HIGH
tWCPL =
tWCPH
5
10
tWMRH
15
20
10
ns
Recovery time
5
60
30
ns
for MR
10
30
15
ns
20
10
ns
tRMR
15
Maximum clock
pulse frequency
5
10
15
VDD
V
Dynamic power
5
fmax
6
12
MHz
12
24
MHz
15
30
MHz
TYPICAL FORMULA FOR P (µW)
500 fi + ∑ (foCL) × VDD2
dissipation per
10
2200 fi + ∑ (foCL) ×
package (P)
15
6000 fi + ∑ (foCL) ×
VDD2
VDD2
where
fi = input freq. (MHz)
fo = output freq. (MHz)
CL = load cap. (pF)
∑ (foCL) = sum of outputs
VDD = supply voltage (V)
January 1995
5
Philips Semiconductors
Product specification
HEF4017B
MSI
5-stage Johnson counter
Fig.4
Waveforms showing hold times for CP0 to CP1 and CP1 to CP0. Hold times are shown as positive values,
but may be specified as negative values.
Conditions: CP1 = LOW while CP0 is triggered on a LOW to HIGH transition. tWCP and
tRMR also apply when CP0 = HIGH and CP1 is triggered on a HIGH to LOW transition.
Fig.5 Waveforms showing recovery time for MR; minimum CP0 and MR pulse widths.
January 1995
6
Philips Semiconductors
Product specification
HEF4017B
MSI
5-stage Johnson counter
Fig.6 Timing diagram.
January 1995
7
Philips Semiconductors
Product specification
HEF4017B
MSI
5-stage Johnson counter
APPLICATION INFORMATION
Some examples of applications for the HEF4017B are:
• Decade counter with decimal decoding
• 1 out of n decoding counter (when cascaded)
• Sequential controller
• Timer.
Figure 7 shows a technique for extending the number of decoded output states for the HEF4017B. Decoded outputs are
sequential within each stage and from stage to stage, with no dead time (except propagation delay).
Fig.7 Counter expansion.
Note
It is essential not to enable the counter on CP1 when CP0 is HIGH, or on CP0 when CP1 is LOW, as the this would cause
an extra count.
January 1995
8