PHILIPS 74HC21DB

74HC21
Dual 4-input AND gate
Rev. 05 — 7 May 2009
Product data sheet
1. General description
The 74HC21 is a high-speed Si-gate CMOS device and is pin compatible with low-power
Schottky TTL (LSTTL).
The 74HC21 provide the 4-input AND function.
2. Features
n Low-power dissipation
n Complies with JEDEC standard no. 7A
n ESD protection:
u HBM JESD22-A114E exceeds 2000 V
u MM JESD22-A115-A exceeds 200 V
n Multiple package options
n Specified from −40 °C to +80 °C and from −40 °C to +125 °C.
3. Ordering information
Table 1.
Ordering information
Type number
Package
Temperature range
Name
Description
Version
74HC21N
−40 °C to +125 °C
DIP14
plastic dual in-line package; 14 leads (300 mil)
SOT27-1
74HC21D
−40 °C to +125 °C
SO14
plastic small outline package; 14 leads;
body width 3.9 mm
SOT108-1
74HC21DB
−40 °C to +125 °C
SSOP14
plastic shrink small outline package; 14 leads;
body width 5.3 mm
SOT337-1
74HC21PW
−40 °C to +125 °C
TSSOP14
plastic thin shrink small outline package; 14 leads;
body width 4.4 mm
SOT402-1
74HC21
NXP Semiconductors
Dual 4-input AND gate
4. Functional diagram
1A
1
1B
2
1Y
1C
4
1
6
2
4
1D
5
9
10
2A
5
2B
9
2Y
2C
12
8
10
12
2D
13
13
1A
1B
6
1D
2A
2B
2Y
2C
8
2D
001aab975
Fig 1.
1Y
1C
001aab973
Functional diagram
Fig 2.
Logic symbol
&
1
2
6
A
4
5
B
&
9
10
Y
8
C
12
13
D
001aab974
Fig 3.
IEC Logic symbol
Fig 4.
001aab976
Logic diagram
5. Pinning information
5.1 Pinning
74HC21
1A
1
14 VCC
1B
2
13 2D
n.c.
3
12 2C
1C
4
11 n.c.
1D
5
10 2B
1Y
6
9
2A
GND
7
8
2Y
74HC21
Pin configuration SOT27-1 and SOT108-1
Fig 6.
74HC21_5
Product data sheet
1
14 VCC
1B
2
13 2D
n.c.
3
12 2C
1C
4
11 n.c.
1D
5
10 2B
1Y
6
9
2A
GND
7
8
2Y
001aai659
001aab972
Fig 5.
1A
Pin configuration SOT337-1 and SOT402-1
© NXP B.V. 2009. All rights reserved.
Rev. 05 — 7 May 2009
2 of 14
74HC21
NXP Semiconductors
Dual 4-input AND gate
5.2 Pin description
Table 2.
Pin description
Symbol
Pin
Description
1A, 1B, 1C, 1D
1, 2, 4, 5
data input
n.c.
3, 11
not connected
1Y
6
data output
GND
7
ground (0 V)
2Y
8
data output
2A, 2B, 2C, 2D
9, 10, 12, 13
data input
VCC
14
supply voltage
6. Functional description
Table 3.
Function table[1]
Input
Output
nA
nB
nC
nD
nY
L
X
X
X
L
X
L
X
X
L
X
X
L
X
L
X
X
X
L
L
H
H
H
H
H
[1]
H = HIGH voltage level; L = LOW voltage level; X = don’t care.
7. Limiting values
Table 4.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol
Parameter
Conditions
Min
Max
Unit
VCC
supply voltage
−0.5
+7
V
IIK
input clamping current
VI < −0.5 V or VI > VCC + 0.5 V
[1]
-
±20
mA
IOK
output clamping current
VO < −0.5 V or VO > VCC + 0.5 V
[1]
-
±20
mA
IO
output current
−0.5 V < VO < VCC + 0.5 V
-
±25
mA
ICC
supply current
-
50
mA
IGND
ground current
−50
-
mA
Tstg
storage temperature
−65
+150
°C
DIP14 package
-
750
mW
SO14 and (T)SSOP14
packages
-
500
mW
[2]
total power dissipation
Ptot
[1]
The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
[2]
For DIP14 package: Ptot derates linearly with 12 mW/K above 70 °C.
For SO14 package: Ptot derates linearly with 8 mW/K above 70 °C.
For (T)SSOP14 packages: Ptot derates linearly with 5.5 mW/K above 60 °C.
74HC21_5
Product data sheet
© NXP B.V. 2009. All rights reserved.
Rev. 05 — 7 May 2009
3 of 14
74HC21
NXP Semiconductors
Dual 4-input AND gate
8. Recommended operating conditions
Table 5.
Recommended operating conditions
Voltages are referenced to GND (ground = 0 V)
Symbol
Parameter
Conditions
VCC
supply voltage
Min
Typ
Max
Unit
2.0
5.0
6.0
V
VI
input voltage
0
-
VCC
V
VO
output voltage
0
-
VCC
V
∆t/∆V
input transition rise and fall
rate
VCC = 2.0 V
-
-
625
ns/V
VCC = 4.5 V
-
1.67
139
ns/V
VCC = 6.0 V
Tamb
ambient temperature
-
-
83
ns/V
−40
-
+125
°C
9. Static characteristics
Table 6.
Static characteristics
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol Parameter
25 °C
Conditions
Min
VIH
VIL
VOH
VOL
HIGH-level
input voltage
LOW-level
input voltage
HIGH-level
output voltage
LOW-level
output voltage
Typ
−40 °C to +85 °C −40 °C to +125 °C Unit
Max
Min
Max
Min
Max
VCC = 2.0 V
1.5
1.2
-
1.5
-
1.5
-
V
VCC = 4.5 V
3.15
2.4
-
3.15
-
3.15
-
V
VCC = 6.0 V
4.2
3.2
-
4.2
-
4.2
-
V
VCC = 2.0 V
-
0.8
0.5
-
0.5
-
0.5
V
VCC = 4.5 V
-
2.1
1.35
-
1.35
-
1.35
V
VCC = 6.0 V
-
2.8
1.8
-
1.8
-
1.8
V
IO = −20 µA; VCC = 2.0 V
1.9
2.0
-
1.9
-
1.9
-
V
IO = −20 µA; VCC = 4.5 V
4.4
4.5
-
4.4
-
4.4
-
V
IO = −20 µA; VCC = 6.0 V
5.9
6.0
-
5.9
-
5.9
-
V
IO = −4.0 mA; VCC = 4.5 V
3.98
4.32
-
3.84
-
3.7
-
V
IO = −5.2 mA; VCC = 6.0 V
5.48
5.81
-
5.34
-
5.2
-
V
IO = 20 µA; VCC = 2.0 V
-
0
0.1
-
0.1
-
0.1
V
IO = 20 µA; VCC = 4.5 V
-
0
0.1
-
0.1
-
0.1
V
IO = 20 µA; VCC = 6.0 V
-
0
0.1
-
0.1
-
0.1
V
IO = 4.0 mA; VCC = 4.5 V
-
0.15
0.26
-
0.33
-
0.4
V
IO = 5.2 mA; VCC = 6.0 V
-
0.16
0.26
-
0.33
-
0.4
V
VI = VIH or VIL
VI = VIH or VIL
II
input leakage
current
VI = VCC or GND;
VCC = 6.0 V
-
-
±0.1
-
±1
-
±1
µA
ICC
supply current
VI = VCC or GND; IO = 0 A;
VCC = 6.0 V
-
-
2.0
-
20
-
40
µA
CI
input
capacitance
-
3.5
-
-
-
-
-
pF
74HC21_5
Product data sheet
© NXP B.V. 2009. All rights reserved.
Rev. 05 — 7 May 2009
4 of 14
74HC21
NXP Semiconductors
Dual 4-input AND gate
10. Dynamic characteristics
Table 7.
Dynamic characteristics
GND = 0 V; test circuit see Figure 8.
Symbol Parameter
propagation
delay
tpd
transition time
tt
power
dissipation
capacitance
CPD
25 °C
Conditions
−40 °C to +85 °C
Min
Typ
Max
Min
Max
Min
Max
VCC = 2.0 V
-
33
110
-
140
-
165
ns
VCC = 4.5 V
-
12
22
-
28
-
33
ns
[1]
nA, nB, nC or nD to nY;
see Figure 7
VCC = 6.0 V
-
10
19
-
24
-
28
ns
VCC = 5.0 V; CL = 15 pF
-
10
-
-
-
-
-
ns
VCC = 2.0 V
-
19
75
-
95
-
110
ns
VCC = 4.5 V
-
7
15
-
19
-
22
ns
VCC = 6.0 V
-
6
13
-
16
-
19
ns
-
15
-
-
-
-
-
pF
nY output; see Figure 7
VI = GND to VCC
[2]
[3]
[1]
tpd is the same as tPHL and tPLH.
[2]
tt is the same as tTHL and tTLH.
[3]
CPD is used to determine the dynamic power dissipation (PD in µW):
PD = CPD × VCC2 × fi × N + ∑ (CL × VCC2 × fo) where:
fi = input frequency in MHz;
fo = output frequency in MHz;
CL = output load capacitance in pF;
VCC = supply voltage in V;
N = number of inputs switching;
∑ (CL × VCC2 × fo) = sum of outputs.
74HC21_5
Product data sheet
−40 °C to +125 °C Unit
© NXP B.V. 2009. All rights reserved.
Rev. 05 — 7 May 2009
5 of 14
74HC21
NXP Semiconductors
Dual 4-input AND gate
11. Waveforms
VI
nA, nB, nC,
nD input
VM
GND
tPHL
VOH
nY output
tPLH
VY
VM
VX
VOL
tTHL
tTLH
001aab977
Measurement points are given in Table 8.
VOL and VOH are typical voltage output levels that occur with the output load.
Fig 7.
Table 8.
Waveforms showing the input (nA, nB, nC, nD) to output (nY) propagation delays and the output
transition times
Measurement points
Type
74HC21
Input
Output
VM
VM
VX
VY
0.5VCC
0.5VCC
0.1VCC
0.9VCC
74HC21_5
Product data sheet
© NXP B.V. 2009. All rights reserved.
Rev. 05 — 7 May 2009
6 of 14
74HC21
NXP Semiconductors
Dual 4-input AND gate
VI
negative
pulse
tW
90 %
VM
VM
10 %
GND
tr
tf
tr
tf
VI
90 %
positive
pulse
GND
VM
VM
10 %
tW
VCC
G
VI
VO
DUT
RT
CL
001aah768
Test data is given in Table 9.
Definitions test circuit:
RT = termination resistance should be equal to output impedance Zo of the pulse generator.
CL = load capacitance including jig and probe capacitance.
Fig 8.
Table 9.
Test circuit for measuring switching times
Test data
Type
74HC21
Input
Load
VI
tr, tf
CL
VCC
6.0 ns
15 pF, 50 pF
74HC21_5
Product data sheet
Test
tPLH, tPHL
© NXP B.V. 2009. All rights reserved.
Rev. 05 — 7 May 2009
7 of 14
74HC21
NXP Semiconductors
Dual 4-input AND gate
12. Package outline
DIP14: plastic dual in-line package; 14 leads (300 mil)
SOT27-1
ME
seating plane
D
A2
A
A1
L
c
e
Z
w M
b1
(e 1)
b
MH
8
14
pin 1 index
E
1
7
0
5
10 mm
scale
DIMENSIONS (inch dimensions are derived from the original mm dimensions)
UNIT
A
max.
A1
min.
A2
max.
b
b1
c
D (1)
E (1)
e
e1
L
ME
MH
w
Z (1)
max.
mm
4.2
0.51
3.2
1.73
1.13
0.53
0.38
0.36
0.23
19.50
18.55
6.48
6.20
2.54
7.62
3.60
3.05
8.25
7.80
10.0
8.3
0.254
2.2
inches
0.17
0.02
0.13
0.068
0.044
0.021
0.015
0.014
0.009
0.77
0.73
0.26
0.24
0.1
0.3
0.14
0.12
0.32
0.31
0.39
0.33
0.01
0.087
Note
1. Plastic or metal protrusions of 0.25 mm (0.01 inch) maximum per side are not included.
Fig 9.
REFERENCES
OUTLINE
VERSION
IEC
JEDEC
JEITA
SOT27-1
050G04
MO-001
SC-501-14
EUROPEAN
PROJECTION
ISSUE DATE
99-12-27
03-02-13
Package outline SOT27-1 (DIP14)
74HC21_5
Product data sheet
© NXP B.V. 2009. All rights reserved.
Rev. 05 — 7 May 2009
8 of 14
74HC21
NXP Semiconductors
Dual 4-input AND gate
SO14: plastic small outline package; 14 leads; body width 3.9 mm
SOT108-1
D
E
A
X
c
y
HE
v M A
Z
8
14
Q
A2
A
(A 3)
A1
pin 1 index
θ
Lp
1
L
7
e
detail X
w M
bp
0
2.5
5 mm
scale
DIMENSIONS (inch dimensions are derived from the original mm dimensions)
UNIT
A
max.
A1
A2
A3
bp
c
D (1)
E (1)
e
HE
L
Lp
Q
v
w
y
Z (1)
mm
1.75
0.25
0.10
1.45
1.25
0.25
0.49
0.36
0.25
0.19
8.75
8.55
4.0
3.8
1.27
6.2
5.8
1.05
1.0
0.4
0.7
0.6
0.25
0.25
0.1
0.7
0.3
0.01
0.019 0.0100 0.35
0.014 0.0075 0.34
0.16
0.15
0.010 0.057
inches 0.069
0.004 0.049
0.05
0.244
0.039
0.041
0.228
0.016
0.028
0.024
0.01
0.01
0.028
0.004
0.012
θ
o
8
o
0
Note
1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included.
REFERENCES
OUTLINE
VERSION
IEC
JEDEC
SOT108-1
076E06
MS-012
JEITA
EUROPEAN
PROJECTION
ISSUE DATE
99-12-27
03-02-19
Fig 10. Package outline SOT108-1 (SO14)
74HC21_5
Product data sheet
© NXP B.V. 2009. All rights reserved.
Rev. 05 — 7 May 2009
9 of 14
74HC21
NXP Semiconductors
Dual 4-input AND gate
SSOP14: plastic shrink small outline package; 14 leads; body width 5.3 mm
D
SOT337-1
E
A
X
c
y
HE
v M A
Z
8
14
Q
A2
A
(A 3)
A1
pin 1 index
θ
Lp
L
7
1
detail X
w M
bp
e
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
UNIT
A
max.
A1
A2
A3
bp
c
D (1)
E (1)
e
HE
L
Lp
Q
v
w
y
Z (1)
θ
mm
2
0.21
0.05
1.80
1.65
0.25
0.38
0.25
0.20
0.09
6.4
6.0
5.4
5.2
0.65
7.9
7.6
1.25
1.03
0.63
0.9
0.7
0.2
0.13
0.1
1.4
0.9
8
o
0
o
Note
1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.
OUTLINE
VERSION
SOT337-1
REFERENCES
IEC
JEDEC
JEITA
EUROPEAN
PROJECTION
ISSUE DATE
99-12-27
03-02-19
MO-150
Fig 11. Package outline SOT337-1 (SSOP14)
74HC21_5
Product data sheet
© NXP B.V. 2009. All rights reserved.
Rev. 05 — 7 May 2009
10 of 14
74HC21
NXP Semiconductors
Dual 4-input AND gate
TSSOP14: plastic thin shrink small outline package; 14 leads; body width 4.4 mm
SOT402-1
E
D
A
X
c
y
HE
v M A
Z
8
14
Q
(A 3)
A2
A
A1
pin 1 index
θ
Lp
L
1
7
e
detail X
w M
bp
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
UNIT
A
max.
A1
A2
A3
bp
c
D (1)
E (2)
e
HE
L
Lp
Q
v
w
y
Z (1)
θ
mm
1.1
0.15
0.05
0.95
0.80
0.25
0.30
0.19
0.2
0.1
5.1
4.9
4.5
4.3
0.65
6.6
6.2
1
0.75
0.50
0.4
0.3
0.2
0.13
0.1
0.72
0.38
8
o
0
o
Notes
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
2. Plastic interlead protrusions of 0.25 mm maximum per side are not included.
OUTLINE
VERSION
SOT402-1
REFERENCES
IEC
JEDEC
JEITA
EUROPEAN
PROJECTION
ISSUE DATE
99-12-27
03-02-18
MO-153
Fig 12. Package outline SOT402-1 (TSSOP14)
74HC21_5
Product data sheet
© NXP B.V. 2009. All rights reserved.
Rev. 05 — 7 May 2009
11 of 14
74HC21
NXP Semiconductors
Dual 4-input AND gate
13. Abbreviations
Table 10.
Abbreviations
Acronym
Description
CMOS
Complementary Metal Oxide Semiconductor
DUT
Device Under Test
ESD
ElectroStatic Discharge
HBM
Human Body Model
MM
Machine Model
TTL
Transistor-Transistor Logic
14. Revision history
Table 11.
Revision history
Document ID
Release date
Data sheet status
Change notice
Supersedes
74HC21_5
20090507
Product data sheet
-
74HC21_4
Modifications:
Table 1: Type number 74HCT21PW changed to 74HC21PW.
74HC21_4
20090407
Modifications:
Product data sheet
-
74HC21_3
•
The format of this data sheet has been redesigned to comply with the new identity guidelines
of NXP Semiconductors.
•
•
Legal texts have been adapted to the new company name where appropriate.
Added type number 74HC21PW (TSSOP14 package).
74HC21_3
20041112
Product data sheet
-
74HC_HCT21_CNV_2
74HC_HCT21_CNV_2
19970828
Product specification
-
74HC_HCT21_1
74HC_HCT21_1
19901201
Product specification
-
-
74HC21_5
Product data sheet
© NXP B.V. 2009. All rights reserved.
Rev. 05 — 7 May 2009
12 of 14
74HC21
NXP Semiconductors
Dual 4-input AND gate
15. Legal information
15.1 Data sheet status
Document status[1][2]
Product status[3]
Definition
Objective [short] data sheet
Development
This document contains data from the objective specification for product development.
Preliminary [short] data sheet
Qualification
This document contains data from the preliminary specification.
Product [short] data sheet
Production
This document contains the product specification.
[1]
Please consult the most recently issued document before initiating or completing a design.
[2]
The term ‘short data sheet’ is explained in section “Definitions”.
[3]
The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.
15.2 Definitions
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liability for the consequences of
use of such information.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is intended
for quick reference only and should not be relied upon to contain detailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall prevail.
15.3 Disclaimers
General — Information in this document is believed to be accurate and
reliable. However, NXP Semiconductors does not give any representations or
warranties, expressed or implied, as to the accuracy or completeness of such
information and shall have no liability for the consequences of use of such
information.
Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
Suitability for use — NXP Semiconductors products are not designed,
authorized or warranted to be suitable for use in medical, military, aircraft,
space or life support equipment, nor in applications where failure or
malfunction of an NXP Semiconductors product can reasonably be expected
to result in personal injury, death or severe property or environmental
damage. NXP Semiconductors accepts no liability for inclusion and/or use of
NXP Semiconductors products in such equipment or applications and
therefore such inclusion and/or use is at the customer’s own risk.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty that such applications will be suitable for the
specified use without further testing or modification.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) may cause permanent
damage to the device. Limiting values are stress ratings only and operation of
the device at these or any other conditions above those given in the
Characteristics sections of this document is not implied. Exposure to limiting
values for extended periods may affect device reliability.
Terms and conditions of sale — NXP Semiconductors products are sold
subject to the general terms and conditions of commercial sale, as published
at http://www.nxp.com/profile/terms, including those pertaining to warranty,
intellectual property rights infringement and limitation of liability, unless
explicitly otherwise agreed to in writing by NXP Semiconductors. In case of
any inconsistency or conflict between information in this document and such
terms and conditions, the latter will prevail.
No offer to sell or license — Nothing in this document may be interpreted
or construed as an offer to sell products that is open for acceptance or the
grant, conveyance or implication of any license under any copyrights, patents
or other industrial or intellectual property rights.
Export control — This document as well as the item(s) described herein
may be subject to export control regulations. Export might require a prior
authorization from national authorities.
15.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks
are the property of their respective owners.
16. Contact information
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: [email protected]
74HC21_5
Product data sheet
© NXP B.V. 2009. All rights reserved.
Rev. 05 — 7 May 2009
13 of 14
74HC21
NXP Semiconductors
Dual 4-input AND gate
17. Contents
1
2
3
4
5
5.1
5.2
6
7
8
9
10
11
12
13
14
15
15.1
15.2
15.3
15.4
16
17
General description . . . . . . . . . . . . . . . . . . . . . . 1
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Ordering information . . . . . . . . . . . . . . . . . . . . . 1
Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2
Pinning information . . . . . . . . . . . . . . . . . . . . . . 2
Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3
Functional description . . . . . . . . . . . . . . . . . . . 3
Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 3
Recommended operating conditions. . . . . . . . 4
Static characteristics. . . . . . . . . . . . . . . . . . . . . 4
Dynamic characteristics . . . . . . . . . . . . . . . . . . 5
Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Package outline . . . . . . . . . . . . . . . . . . . . . . . . . 8
Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Revision history . . . . . . . . . . . . . . . . . . . . . . . . 12
Legal information. . . . . . . . . . . . . . . . . . . . . . . 13
Data sheet status . . . . . . . . . . . . . . . . . . . . . . 13
Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Contact information. . . . . . . . . . . . . . . . . . . . . 13
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
© NXP B.V. 2009.
All rights reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: [email protected]
Date of release: 7 May 2009
Document identifier: 74HC21_5