INTEGRATED CIRCUITS DATA SHEET 74LVC2G07 Buffers with open-drain outputs Product specification Supersedes data of 2004 Mar 19 2004 Sep 08 Philips Semiconductors Product specification Buffers with open-drain outputs 74LVC2G07 FEATURES DESCRIPTION • Wide supply voltage range from 1.65 V to 5.5 V The 74LVC2G07 is a high-performance, low-power, low-voltage, Si-gate CMOS device superior to most advanced CMOS compatible TTL families. • 5 V tolerant input/output for interfacing with 5 V logic • High noise immunity Input can be driven from either 3.3 V or 5 V devices. This feature allows the use of this device in a mixed 3.3 V and 5 V environment. • Complies with JEDEC standard: – JESD8-7 (1.65 V to 1.95 V) – JESD8-5 (2.3 V to 2.7 V) Schmitt trigger action at all inputs makes the circuit tolerant for slower input rise and fall time. – JESD8B/JESD36 (2.7 V to 3.6 V). • −24 mA output drive (VCC = 3.0 V) This device is fully specified for partial power-down applications using Ioff. The Ioff circuitry disables the output, preventing the damaging backflow current through the device when it is powered down. • CMOS low power consumption • Latch-up performance exceeds 250 mA • Direct interface with TTL levels • Inputs accept voltages up to 5 V The 74LVC2G07 provides two non-inverting buffers. • Multiple package options The output of the device is an open drain and can be connected to other open-drain outputs to implement active-LOW wired-OR or active-HIGH wired-AND functions. • ESD protection: – HBM EIA/JESD22-A114-B exceeds 2000 V – MM EIA/JESD22-A115-A exceeds 200 V. • Specified from −40 °C to +85 °C and −40 °C to +125 °C. QUICK REFERENCE DATA GND = 0 V; Tamb = 25 °C. SYMBOL tPLZ/tPZL PARAMETER CONDITIONS propagation delay input nA to output nY VCC = 1.8 V; CL = 30 pF; RL = 1 kΩ CI input capacitance CPD power dissipation capacitance per gate UNIT 3.5 ns VCC = 2.5 V; CL = 30 pF; RL = 500 Ω 2.4 ns VCC = 2.7 V; CL = 50 pF; RL = 500 Ω 2.3 ns VCC = 3.3 V; CL = 50 pF; RL = 500 Ω 2.6 ns VCC = 5.0 V; CL = 50 pF; RL = 500 Ω 1.5 ns 2.5 pF 6.5 pF VCC = 3.3 V; notes 1 and 2 Notes 1. CPD is used to determine the dynamic power dissipation (PD in µW). PD = CPD × VCC2 × fi × N + ∑(CL × VCC2 × fo) where: fi = input frequency in MHz; fo = output frequency in MHz; CL = output load capacitance in pF; VCC = supply voltage in Volts; N = total load switching outputs; ∑(CL × VCC2 × fo) = sum of outputs. 2. The condition is VI = GND to VCC. 2004 Sep 08 TYPICAL 2 Philips Semiconductors Product specification Buffers with open-drain outputs 74LVC2G07 FUNCTION TABLE See note 1. INPUT OUTPUT nA nY L L H Z Note 1. H = HIGH voltage level; L = LOW voltage level; Z = high-impedance OFF-state. ORDERING INFORMATION PACKAGE TYPE NUMBER TEMPERATURE RANGE PINS PACKAGE MATERIAL CODE MARKING 74LVC2G07GW −40 °C to +125 °C 6 SC-88 plastic SOT363 V7 74LVC2G07GV −40 °C to +125 °C 6 SC-74 plastic SOT457 V07 74LVC2G07GM −40 °C to +125 °C 6 XSON6 plastic SOT886 V7 PINNING PIN SYMBOL DESCRIPTION 1 1A data input 2 GND ground (0 V) 3 2A data input 4 2Y data output 5 VCC supply voltage 6 1Y data output 07 1A 1 GND 2 2A 3 07 6 1Y 5 VCC 4 2Y 1A 1 6 1Y GND 2 5 VCC 2A 3 4 2Y 001aab670 001aab671 Transparent top view Fig.1 Pin configuration SC-88 and SC-74. 2004 Sep 08 Fig.2 Pin configuration XSON6. 3 Philips Semiconductors Product specification Buffers with open-drain outputs 74LVC2G07 handbook, halfpage handbook, halfpage 1 1A 1Y 6 3 2A 2Y 4 1A 2A 1 6 3 4 MNB092 1Y 2Y MNB093 Fig.3 Logic symbol. Fig.4 IEEE/IEC logic symbol. RECOMMENDED OPERATING CONDITIONS SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT VCC supply voltage 1.65 5.5 V VI input voltage 0 5.5 V VO output voltage active mode 0 VCC V VCC = 0 V; Power-down mode 0 5.5 V Tamb operating ambient temperature −40 +125 °C tr, tf input rise and fall times VCC = 1.65 V to 2.7 V 0 20 ns/V VCC = 2.7 V to 5.5 V 0 10 ns/V LIMITING VALUES In accordance with the Absolute Maximum Rating System (IEC 60134); voltages are referenced to GND (ground = 0 V). SYMBOL PARAMETER CONDITIONS MIN. −0.5 MAX. VCC supply voltage IIK input diode current VI < 0 V − −50 mA VI input voltage note 1 −0.5 +6.5 V IOK output diode current VO < 0 V − −50 mA VO output voltage active mode; notes 1 and 2 −0.5 +6.5 V Power-down mode; notes 1 and 2 −0.5 +6.5 V 50 mA IO output source or sink current VO = 0 V to 6.5 V − +6.5 UNIT V ICC, IGND VCC or GND current − ±100 mA Tstg storage temperature −65 +150 °C Ptot power dissipation − 300 mW Tamb = −40 °C to +125 °C Notes 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed. 2. When VCC = 0 V (Power-down mode), the output voltage can be 5.5 V in normal operation. 2004 Sep 08 4 Philips Semiconductors Product specification Buffers with open-drain outputs 74LVC2G07 DC CHARACTERISTICS At recommended operating conditions; voltages are referenced to GND (ground = 0 V). TEST CONDITIONS SYMBOL PARAMETER MIN. TYP. MAX. UNIT VCC (V) OTHER Tamb = −40 °C to +85 °C; note 1 VIH VIL VOL HIGH-level input voltage LOW-level input voltage 1.65 to 1.95 0.65 × VCC − − V 2.3 to 2.7 1.7 − − V 2.7 to 3.6 2.0 − − V 4.5 to 5.5 0.7 × VCC − − V 1.65 to 1.95 − − 0.35 × VCC V 2.3 to 2.7 − − 0.7 V 2.7 to 3.6 − − 0.8 V 4.5 to 5.5 − − 0.3 × VCC V LOW-level output voltage VI = VIH or VIL IO = 100 µA 1.65 to 5.5 − − 0.1 V IO = 4 mA 1.65 − − 0.45 V IO = 8 mA 2.3 − − 0.3 V IO = 12 mA 2.7 − − 0.4 V IO = 24 mA 3.0 − − 0.55 V IO = 32 mA 4.5 − − 0.55 V 1.65 to 5.5 − ±0.1 ±5 µA ILI input leakage current IOZ output OFF-state current VI = VIH or VIL; VO = VCC or GND 5.5 − ±0.1 ±10 µA Ioff power OFF leakage current 0 − ±0.1 ±10 µA ICC quiescent supply current VI = VCC or GND; IO = 0 A 5.5 − 0.1 10 µA ∆ICC additional quiescent supply current per pin 2.3 to 5.5 − 5 500 µA 2004 Sep 08 VI = 5.5 V or GND VI or VO = 5.5 V VI = VCC − 0.6 V; IO = 0 A 5 Philips Semiconductors Product specification Buffers with open-drain outputs 74LVC2G07 TEST CONDITIONS SYMBOL PARAMETER MIN. OTHER TYP. MAX. UNIT VCC (V) Tamb = −40 °C to +125 °C VIH VIL VOL HIGH-level input voltage LOW-level input voltage 1.65 to 1.95 0.65 × VCC − − V 2.3 to 2.7 1.7 − − V 2.7 to 3.6 2.0 − − V 4.5 to 5.5 0.7 × VCC − − V 1.65 to 1.95 − − 0.35 × VCC V 2.3 to 2.7 − − 0.7 V 2.7 to 3.6 − − 0.8 V 4.5 to 5.5 − − 0.3 × VCC V IO = 100 µA 1.65 to 5.5 − − 0.1 V IO = 4 mA 1.65 − − 0.70 V IO = 8 mA 2.3 − − 0.45 V IO = 12 mA 2.7 − − 0.60 V IO = 24 mA 3.0 − − 0.80 V IO = 32 mA 4.5 − − 0.80 V LOW-level output voltage VI = VIH or VIL ILI input leakage current 1.65 to 5.5 − − ±20 µA IOZ output OFF-state current VI = VIH or VIL; VO = VCC or GND 5.5 − − ±10 µA Ioff power OFF leakage current 0 − − ±20 µA ICC quiescent supply current VI = VCC or GND; IO = 0 A 5.5 − − 40 µA ∆ICC additional quiescent supply current per pin 2.3 to 5.5 − − 5000 µA VI = 5.5 V or GND VI or VO = 5.5 V VI = VCC − 0.6 V; IO = 0 A Note 1. All typical values are measured at VCC = 3.3 V and Tamb = 25 °C. 2004 Sep 08 6 Philips Semiconductors Product specification Buffers with open-drain outputs 74LVC2G07 AC CHARACTERISTICS GND = 0 V. TEST CONDITIONS SYMBOL PARAMETER MIN. TYP. MAX. UNIT VCC (V) WAVEFORMS Tamb = −40 °C to +85 °C; note 1 tPLZ/tPZL propagation delay input nA to output nY see Figs 5 and 6 1.65 to 1.95 1.0 3.5 6.7 ns 2.3 to 2.7 0.5 2.4 4.3 ns 2.7 1.0 2.3 4.2 ns 3.0 to 3.6 0.5 2.6 3.7 ns 4.5 to 5.5 0.5 1.5 2.9 ns Tamb = −40 °C to +125 °C tPLZ/tPZL propagation delay input nA to output nY see Figs 5 and 6 1.65 to 1.95 1.0 3.5 8.4 ns 2.3 to 2.7 0.5 2.4 5.5 ns 2.7 1.0 2.3 5.3 ns 3.0 to 3.6 0.5 2.6 4.7 ns 4.5 to 5.5 0.5 1.5 3.7 ns Note 1. All typical values are measured at Tamb = 25 °C and at VCC = 1.8 V, 2.5 V, 2.7 V, 3.3 V and 5.0 V respectively. AC WAVEFORMS VI VM nA input GND t PLZ t PZL VCC nY output VM VX VOL mna528 INPUT VCC VM VX VI tr = tf 0.5 × VCC VOL + 0.15 V VCC ≤ 2.0 ns 2.3 V to 2.7 V 0.5 × VCC VOL + 0.15 V VCC ≤ 2.0 ns 2.7 V 1.5 V VOL + 0.3 V 2.7 V ≤ 2.5 ns 3.0 V to 3.6 V 1.5 V VOL + 0.3 V 2.7 V ≤ 2.5 ns 4.5 V to 5.5 V 0.5 × VCC VOL + 0.3 V VCC ≤ 2.5 ns 1.65 V to 1.95 V VOL and VOH are typical output voltage drop that occur with the output load. Fig.5 Input nA to output nY propagation delays. 2004 Sep 08 7 Philips Semiconductors Product specification Buffers with open-drain outputs 74LVC2G07 VEXT VCC VI PULSE GENERATOR RL VO D.U.T. CL RT RL mna616 VCC VI CL RL VEXT tPZL/tPLZ 1.65 V to 1.95 V VCC 30 pF 1 kΩ 2 × VCC 2.3 V to 2.7 V VCC 30 pF 500 Ω 2 × VCC 2.7 V 2.7 V 50 pF 500 Ω 6V 3.0 V to 3.6 V 2.7 V 50 pF 500 Ω 6V 4.5 V to 5.5 V VCC 50 pF 500 Ω 2 × VCC Definitions for test circuit: RL = Load resistor. CL = Load capacitance including jig and probe capacitance. RT = Termination resistance should be equal to the output impedance Zo of the pulse generator. Fig.6 Load circuitry for switching times. 2004 Sep 08 8 Philips Semiconductors Product specification Buffers with open-drain outputs 74LVC2G07 PACKAGE OUTLINES Plastic surface mounted package; 6 leads SOT363 D E B y X A HE 6 v M A 4 5 Q pin 1 index A A1 1 2 e1 3 bp c Lp w M B e detail X 0 1 2 mm scale DIMENSIONS (mm are the original dimensions) UNIT A A1 max bp c D E e e1 HE Lp Q v w y mm 1.1 0.8 0.1 0.30 0.20 0.25 0.10 2.2 1.8 1.35 1.15 1.3 0.65 2.2 2.0 0.45 0.15 0.25 0.15 0.2 0.2 0.1 OUTLINE VERSION SOT363 2004 Sep 08 REFERENCES IEC JEDEC EIAJ SC-88 9 EUROPEAN PROJECTION ISSUE DATE 97-02-28 Philips Semiconductors Product specification Buffers with open-drain outputs 74LVC2G07 Plastic surface mounted package; 6 leads SOT457 D E B y A HE 6 X v M A 4 5 Q pin 1 index A A1 c 1 2 3 Lp bp e w M B detail X 0 1 2 mm scale DIMENSIONS (mm are the original dimensions) UNIT A A1 bp c D E e HE Lp Q v w y mm 1.1 0.9 0.1 0.013 0.40 0.25 0.26 0.10 3.1 2.7 1.7 1.3 0.95 3.0 2.5 0.6 0.2 0.33 0.23 0.2 0.2 0.1 OUTLINE VERSION SOT457 2004 Sep 08 REFERENCES IEC JEDEC EIAJ SC-74 10 EUROPEAN PROJECTION ISSUE DATE 97-02-28 01-05-04 Philips Semiconductors Product specification Buffers with open-drain outputs 74LVC2G07 XSON6: plastic extremely thin small outline package; no leads; 6 terminals; body 1 x 1.45 x 0.5 mm SOT886 b 1 2 3 4× (2) L L1 e 6 5 e1 4 e1 6× A (2) A1 D E terminal 1 index area 0 1 2 mm scale DIMENSIONS (mm are the original dimensions) UNIT A (1) max A1 max b D E e e1 L L1 mm 0.5 0.04 0.25 0.17 1.5 1.4 1.05 0.95 0.6 0.5 0.35 0.27 0.40 0.32 Notes 1. Including plating thickness. 2. Can be visible in some manufacturing processes. OUTLINE VERSION SOT886 2004 Sep 08 REFERENCES IEC JEDEC JEITA EUROPEAN PROJECTION ISSUE DATE 04-07-15 04-07-22 MO-252 11 Philips Semiconductors Product specification Buffers with open-drain outputs 74LVC2G07 DATA SHEET STATUS LEVEL DATA SHEET STATUS(1) PRODUCT STATUS(2)(3) Development DEFINITION I Objective data II Preliminary data Qualification This data sheet contains data from the preliminary specification. Supplementary data will be published at a later date. Philips Semiconductors reserves the right to change the specification without notice, in order to improve the design and supply the best possible product. III Product data This data sheet contains data from the product specification. Philips Semiconductors reserves the right to make changes at any time in order to improve the design, manufacturing and supply. Relevant changes will be communicated via a Customer Product/Process Change Notification (CPCN). Production This data sheet contains data from the objective specification for product development. Philips Semiconductors reserves the right to change the specification in any manner without notice. Notes 1. Please consult the most recently issued data sheet before initiating or completing a design. 2. The product status of the device(s) described in this data sheet may have changed since this data sheet was published. The latest information is available on the Internet at URL http://www.semiconductors.philips.com. 3. For data sheets describing multiple type numbers, the highest-level product status determines the data sheet status. DEFINITIONS DISCLAIMERS Short-form specification The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook. Life support applications These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application. Limiting values definition Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 60134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Right to make changes Philips Semiconductors reserves the right to make changes in the products including circuits, standard cells, and/or software described or contained herein in order to improve design and/or performance. When the product is in full production (status ‘Production’), relevant changes will be communicated via a Customer Product/Process Change Notification (CPCN). Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no licence or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified. Application information Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification. 2004 Sep 08 12 Philips Semiconductors – a worldwide company Contact information For additional information please visit http://www.semiconductors.philips.com. Fax: +31 40 27 24825 For sales offices addresses send e-mail to: [email protected]. SCA76 © Koninklijke Philips Electronics N.V. 2004 All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights. Printed in The Netherlands R20/03/pp13 Date of release: 2004 Sep 08 Document order number: 9397 750 13775