PHILIPS 74HC133N

INTEGRATED CIRCUITS
DATA SHEET
For a complete data sheet, please also download:
• The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications
• The IC06 74HC/HCT/HCU/HCMOS Logic Package Information
• The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines
74HC133
13-input NAND gate
Product specification
File under Integrated Circuits, IC06
September 1993
Philips Semiconductors
Product specification
13-input NAND gate
74HC133
FEATURES
• Output capability: standard
• ICC category: SSI
GENERAL DESCRIPTION
The HC133 is an high-speed Si-gate CMOS device and is pin compatible with low power Schottky TTL (LSTTL).
It is specified in compliance with JEDEC standard no. 7A.
The 74HC133 provides the 13-input NAND function.
QUICK REFERENCE DATA
GND = 0 V; Tamb = 25 °C; tr = tf = 6 ns
SYMBOL
PARAMETER
CONDITIONS
tPHL/tPLH
propagation delay A..M to Y
CI
input capacitance
CPD
power dissipation per gate
TYPICAL
CL = 15 pF; VCC = 5 V
notes 1 and 2
UNIT
9
ns
3.5
pF
19
pF
Notes to the quick reference data
1. CPD is used to determine the dynamic power dissipation (PD in µW)
PD = CPD × VCC2 × fi + ∑ (CL × VCC2 × fo) where:
fi = input frequency in MHz; CL = output load capacitance in pF;
fo = output frequency in MHz; VCC = supply voltage in V;
∑ (CL × VCC2 × fo) = sum of the outputs.
2. For HC the condition is VI = GND to VCC
ORDERING INFORMATION
PACKAGES
TYPE NUMBER
PINS
PIN POSITION
MATERIAL
CODE
74HC133N
16
DIL
plastic
SOT38
74HC133D
16
SO
plastic
SOT109A
See also “74HC/HCT/HCU/HCMOS Logic Package Information”.
September 1993
2
Philips Semiconductors
Product specification
13-input NAND gate
74HC133
PINNING
PIN NO.
SYMBOL
NAME AND FUNCTION
1..7, 10.. 15
A.. G, H..M
data input
8
GND
ground (0 V)
9
Y
data output
16
VCC
positive supply voltage
Fig.1 Pin configuration.
September 1993
Fig.2 Logic symbol.
3
Fig.3 IEC logic symbol.
Philips Semiconductors
Product specification
13-input NAND gate
Fig.4
74HC133
Functional diagram;
Y = ABCDEFGHIJKLM.
Fig.5 Logic diagram.
FUNCTION TABLE
INPUTS
OUTPUT
A
B
C
D
E
F
G
H
I
J
K
L
M
Y
L
X
X
X
X
X
L
X
X
X
X
X
L
X
X
X
X
X
L
X
X
X
X
X
L
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
H
H
H
H
H
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
L
X
X
X
X
X
L
X
X
X
X
X
L
X
X
X
X
X
L
X
X
X
X
X
L
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
H
H
H
H
H
X
X
X
H
X
X
X
H
X
X
X
H
X
X
X
H
X
X
X
H
X
X
X
H
X
X
X
H
X
X
X
H
X
X
X
H
X
X
X
H
L
X
X
H
X
L
X
H
X
X
L
H
H
H
H
L
Notes
1. H = HIGH voltage level
L = LOW voltage level
X = don’t care
September 1993
4
Philips Semiconductors
Product specification
13-input NAND gate
74HC133
DC CHARACTERISTICS FOR 74HC
For the DC characteristics see “74HC/HCT/HCU/HCMOS Logic Family Specifications”.
Output capability: standard
ICC category: SSI
AC CHARACTERISTICS FOR 74HC
GND = 0 V; tf = tr = 6 ns; CL = 50 pF
Tamb (°C)
SYMBOL PARAMETER
−40 to +85
+25
TEST CONDITIONS
−40 to +125
MIN. TYP.
MAX.
MIN.
MAX.
MIN.
MAX.
UNIT
VCC
WAVEFORMS
(V)
tPHL/tPLH
propagation delay
A..M to Y
−
−
−
36
13
10
110
22
19
−
−
−
140
28
23
−
−
−
165
33
28
ns
2.0
4.5
6.0
Fig.6
tTHL/tTLH
output transition
time
−
−
−
19
7
6
75
15
13
−
−
−
95
19
16
−
−
−
110
22
19
ns
2.0
4.5
6.0
Fig.6
(1) HC: VM = 50%; VI = GND to VCC.
Fig.6
Waveforms showing the input (A, B, C, D, E, F, G, H, I, J, K, L, M) to output (Y) propagation delays and
the output transition times.
PACKAGE OUTLINES
See “74HC/HCT/HCU/HCMOS Logic Package Outlines”.
September 1993
5