INTEGRATED CIRCUITS DATA SHEET 74AVC16373 16-bit D-type transparent latch; 3.6 V tolerant; 3-state Product Specification Supersedes data of 1998 Dec 11 File under Integrated Circuits, IC24 2000 Mar 09 Philips Semiconductors Product Specification 16-bit D-type transparent latch; 3.6 V tolerant; 3-state 74AVC16373 FEATURES DESCRIPTION • Wide supply voltage range from 1.2 to 3.6 V The 74AVC16373 is a 16-bit D-type transparent latch featuring separate D-type inputs for each latch, and 3-state outputs for bus oriented applications. One Latch Enable (LE) input and one Output Enable (OE) input are provided per 8-bit section. The 74AVC16373 consist of two sections of eight D-type transparent latches with 3-state true outputs. • Complies with JEDEC standard no. 8-1A/5/7 • CMOS low power consumption • Input/output tolerant up to 3.6 V • Dynamic Controlled Output (DCO) circuit dynamically changes output impedance, resulting in noise reduction without speed degradation The 74AVC16373 is designed to have an extremely fast propagation delay and a minimum amount of power consumption. • Low inductance multiple VCC and GND pins to minimize noise and ground bounce • Supports Live Insertion. To ensure the high-impedance output state during power-up or power-down, pin OEn should be tied to VCC through a pull-up resistor (Live Insertion). A Dynamic Controlled Output (DCO) circuitry is implemented to support termination line drive during transient (see Figs 1 and 2). MNA506 MNA507 0 300 handbook, halfpage handbook, halfpage I OH (mA) I OL (mA) 3.3 V 1.8 V −100 200 2.5 V 2.5 V −200 100 1.8 V 3.3 V −300 Fig.1 0 0 1 2 3 VOH (V) 4 0 Output voltage as a function of the HIGH-level output current. 2000 Mar 09 Fig.2 2 1 2 3 VOL (V) Output voltage as a function of the LOW-level output current. 4 Philips Semiconductors Product Specification 16-bit D-type transparent latch; 3.6 V tolerant; 3-state 74AVC16373 QUICK REFERENCE DATA GND = 0 V; Tamb = 25 °C; tr = tf ≤ 2.0 ns. SYMBOL tPHL/tPLH PARAMETER CONDITIONS propagation delay nDn to nQn CI input capacitance CPD power dissipation capacitance per buffer TYP. UNIT VCC = 1.2 V 3.6 ns VCC = 1.5 V 3.1 ns VCC = 1.8 V 2.2 ns VCC = 2.5 V 1.6 ns VCC = 3.3 V 1.4 ns 5.0 pF outputs enabled 34 pF outputs disabled 1 pF notes 1 and 2 Notes 1. CPD is used to determine the dynamic power dissipation (PD in µW). PD = CPD × VCC2 × fi + ∑ (CL × VCC2 × fo) where: fi = input frequency in MHz; fo = output frequency in MHz; CL = output load capacitance in pF; VCC = supply voltage in Volts; ∑ (CL × VCC2 × fo) = sum of outputs. 2. The condition is VI = GND to VCC. FUNCTION TABLE See note 1. INPUTS OUTPUTS nOE LE nAn INTERNAL LATCHES Enable and read register (transparent mode) L L H H L H L H L H Latch and read register (hold mode) L L L L l h L H L H Latch register and disable outputs H H L L l h L H Z Z OPERATING MODES Note 1. H = HIGH voltage level; h = HIGH voltage level one set-up time prior to the HIGH-to-LOW LE transition; L = LOW voltage level; l = LOW voltage level one set-up time prior to the HIGH-to-LOW LE transition; Z = high impedance OFF-state. 2000 Mar 09 3 nYn Philips Semiconductors Product Specification 16-bit D-type transparent latch; 3.6 V tolerant; 3-state 74AVC16373 ORDERING AND PACKAGE INFORMATION PACKAGE TYPE NUMBER TEMPERATURE RANGE PINS PACKAGE MATERIAL CODE −40 to +85 °C 48 TSSOP plastic SOT362-1 74AVC16373DGG PINNING PIN SYMBOL DESCRIPTION 1 1OE output enable input (active LOW) 2, 3, 5, 6, 8, 9, 11 and 12 1Q0 to 1Q7 data outputs 4, 10, 15, 21, 28, 34, 39 and 45 GND ground (0 V) 7, 18, 31 and 42 VCC DC supply voltage 13, 14, 16, 17, 19, 20, 22 and 23 2Q0 to 2Q7 data outputs 24 2OE output enable input (active LOW) 25 2LE latch enable input (active HIGH) 26, 27, 29, 30, 32, 33, 35 and 36 2D7 to 2D0 data inputs 37, 38, 40, 41, 43, 44, 46 and 47 1D7 to 1D0 data inputs 48 1LE latch enable input (active HIGH) 2000 Mar 09 4 Philips Semiconductors Product Specification 16-bit D-type transparent latch; 3.6 V tolerant; 3-state 74AVC16373 handbook, halfpage 1OE 1 48 1LE 1Q0 2 47 1D0 1Q1 3 46 1D1 GND 4 45 GND 1Q2 5 44 1D2 1Q3 6 43 1D3 1 24 1OE 2OE handbook, halfpage 47 1D0 1Q0 2 46 1D1 1Q1 3 VCC 7 42 VCC 44 8 41 1D4 1D2 1Q2 5 1Q4 43 1D3 1Q3 6 1Q5 9 40 1D5 41 1D4 1Q4 8 39 GND 40 1D5 1Q5 9 38 1D6 1Q6 11 GND 10 1Q6 11 38 1D6 37 37 1D7 1D7 1Q7 12 1Q7 12 36 2D0 2Q0 13 36 2D0 35 2D1 2Q1 14 2Q1 14 35 2D1 33 2D2 2Q2 16 GND 15 34 GND 32 2D3 2Q3 17 30 2D4 2Q4 19 16373 2Q0 13 2Q2 16 33 2D2 29 2D5 2Q5 20 2Q3 17 32 2D3 27 2D6 2Q6 22 VCC 18 31 VCC 26 2D7 2Q7 23 2Q4 19 30 2D4 2Q5 20 29 2D5 GND 21 28 GND 2Q6 22 27 2D6 2Q7 23 26 2D7 2OE 24 25 2LE 1LE 2LE 48 25 MNA547 MNA541 Fig.3 Pin configuration. 2000 Mar 09 Fig.4 Logic symbol. 5 Philips Semiconductors Product Specification 16-bit D-type transparent latch; 3.6 V tolerant; 3-state handbook, halfpage 1OE 1LE 2OE 2LE 1D0 1D1 1D2 1D3 1D4 1D5 1D6 1D7 2D0 2D1 2D2 2D3 2D4 2D5 2D6 2D7 1 48 24 25 47 74AVC16373 1EN C3 2EN C4 3D 2 1 46 3 44 5 43 6 41 8 40 9 38 11 37 12 36 13 4D 2 35 14 33 16 32 17 30 19 29 20 27 22 26 23 1Q0 1Q1 1Q2 1Q3 1Q4 1Q5 1Q6 1Q7 2Q0 2Q1 2Q2 2Q3 2Q4 2Q5 2Q6 2Q7 MNA546 Fig.5 IEEE/IEC logic symbol. handbook, full pagewidth 1D0 D Q 1Q0 2D0 LATCH 9 LE LE 2LE 1OE 2OE to 7 other channels to 7 other channels Fig.6 Logic diagram. 2000 Mar 09 Q LATCH 1 1LE MNA545 D 6 2Q0 Philips Semiconductors Product Specification 16-bit D-type transparent latch; 3.6 V tolerant; 3-state 74AVC16373 RECOMMENDED OPERATING CONDITIONS SYMBOL VCC PARAMETER DC supply voltage CONDITIONS according to JEDEC Low Voltage Standards for low-voltage applications VI DC input voltage VO DC output voltage Tamb operating ambient temperature tr, tf input rise and fall time ratios MIN. MAX. UNIT 1.4 1.6 V 1.65 1.95 V 2.3 2.7 V 3.0 3.6 V 1.2 3.6 V 0 3.6 V output 3-state 0 3.6 V output HIGH or LOW state 0 VCC V in free air −40 +85 °C VCC = 1.4 to 1.6 V 0 40 ns/V VCC = 1.65 to 2.3 V 0 30 ns/V VCC = 2.3 to 3.0 V 0 20 ns/V VCC = 3.0 to 3.6 V 0 10 ns/V LIMITING VALUES In accordance with the Absolute Maximum Rating System (IEC 60134); voltages are referenced to GND (ground = 0 V). SYMBOL PARAMETER VCC DC supply voltage CONDITIONS MIN. MAX. UNIT −0.5 +4.6 V IIK DC input diode current VI < 0 − −50 mA VI DC input voltage for inputs; note 1 −0.5 +4.6 V IOK DC output clamping diode current VO < 0 − −50 mA VO DC output voltage output HIGH or LOW state; note 1 −0.5 IO DC output sink current ICC, IGND DC VCC or GND current Tstg storage temperature PD power dissipation per package VCC + 0.5 V output 3-state; note 1 −0.5 +4.6 V VO = 0 to VCC − 50 mA − ±100 mA −65 +150 °C − 500 mW for temperature range: −40 to +85 °C; note 2 Notes 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed. 2. Above 60 °C the value of PD derates linearly with 5.5 mW/K. 2000 Mar 09 7 Philips Semiconductors Product Specification 16-bit D-type transparent latch; 3.6 V tolerant; 3-state 74AVC16373 DC CHARACTERISTICS Over recommended operating conditions; voltages are referenced to GND (ground = 0 V). Tamb = −40 to +85 °C TEST CONDITIONS SYMBOL PARAMETER OTHER VIH VIL VOH VOL HIGH-level input voltage LOW-level output voltage TYP.(1) MIN. UNIT MAX. 1.2 VCC − − V 1.4 to 1.6 0.65 × VCC 0.9 − V 1.65 to 1.95 0.65 × VCC 0.9 − V 2.3 to 2.7 1.2 − V 1.7 3.0 to 3.6 2.0 1.5 − V 1.2 − − GND V 1.4 to 1.6 − 0.9 0.35 × VCC V 1.65 to 1.95 − 0.9 0.35 × VCC V 2.3 to 2.7 − 1.2 0.7 V 3.0 to 3.6 − 1.5 0.8 V IO = −100 µA 1.65 to 3.6 VCC − 0.20 VCC − V IO = −3 mA 1.4 VCC − 0.35 VCC − 0.23 − V IO = −4 mA 1.65 VCC − 0.45 VCC − 0.25 − V IO = −8 mA 2.3 VCC − 0.55 VCC − 0.38 − V IO = −12 mA 3.0 VCC − 0.70 VCC − 0.48 − V LOW-level input voltage HIGH-level output voltage VCC (V) VI = VIH or VIL VI = VIH or VIL IO = 100 µA 1.65 to 3.6 − GND 0.20 V IO = 3 mA 1.4 − 0.18 0.35 V IO = 4 mA 1.65 − 0.22 0.45 V IO = 8 mA 2.3 − 0.37 0.55 V IO = 2 mA 3.0 − 0.51 0.70 V II input leakage current per pin VI = VCC or GND 1.4 to 3.6 − 0.1 2.5 µA Ioff power-off leakage current VI or VO = 3.6 V 0 − 0.1 ±10 µA IIHZ/IILZ input current for common I/O pins VI = VCC or GND 1.4 to 3.6 − 0.1 12.5 µA IOZ 3-state output OFF−state current VI = VIH or VIL; VO = VCC or GND 1.4 to 2.7 − 0.1 5 µA 3.0 to 3.6 − 0.1 10 µA ICC quiescent supply current VI = VCC or GND; IO = 0 1.4 to 2.7 − 0.1 20 µA 3.0 to 3.6 − 0.2 40 µA Note 1. All typical values are measured at Tamb = 25 °C. 2000 Mar 09 8 Philips Semiconductors Product Specification 16-bit D-type transparent latch; 3.6 V tolerant; 3-state 74AVC16373 AC CHARACTERISTICS GND = 0 V; tr = tf ≤ 2.0 ns. Tamb = −40 to +85 °C TEST CONDITIONS SYMBOL PARAMETER WAVEFORMS tPHL/tPLH propagation delay nDn to nQn propagation delay nLE to nQn tPZH/tPZL tPHZ/tPLZ tW tsu 3-state output enable time nOE to nQn 3-state output disable time nOE to nQn nLE pulse width HIGH set-up time nDn to nLE see Figs 7 and 11 see Figs 8 and 11 see Figs 9 and 11 see Figs 9 and 11 see Figs 8 and 11 see Figs 10 and 11 VCC (V) MIN. − ns 1.40 to 1.60 1.2 3.1 6.8 ns 1.65 to 1.95 1.0 2.2 5.7 ns 2.3 to 2.7 0.7 1.6 3.3 ns 3.0 to 3.6 0.7 1.4 2.8 ns 1.2 − 3.6 − ns 1.40 to 1.60 2.5 3.1 9.4 ns 1.65 to 1.95 2.3 2.2 7.8 ns 2.3 to 2.7 1.3 1.6 4.2 ns 3.0 to 3.6 0.7 1.4 3.9 ns 1.2 − 5.9 − ns 1.40 to 1.60 1.6 4.2 8.8 ns 1.65 to 1.95 1.6 3.5 6.7 ns 2.3 to 2.7 2.4 4.3 ns 1.4 3.0 to 3.6 0.7 2.0 3.4 ns 1.2 − 5.8 − ns 1.40 to 1.60 2.5 4.6 9.4 ns 1.65 to 1.95 2.3 3.6 7.8 ns 2.3 to 2.7 1.3 1.9 4.2 ns 3.0 to 3.6 1.2 2.1 3.9 ns 1.2 − 2.4 − ns 1.40 to 1.60 − 1.9 − ns 1.65 to 1.95 2.2 1.7 − ns 2.3 to 2.7 1.6 − ns 2.0 3.0 to 3.6 1.8 1.4 − ns 1.2 − 0.4 − ns 0.2 − ns 1.65 to 1.95 1.1 0.1 − ns 2.3 to 2.7 +0.9 −0.1 − ns 3.0 to 3.6 +0.8 −0.1 − ns 1.2 − 1.40 to 1.60 1.2 th hold time nDn to nLE see Figs 10 and 11 −0.2 − ns 1.40 to 1.60 +1.1 −0.1 − ns 1.65 to 1.95 1.1 0.0 − ns 2.3 to 2.7 1.1 0.1 − ns 3.0 to 3.6 1.0 0.2 − ns Note 1. All typical values are measured at Tamb = 25 °C and at VCC respectively 1.2, 1.5, 1.8, 2.5 and 3.3 V. 2000 Mar 09 9 UNIT MAX. 3.6 1.2 − TYP.(1) Philips Semiconductors Product Specification 16-bit D-type transparent latch; 3.6 V tolerant; 3-state 74AVC16373 AC WAVEFORMS VI handbook, full pagewidth nDn input VM GND t PHL t PLH VOH VM nQn output VOL VCC VM MNA544 VI ≤2.3 to 2.7 V 0.5 × VCC VCC 3.0 to 3.6 V 0.5 × VCC VCC VOL and VOH are typical output voltage drop that occur with the output load. Fig.7 The input (nDn) to output (nQn) propagation delay. VI handbook, full pagewidth nLE input VM VM GND tW t PHL t PLH VOH nQn output VM VOL VCC VM MNA543 VI ≤2.3 to 2.7 V 0.5 × VCC VCC 3.0 to 3.6 V 0.5 × VCC VCC VOL and VOH are typical output voltage drop that occur with the output load. Fig.8 The latch enable input (nLE) pulse width to output (nQn) propagation delays. 2000 Mar 09 10 Philips Semiconductors Product Specification 16-bit D-type transparent latch; 3.6 V tolerant; 3-state 74AVC16373 VI handbook, full pagewidth nOE input VM GND t PLZ t PZL VCC output LOW-to-OFF OFF-to-LOW VM VX VOL t PZH t PHZ VOH VY output HIGH-to-OFF OFF-to-HIGH GND VM outputs enabled outputs enabled outputs disabled MNA478 VCC VM VX VY VI ≤2.3 to 2.7 V 0.5 × VCC VOL + 0.15 V VOH − 0.15 V VCC 3.0 to 3.6 V 0.5 × VCC VOL + 0.3 V VOH − 0.3 V VCC VOL and VOH are typical output voltage drop that occur with the output load. Fig.9 3-state enable and disable times. VI handbook, full pagewidth nDn input VM GND th th t su t su VI nLE input VM GND MNA542 VCC VM VI ≤2.3 to 2.7 V 0.5 × VCC VCC 0.5 × VCC VCC 3.0 to 3.6 V The shaded areas indicate when the input is permitted to change for predictable output performance. Fig.10 Data set-up and hold times for nDn input to nLE input. 2000 Mar 09 11 Philips Semiconductors Product Specification 16-bit D-type transparent latch; 3.6 V tolerant; 3-state 74AVC16373 S1 handbook, full pagewidth VCC PULSE GENERATOR VI 2 × VCC open GND R load VO D.U.T. CL RT R load MNA505 VCC (V) VI Rload CL 1.2 VCC 2000 Ω 15 pF 1.4 to 1.6 VCC 2000 Ω 15 pF tPLH/tPHL open 1.65 to 1.95 VCC 1000 Ω 30 pF tPLZ/tPZL 2 × VCC 2.3 to 2.7 VCC 500 Ω 30 pF tPHZ/tPZH GND 3.0 to 3.6 VCC 500 Ω 30 pF TEST S1 Fig.11 Load circuitry for switching times. 2000 Mar 09 12 Philips Semiconductors Product Specification 16-bit D-type transparent latch; 3.6 V tolerant; 3-state 74AVC16373 PACKAGE OUTLINE TSSOP48: plastic thin shrink small outline package; 48 leads; body width 6.1 mm SOT362-1 E D A X c HE y v M A Z 48 25 Q A2 (A 3) A1 pin 1 index A θ Lp L 1 detail X 24 w M bp e 2.5 0 5 mm scale DIMENSIONS (mm are the original dimensions). UNIT A max. A1 A2 A3 bp c D (1) E (2) e HE L Lp Q v w y Z θ mm 1.2 0.15 0.05 1.05 0.85 0.25 0.28 0.17 0.2 0.1 12.6 12.4 6.2 6.0 0.5 8.3 7.9 1 0.8 0.4 0.50 0.35 0.25 0.08 0.1 0.8 0.4 8 0o Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT362-1 2000 Mar 09 REFERENCES IEC JEDEC EIAJ EUROPEAN PROJECTION ISSUE DATE 95-02-10 99-12-27 MO-153 13 o Philips Semiconductors Product Specification 16-bit D-type transparent latch; 3.6 V tolerant; 3-state SOLDERING 74AVC16373 If wave soldering is used the following conditions must be observed for optimal results: Introduction to soldering surface mount packages • Use a double-wave soldering method comprising a turbulent wave with high upward pressure followed by a smooth laminar wave. This text gives a very brief insight to a complex technology. A more in-depth account of soldering ICs can be found in our “Data Handbook IC26; Integrated Circuit Packages” (document order number 9398 652 90011). • For packages with leads on two sides and a pitch (e): – larger than or equal to 1.27 mm, the footprint longitudinal axis is preferred to be parallel to the transport direction of the printed-circuit board; There is no soldering method that is ideal for all surface mount IC packages. Wave soldering is not always suitable for surface mount ICs, or for printed-circuit boards with high population densities. In these situations reflow soldering is often used. – smaller than 1.27 mm, the footprint longitudinal axis must be parallel to the transport direction of the printed-circuit board. Reflow soldering The footprint must incorporate solder thieves at the downstream end. Reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. • For packages with leads on four sides, the footprint must be placed at a 45° angle to the transport direction of the printed-circuit board. The footprint must incorporate solder thieves downstream and at the side corners. Several methods exist for reflowing; for example, infrared/convection heating in a conveyor type oven. Throughput times (preheating, soldering and cooling) vary between 100 and 200 seconds depending on heating method. During placement and before soldering, the package must be fixed with a droplet of adhesive. The adhesive can be applied by screen printing, pin transfer or syringe dispensing. The package can be soldered after the adhesive is cured. Typical reflow peak temperatures range from 215 to 250 °C. The top-surface temperature of the packages should preferable be kept below 230 °C. Typical dwell time is 4 seconds at 250 °C. A mildly-activated flux will eliminate the need for removal of corrosive residues in most applications. Wave soldering Manual soldering Conventional single wave soldering is not recommended for surface mount devices (SMDs) or printed-circuit boards with a high component density, as solder bridging and non-wetting can present major problems. Fix the component by first soldering two diagonally-opposite end leads. Use a low voltage (24 V or less) soldering iron applied to the flat part of the lead. Contact time must be limited to 10 seconds at up to 300 °C. To overcome these problems the double-wave soldering method was specifically developed. When using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 °C. 2000 Mar 09 14 Philips Semiconductors Product Specification 16-bit D-type transparent latch; 3.6 V tolerant; 3-state 74AVC16373 Suitability of surface mount IC packages for wave and reflow soldering methods SOLDERING METHOD PACKAGE REFLOW(1) WAVE BGA, LFBGA, SQFP, TFBGA not suitable suitable(2) HBCC, HLQFP, HSQFP, HSOP, HTQFP, HTSSOP, SMS not PLCC(3), SO, SOJ suitable LQFP, QFP, TQFP SSOP, TSSOP, VSO suitable suitable suitable not recommended(3)(4) suitable not recommended(5) suitable Notes 1. All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the maximum temperature (with respect to time) and body size of the package, there is a risk that internal or external package cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). For details, refer to the Drypack information in the “Data Handbook IC26; Integrated Circuit Packages; Section: Packing Methods”. 2. These packages are not suitable for wave soldering as a solder joint between the printed-circuit board and heatsink (at bottom version) can not be achieved, and as solder may stick to the heatsink (on top version). 3. If wave soldering is considered, then the package must be placed at a 45° angle to the solder wave direction. The package footprint must incorporate solder thieves downstream and at the side corners. 4. Wave soldering is only suitable for LQFP, TQFP and QFP packages with a pitch (e) equal to or larger than 0.8 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm. 5. Wave soldering is only suitable for SSOP and TSSOP packages with a pitch (e) equal to or larger than 0.65 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm. DEFINITIONS Data sheet status Objective specification This data sheet contains target or goal specifications for product development. Preliminary specification This data sheet contains preliminary data; supplementary data may be published later. Product specification This data sheet contains final product specifications. Limiting values Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 60134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Where application information is given, it is advisory and does not form part of the specification. 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Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights. Printed in The Netherlands 613507/02/pp16 Date of release: 2000 Mar 09 Document order number: 9397 750 06897