INTEGRATED CIRCUITS DATA SHEET For a complete data sheet, please also download: • The IC04 LOCMOS HE4000B Logic Family Specifications HEF, HEC • The IC04 LOCMOS HE4000B Logic Package Outlines/Information HEF, HEC HEF4035B MSI 4-bit universal shift register Product specification File under Integrated Circuits, IC04 January 1995 Philips Semiconductors Product specification HEF4035B MSI 4-bit universal shift register When PE is LOW, data is shifted into the first register position from J and K and all the data in the register is shifted one position to the right on the LOW to HIGH transition of CP. D-type entry is obtained by interconnecting J and K. When J = HIGH and K = LOW the first stage is in the toggle mode. When J = LOW and K = HIGH the first stage is in the hold mode. DESCRIPTION The HEF4035B is a fully synchronous edge-triggered 4-bit shift register with a clock input (CP), four synchronous parallel data inputs (P0 to P3), two synchronous serial data inputs (J, K), a synchronous parallel enable input (PE), buffered parallel outputs from all 4-bit positions (O0 to O3), a true/complement input (T/C) and an overriding asynchronous master reset input (MR). Each register is of a D-type master-slave flip-flop. The outputs (O0 to O3) are either inverting or non-inverting, depending on T/C state. With T/C HIGH, O0 to O3 are non-inverting (active HIGH) and when T/C is LOW, O0 to O3 are inverting (active LOW). Operation is synchronous (except for MR) and is edge-triggered on the LOW to HIGH transition of the CP input. When PE is HIGH, data is loaded into the register from P0 to P3 on the LOW to HIGH transition of CP. A HIGH on MR resets all four bit positions (O0 to O3 = LOW if T/C = HIGH, O0 to O3 = HIGH if T/C = LOW) independent of all other input conditions. Schmitt-trigger action in the clock input makes the circuit highly tolerant to slower clock rise and fall times. Fig.1 Functional diagram. FAMILY DATA, IDD LIMITS category MSI See Family Specifications January 1995 2 This text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here in _white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here inThis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader. white to force landscape pages to be ... Philips Semiconductors 4-bit universal shift register January 1995 3 Product specification HEF4035B MSI Fig.2 Logic diagram. Philips Semiconductors Product specification HEF4035B MSI 4-bit universal shift register HEF4035BP(N): 16-lead DIL; plastic HEF4035BD(F): 16-lead DIL; ceramic (cerdip) (SOT38-1) (SOT74) HEF4035BT(D): 16-lead SO; plastic (SOT109-1) ( ): Package Designator North America Fig.3 Pinning diagram. PINNING PE parallel enable input P0 to P3 parallel data inputs J first stage J-input (active HIGH) K first stage K-input (active LOW) CP clock input (LOW to HIGH edge-triggered) T/C true/complement input MR master reset input O0 to O3 buffered parallel outputs FUNCTION TABLES Serial operation first stage INPUTS CP X Parallel operation OUTPUT INPUTS MODE OF OPERATION OUTPUTS CP J K MR O0 + 1 H H L H L L L L H L L O0 toggle Notes L H L O0 no change X X H L 1. T/C = HIGH; PE = HIGH; MR = LOW = positive-going transition H = HIGH state (the more positive voltage) L = LOW state (the less positive voltage) X = state is immaterial P0 P1 P2 P3 O0 O1 O2 O3 D flip-flop H H H H H H H H D flip-flop L L L L L L L L reset Note 1. T/C = HIGH; PE = LOW January 1995 4 Philips Semiconductors Product specification HEF4035B MSI 4-bit universal shift register AC CHARACTERISTICS VSS = 0 V; Tamb = 25 °C; CL = 50 pF; input transition times ≤ 20 ns VDD V TYPICAL EXTRAPOLATION FORMULA SYMBOL MIN. TYP. MAX. Propagation delays CP → On HIGH to LOW 5 10 tPHL 15 5 LOW to HIGH 10 tPLH 15 MR → On HIGH to LOW 5 10 tPHL 15 5 LOW to HIGH 10 tPLH 15 T/C → On HIGH to LOW LOW to HIGH Output transition times HIGH to LOW LOW to HIGH 340 ns 143 ns + (0,55 ns/pF) CL 140 ns 59 ns + (0,23 ns/pF) CL 50 100 ns 42 ns + (0,16 ns/pF) CL 150 300 ns 123 ns + (0,55 ns/pF) CL 65 130 ns 54 ns + (0,23 ns/pF) CL 50 100 ns 42 ns + (0,16 ns/pF) CL 115 230 ns 88 ns + (0,55 ns/pF) CL 50 100 ns 39 ns + (0,23 ns/pF) CL 40 80 ns 32 ns + (0,16 ns/pF) CL 115 230 ns 88 ns + (0,55 ns/pF) CL 50 100 ns 39 ns + (0,23 ns/pF) CL 40 80 ns 32 ns + (0,16 ns/pF) CL 105 210 ns 78 ns + (0,55 ns/pF) CL 50 100 ns 39 ns + (0,23 ns/pF) CL 15 35 70 ns 27 ns + (0,16 ns/pF) CL 5 85 170 ns 58 ns + (0,55 ns/pF) CL 5 10 tPHL 45 90 ns 34 ns + (0,23 ns/pF) CL 15 35 70 ns 27 ns + (0,16 ns/pF) CL 5 60 120 ns 10 ns + 10 tPLH (1,0 ns/pF) CL 30 60 ns 9 ns + (0,42 ns/pF) CL 15 20 40 ns 6 ns + (0,28 ns/pF) CL 5 60 120 ns 10 ns + 10 10 tTHL tTLH 15 January 1995 170 70 5 (1,0 ns/pF) CL 30 60 ns 9 ns + (0,42 ns/pF) CL 20 40 ns 6 ns + (0,28 ns/pF) CL Philips Semiconductors Product specification HEF4035B MSI 4-bit universal shift register VDD V Minimum clock pulse width; LOW Minimum MR pulse width; HIGH Recovery time for MR TYPICAL EXTRAPOLATION FORMULA SYMBOL MIN. TYP. MAX. 5 80 40 ns 40 20 ns 15 30 15 ns 5 50 25 ns 10 10 tWCPL tWMRH 30 15 ns 15 20 10 ns 5 50 20 ns 40 15 ns 10 tRMR 15 25 10 ns Set-up times 5 40 5 ns Pn → CP 10 25 0 ns 15 15 0 ns 5 50 25 ns 35 15 ns 15 30 10 ns 5 55 40 ns 35 15 ns PE → CP J, K → CP 10 10 tsu tsu tsu 15 25 10 ns Hold times 5 25 10 ns Pn → CP 10 20 10 ns 15 20 10 ns 5 15 −5 ns 10 −5 ns 5 −5 ns PE → CP 10 thold thold 15 5 J, K → CP 10 thold 15 Maximum clock pulse frequency 5 10 15 VDD V Dynamic power dissipation per package (P) fmax 10 −5 ns 10 0 ns 10 0 ns 5 10 MHz 12 25 MHz 15 30 MHz see also waveforms Figs 4 and 5 TYPICAL FORMULA FOR P (µW) 5 1 000 fi + ∑ (foCL) × VDD 2 where 10 6 000 fi + ∑ (foCL) × VDD 2 fi = input freq. (MHz) 15 20 000 fi + ∑ (foCL) × VDD 2 fo = output freq. (MHz) CL = load cap. (pF) ∑ (foCL) = sum of outputs VDD = supply voltage (V) January 1995 6 This text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here in _white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here inThis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader. white to force landscape pages to be ... Philips Semiconductors 4-bit universal shift register January 1995 7 Product specification Waveforms showing minimum clock pulse width, set-up times, hold times. Set-up times and hold times are shown as positive values but may be specified as negative values. HEF4035B MSI Fig.4 Philips Semiconductors Product specification HEF4035B MSI 4-bit universal shift register APPLICATION INFORMATION Some examples of applications for the HEF4035B are: • Counters, registers, arithmetic-unit registers, shift-left/shift-right registers. • Serial-to-parallel/parallel-to-serial conversions. • Sequence generation. • Control circuits. • Code conversion. Fig.5 Waveforms showing minimum MR pulse width and MR recovery time. Fig.6 Shift-left/shift-right register. January 1995 8