Philips Semiconductors Product specification N-channel enhancement mode TrenchMOS transistor array FEATURES PHN70308 SYMBOL • 30 mΩ isolation transistor • 80 mΩ spindle transistors • TrenchMOS technology • Logic level compatible • Surface mount package QUICK REFERENCE DATA isolation FET S4 VDS = 25 V G4 ID = 5 A RDS(ON) ≤ 30 mΩ D4 G6 G7 (VGS = 10 V; isolation FET) G5 S7 S6 S5 D1 D2 D3 G1 G2 S1 RDS(ON) ≤ 80 mΩ (VGS = 10 V; spindle FETs) G3 S2 S3 GENERAL DESCRIPTION This product is used to drive high performance, three phase brushless d.c. motors in computer disk drives. The PHN70308 contains seven, n-channel enhancement mode trenchMOS transistors in a surface mounting plastic package. Six of the transistors can be configured as a three phase bridge to drive the spindle of a disk drive motor. The remaining transistor delivers power to the three phase bridge during normal operation. In the event of a power failure occurring whilst the motor is still spinning, this transistor isolates the computer power supply from the back emf generated by the motor. The PHN70308 is supplied in the surface mounting SOT341-1 (SSOP28) package. PINNING SOT341-1 (SSOP28) PIN DESCRIPTION PIN DESCRIPTION 1,3 2 4 5,7 6 8 9,11 10 12 drain 1 source 1 gate 1 drain 2 source 2 gate 2 drain 3 source 3 gate 3 source 4 gate 4 gate 5 source 5 gate 6 source 6 gate 7 source 7 drain 4 May 1999 16,17 18 20 21 23 24 26 27 13-15,19,22,25,28 1 28 1 Top view 15 14 Rev 1.000 Philips Semiconductors Product specification N-channel enhancement mode TrenchMOS transistor array PHN70308 LIMITING VALUES Limiting values in accordance with the Absolute Maximum System (IEC 134) SYMBOL PARAMETER CONDITIONS VDS VDGR VGS ID Drain-source voltage Drain-gate voltage Gate-source voltage Peak drain current per device (continuous operation) Tj = 25 ˚C to 150˚C RGS = 20 kΩ IDM Ptot Peak current per device (pulse peak value) Power dissipation per device2 Ptot Total power dissipation in normal operation2 Tstg, Tj Storage & operating temperature Tsp = 50 ˚C1 spindle FETs; δ = 33.3% Isolation FET (dc) spindle FETs isolation FET Tsp = 50 ˚C spindle FETs; δ = 33.3% isolation FET (dc) Tsp = 50 ˚C spindle FETs; δ = 33.3% isolation FET (dc) MIN. MAX. UNIT - 25 25 ± 20 V V V - 5 5 20 20 A A A A - 1.13 1.275 8 W W W - 55 150 ˚C THERMAL RESISTANCES SYMBOL PARAMETER CONDITIONS Rth j-sp Thermal resistance junction to solder point Thermal resistance junction to ambient isolation FET spindle FET device soldered to FR4 board, minimum footprint. isolation FET spindle FET Rth j-a TYP. MAX. UNIT 20 43 - K/W K/W 85 100 - K/W K/W 1 Tsp is the temperature at the soldering point of the drain leads. 2 In normal operation, the isolation FET conducts continuously whilst each of the spindle FETs conducts for 33.3% of the time. The dissipation in the isolation transistor is given by:Pisolation = I 2xRDS(ON) (isolationFET) The dissipation in each of the spindle transistors is given by:Pspindle = 0.333xI 2xRDS(ON) (spindleFET) The total dissipation under these conditions is given by:Ptot = Pisolation + 6xPspindle With the motor being driven at 5 A and assuming Tj = 150˚C, the total dissipation is:Ptot = 25x0.03x1.7 + 0.333x25x0.08x1.7x6 = 8W Switching losses are assumed to be negligible. May 1999 2 Rev 1.000 Philips Semiconductors Product specification N-channel enhancement mode TrenchMOS transistor array PHN70308 ELECTRICAL CHARACTERISTICS Tj= 25˚C unless otherwise specified SYMBOL PARAMETER V(BR)DSS VGS(TO) RDS(ON) RDS(ON) RDS(ON) IGSS IDSS Qg(tot) MIN. TYP. MAX. UNIT VGS = 0 V; ID = 10 µA 25 - - V VDS = VGS; ID = 1 mA VGS = 10 V; ID = 4 A 1.0 1.5 - V spindle FET isolation FET - 60 27 80 30 mΩ mΩ spindle FET isolation FET Drain-source on-state VGS = 10 V; ID = 4 A; Tj = 150˚C resistance spindle FET isolation FET Gate source leakage current VGS = ±20 V; VDS = 0 V Zero gate voltage drain VDS = 20 V; VGS = 0 V; current Tj = 150˚C - 95 38 150 60 mΩ mΩ - 102 46 10 10 0.1 136 51 100 100 0.5 mΩ mΩ nA nA mA ID = 1 A; VDD = 20 V; VGS = 10 V spindle FET isolation FET spindle FET isolation FET spindle FET isolation FET - 5.4 17.6 0.4 1.4 1.6 5.7 - nC nC nC nC nC nC VDD = 20 V; ID = 1 A; VGS = 10 V; RG = 6 Ω; resistive load spindle FET isolation FET spindle FET isolation FET - 5.5 11 16 45 10 20 25 60 ns ns ns ns VGS = 0 V; VDS = 20 V; f = 1 MHz spindle FET isolation FET spindle FET isolation FET spindle FET isolation FET - 180 546 70 311 36 133 - pF pF pF pF pF pF Drain-source breakdown voltage Gate threshold voltage Drain-source on-state resistance Drain-source on-state resistance Total gate charge Qgs Gate-source charge Qgd Gate-drain (Miller) charge t on Turn-on time t off Turn-off time Ciss Input capacitance Coss Output capacitance Crss Feedback capacitance May 1999 CONDITIONS VGS = 4.5 V; ID = 2 A 3 Rev 1.000 Philips Semiconductors Product specification N-channel enhancement mode TrenchMOS transistor array PHN70308 SOURCE-DRAIN DIODE LIMITING VALUES AND CHARACTERISTICS Tj = 25˚C unless otherwise specified SYMBOL PARAMETER CONDITIONS IF Continuous forward diode current Tsp = 50 ˚C IFRM trr Reverse recovery time Normalised Power Derating, Ptot (%) 90 80 70 60 50 40 30 20 10 0 20 40 60 80 100 120 MAX. UNIT - - 5 5 20 20 A A A A - 0.8 0.8 1 1 V V - 20 25 - ns ns Normalised On-state Resistance 2 1.9 1.8 1.7 1.6 1.5 1.4 1.3 1.2 1.1 1 0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0 100 0 TYP. spindle FET; δ = 33.3% isolation FET spindle FET isolation FET IF = 1.25 A; VGS = 0 V spindle FET isolation FET IF = 1.25 A; -dIF/dt = 100 A/µs; VDS = 25 V spindle FET isolation FET Repetitive peak forward diode current Diode forward voltage VF MIN. 140 160 -60 -40 -20 0 Solder Point temperature, Tsp (C) Fig.1. Normalised power dissipation. PD% = 100⋅PD/PD 25 ˚C = f(Tsp) 20 40 60 80 100 Junction temperature, Tj (C) 120 140 160 180 Fig.3. Normalised drain-source on-state resistance. RDS(ON)/RDS(ON)25 ˚C = f(Tj) Threshold Voltage, VGS(TO) (V) Normalised Current Derating, ID (%) 3 120 2.75 2.5 100 2.25 2 80 typical 1.75 1.5 60 1.25 1 40 minimum 0.75 20 0.5 0.25 0 0 0 20 40 60 80 100 120 140 160 -60 Solder Point temperature, Tsp (C) -20 0 20 40 60 80 100 120 140 160 180 Junction Temperature, Tj (C) Fig.2. Normalised continuous drain current. ID% = 100⋅ID/ID 25 ˚C = f(Tsp); conditions: VGS ≥ 10 V May 1999 -40 Fig.4. Gate threshold voltage. VGS(TO) = f(Tj); conditions: ID = 1 mA; VDS = VGS 4 Rev 1.000 Philips Semiconductors Product specification N-channel enhancement mode TrenchMOS transistor array PHN70308 Drain current, ID (A) 1.0E-01 100 Transient thermal impedance, Zth j-a (K/W) VDS = 5 V D = 0.5 1.0E-02 10 0.2 0.1 minimum 0.05 1.0E-03 1 0.02 typical P D 1.0E-04 0.1 D = tp/T tp single pulse 1.0E-05 T 0.01 1E-06 1.0E-06 0 0.5 1 1.5 2 Gate-source voltage, VGS (V) 2.5 3 1E-03 1E-02 1E-01 1E+00 1E+01 Fig.8. Transient thermal impedance (spindle FET). Zth j-sp = f(t); parameter D = tp/T Peak Pulsed Drain Current, IDM (A) 100 tp = 10 us RDS(on) = VDS/ ID 1E-04 Pulse width, tp (s) Fig.5. Sub-threshold drain current. ID = f(VGS); conditions: Tj = 25 ˚C 100 1E-05 10 Transient thermal impedance, Zth j-a (K/W) D = 0.5 0.2 10 0.1 100 us 0.05 1 1 ms 0.02 P D single pulse 1 D = tp/T tp 0.1 10 ms D.C. T 100 ms 0.01 1E-06 0.1 0.1 1 10 Drain-Source Voltage, VDS (V) 1E-04 1E-03 1E-02 1E-01 1E+00 1E+01 Pulse width, tp (s) Fig.6. Safe operating area (spindle FET) Tsp = 25˚C ID & IDM = f(VDS); IDM single pulse; parameter tp 100 1E-05 100 Fig.9. Transient thermal impedance (isolation FET). Zth j-sp = f(t); parameter D = tp/T Peak Pulsed Drain Current, IDM (A) 8 Drain Current, ID (A) 4.5 V VGS = 10 V 7 RDS(on) = VDS/ ID Tj = 25 C tp = 100 us 6 10 5 1 ms 3.6 V 4 10 ms 3.4 V D.C. 3 1 3.2 V 100 ms 2 3V 1 2.8 V 2.6 V 0.1 0 0.1 1 10 Drain-Source Voltage, VDS (V) 100 0 Fig.7. Safe operating area (isolation FET) Tsp = 25˚C ID & IDM = f(VDS); IDM single pulse; parameter tp May 1999 0.2 0.4 0.6 0.8 1 1.2 1.4 Drain-Source Voltage, VDS (V) 1.6 1.8 2 Fig.10. Typical output characteristics (spindle FET) Tj = 25 ˚C; ID = f(VDS); parameter VGS 5 Rev 1.000 Philips Semiconductors Product specification N-channel enhancement mode TrenchMOS transistor array PHN70308 Drain Current, ID (A) 10 Drain current, ID (A) VGS = 4.5 V 10 V Tj = 25 C 5 VDS > ID X RDS(ON) 9 4.5 8 4 3.6 V 7 3.5 6 3 5 3.4 V 2.5 3.2 V 1.5 2 4 3 2 0.5 2.8 V 1 150 C 1 3V 2.6 V Tj = 25 C 0 0 0 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 0.5 1 1.5 2 2 2.5 3 3.5 4 4.5 5 Gate-source voltage, VGS (V) Drain-Source Voltage, VDS (V) Fig.11. Typical output characteristics (isolation FET) Tj = 25 ˚C; ID = f(VDS); parameter VGS Fig.14. Typical transfer characteristics (spindle FET) ID = f(VGS) Drain current, ID (A) Drain-Source On Resistance, RDS(on) (Ohms) 0.5 5 3.2 V 2.8 V 3.4V Tj = 25 C 3.6 V VDS > ID X RDS(ON) 4.5 3V 4 0.4 3.5 3 0.3 2.5 2 0.2 VGS =4.5 V 1 10V 0.1 150 C 1.5 0.5 Tj = 25 C 0 0 0 0 1 2 3 4 Drain Current, ID (A) 5 6 7 Drain-Source On Resistance, RDS(on) (Ohms) 3.4V 6 2 2.5 3 3.5 4 4.5 5 Transconductance, gfs (S) VDS > ID X RDS(ON) Tj = 25 C 3.6 V 1.5 Fig.15. Typical transfer characteristics (isolation FET); ID = f(VGS) 0.2 3.2 V 1 Gate-source voltage, VGS (V) Fig.12. Typical on-state resistance (spindle FET) Tj = 25 ˚C; RDS(ON) = f(ID); parameter VGS 3V 0.5 8 0.18 5 Tj = 25 C 0.16 4 0.14 150 C 0.12 3 0.1 0.08 2 0.06 VGS =4.5 V 0.04 10V 1 0.02 0 0 0 1 2 3 4 5 Drain Current, ID (A) 6 7 8 9 0 10 Fig.13. Typical on-state resistance (isolation FET) Tj = 25 ˚C; RDS(ON) = f(ID); parameter VGS May 1999 0.5 1 1.5 2 2.5 3 Drain current, ID (A) 3.5 4 4.5 5 Fig.16. Typical transconductance (spindle FET) Tj = 25 ˚C; gfs = f(ID) 6 Rev 1.000 Philips Semiconductors Product specification N-channel enhancement mode TrenchMOS transistor array 10 PHN70308 Transconductance, gfs (S) Gate-source voltage, VGS (V) Tj = 25 C VDS > ID X RDS(ON) 9 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 8 7 150 C 6 5 4 3 2 1 0 ID = 1A Tj = 25 C VDD = 20 V 0 0 1 2 3 4 5 6 Drain current, ID (A) 7 8 9 1 2 3 4 5 Gate charge, QG (nC) 10 Fig.17. Typical transconductance (isolation FET) Tj = 25 ˚C; gfs = f(ID) 6 7 8 Fig.20. Typical turn-on gate-charge characteristics (spindle FET); VGS = f(QG) 15 Capacitances, Ciss, Coss, Crss (pF) Gate-source voltage, VGS (V) 14 1000 13 ID = 1A 12 11 Tj = 25 C 10 VDD = 20 V 9 Ciss 8 7 100 6 Coss 5 4 Crss 3 2 1 0 10 0 0.1 1 10 Drain-Source Voltage, VDS (V) 2 4 6 8 100 Fig.18. Typical capacitances (spindle FET) C = f(VDS); conditions: VGS = 0 V; f = 1 MHz 10 12 14 16 Gate charge, QG (nC) 18 20 22 24 26 Fig.21. Typical turn-on gate-charge characteristics (isolation FET); VGS = f(QG) Source-Drain Diode Current, IF (A) 5 Capacitances, Ciss, Coss, Crss (pF) VGS = 0 V 10000 4.5 4 3.5 3 2.5 1000 150 C 2 Ciss Tj = 25 C 1.5 1 Coss 0.5 Crss 0 100 0 0.1 1 10 Drain-Source Voltage, VDS (V) 100 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 Source-Drain Voltage, VSDS (V) Fig.19. Typical capacitances (isolation FET) C = f(VDS); conditions: VGS = 0 V; f = 1 MHz May 1999 0.1 Fig.22. Typical reverse diode current (spindle FET) IF = f(VSDS); conditions: VGS = 0 V; parameter Tj 7 Rev 1.000 Philips Semiconductors Product specification N-channel enhancement mode TrenchMOS transistor array PHN70308 Source-Drain Diode Current, IF (A) 10 VGS = 0 V 9 8 7 6 5 150 C 4 Tj = 25 C 3 2 1 0 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 Source-Drain Voltage, VSDS (V) Fig.23. Typical reverse diode current (isolation FET) IF = f(VSDS); conditions: VGS = 0 V; parameter Tj May 1999 8 Rev 1.000 Philips Semiconductors Product specification N-channel enhancement mode TrenchMOS transistor array PHN70308 MECHANICAL DATA SSOP28: plastic shrink small outline package; 28 leads; body width 5.3 mm D SOT341-1 E A X c HE y v M A Z 28 15 Q A2 pin 1 index A (A 3) A1 θ Lp L 1 14 w M bp e detail X 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT mm A max. A1 A2 2.0 0.21 0.05 1.80 1.65 A3 bp c D (1) E (1) 0.25 0.38 0.25 0.20 0.09 10.4 10.0 5.4 5.2 e HE 0.65 7.9 7.6 L Lp Q v w y Z (1) θ 1.25 1.03 0.63 0.9 0.7 0.2 0.13 0.1 1.1 0.7 8 0o o Note 1. Plastic or metal protrusions of 0.20 mm maximum per side are not included. OUTLINE VERSION SOT341-1 REFERENCES IEC JEDEC EIAJ EUROPEAN PROJECTION ISSUE DATE 93-09-08 95-02-04 MO-150AH Fig.24. SOT341-1 (SSOP28) surface mounting package. Notes 1. This product is supplied in anti-static packaging. The leads must be protected against static discharge during transport or handling. 2. Refer to Integrated Circuit Packages, Data Handbook IC26. 3. Epoxy meets UL94 V0 at 1/8". May 1999 9 Rev 1.000 Philips Semiconductors Product specification N-channel enhancement mode TrenchMOS transistor array PHN70308 DEFINITIONS Data sheet status Objective specification This data sheet contains target or goal specifications for product development. Preliminary specification This data sheet contains preliminary data; supplementary data may be published later. Product specification This data sheet contains final product specifications. Limiting values Limiting values are given in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of this specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Where application information is given, it is advisory and does not form part of the specification. Philips Electronics N.V. 1999 All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, it is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent or other industrial or intellectual property rights. LIFE SUPPORT APPLICATIONS These products are not designed for use in life support appliances, devices or systems where malfunction of these products can be reasonably expected to result in personal injury. Philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such improper use or sale. May 1999 10 Rev 1.000