INTEGRATED CIRCUITS DATA SHEET 74ALVC02 Quad 2-input NOR gate Product specification Supersedes data of 2003 Feb 05 2003 Jul 14 Philips Semiconductors Product specification Quad 2-input NOR gate 74ALVC02 FEATURES DESCRIPTION • Wide supply voltage range from 1.65 to 3.6 V The 74ALVC02 is a high-performance, low-power, low-voltage, Si-gate CMOS device and superior to most advanced CMOS compatible TTL families. • 3.6 V tolerant inputs/outputs • CMOS low power consumption Schmitt-trigger action at all inputs makes the circuit tolerant for slower input rise and fall times. • Direct interface with TTL levels (2.7 to 3.6 V) • Power-down mode The 74ALVC02 provides the 2-input NOR function. • Latch-up performance exceeds 250 mA • Complies with JEDEC standard: JESD8-7 (1.65 to 1.95 V) JESD8-5 (2.3 to 2.7 V) JESD8B/JESD36 (2.7 to 3.6 V). • ESD protection: HBM EIA/JESD22-A114-A exceeds 2000 V MM EIA/JESD22-A115-A exceeds 200 V. QUICK REFERENCE DATA GND = 0 V; Tamb = 25 °C. SYMBOL tPHL/tPLH PARAMETER propagation delay nA, nB to nY CI input capacitance CPD power dissipation capacitance per buffer CONDITIONS UNIT VCC = 1.8 V; CL = 30 pF; RL = 1 kΩ 2.8 ns VCC = 2.5 V; CL = 30 pF; RL = 500 Ω 2.0 ns VCC = 2.7 V; CL = 50 pF; RL = 500 Ω 2.5 ns VCC = 3.3 V; CL = 50 pF; RL = 500 Ω 2.2 ns 3.5 pF 32 pF VCC = 3.3 V; notes 1 and 2 Notes 1. CPD is used to determine the dynamic power dissipation (PD in µW). PD = CPD × VCC2 × fi × N + Σ(CL × VCC2 × fo) where: fi = input frequency in MHz; fo = output frequency in MHz; CL = output load capacitance in pF; VCC = supply voltage in Volts; N = total load switching outputs; Σ(CL × VCC2 × fo) = sum of the outputs. 2. The condition is VI = GND to VCC. 2003 Jul 14 TYPICAL 2 Philips Semiconductors Product specification Quad 2-input NOR gate 74ALVC02 ORDERING INFORMATION PACKAGE TYPE NUMBER TEMPERATURE RANGE PINS PACKAGE MATERIAL CODE SO14 plastic SOT108-1 74ALVC02D −40 to +85 °C 14 74ALVC02PW −40 to +85 °C 14 TSSOP14 plastic SOT402-1 74ALVC02BQ −40 to +85 °C 14 DHVQFN14 plastic SOT762-1 FUNCTION TABLE See note 1. INPUT OUTPUT nA nB nY L L H L H L H L L H H L Note 1. H = HIGH voltage level; L = LOW voltage level PINNING Pin SYMBOL DESCRIPTION 1 1Y data output 2 1A data input 3 1B data input 1Y 1 14 VCC 4 2Y data output 1A 2 13 4Y 5 2A data input 1B 3 12 4B 6 2B data input 2Y 4 7 GND ground (0 V) 8 3A data input 2A 5 10 3Y 9 3B data input 2B 6 9 10 3Y data output GND 7 8 3A 11 4A data input 12 4B data input 13 4Y data output 14 VCC supply voltage 2003 Jul 14 handbook, halfpage 02 11 4A 3B MNA214 Fig.1 Pin configuration SO14 and TSSOP14. 3 Philips Semiconductors Product specification Quad 2-input NOR gate handbook, halfpage 1Y VCC 1 14 74ALVC02 1A 2 13 4Y 1B 3 12 4B 2Y 4 2A 2B GND(1) 11 4A 5 10 3Y 6 9 3B Top view 7 8 GND 3A handbook, halfpage A Y B MNA215 MNA951 (1) (1) The die substrate is attached to this pad using conductive die attach material. It can not be used as a supply pin or input. Fig.2 Pin configuration DHVQFN14. Fig.3 Logic diagram (one gate). handbook, halfpage 2 ≥1 1 ≥1 4 ≥1 10 ≥1 13 3 handbook, halfpage 2 1A 3 1B 5 2A 6 2B 8 3A 9 3B 11 4A 12 4B 1Y 1 5 2Y 4 6 3Y 10 8 9 4Y 13 11 MNA216 12 MNA217 Fig.4 Function diagram. 2003 Jul 14 Fig.5 IEC logic symbol. 4 Philips Semiconductors Product specification Quad 2-input NOR gate 74ALVC02 RECOMMENDED OPERATING CONDITIONS SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT VCC supply voltage 1.65 3.6 V VI input voltage 0 3.6 V VO output voltage VCC = 1.65 to 3.6 V 0 VCC V VCC = 0 V; Power-down mode 0 4.6 V Tamb operating ambient temperature −40 +85 °C tr, tf input rise and fall times VCC = 1.65 to 2.7 V 0 20 ns/V VCC = 2.7 to 3.6 V 0 10 ns/V LIMITING VALUES In accordance with the Absolute Maximum Rating System (IEC 60134); voltages are referenced to GND (ground = 0 V). SYMBOL PARAMETER VCC supply voltage IIK input diode current VI input voltage IOK output diode current VO output voltage CONDITIONS VI < 0 VO > VCC or VO < 0 MIN. MAX. UNIT −0.5 +4.6 V − −50 mA −0.5 +4.6 V − ±50 mA notes 1 and 2 −0.5 VCC + 0.5 V Power-down mode; note 2 −0.5 +4.6 V VO = 0 to VCC − ±50 mA IO output source or sink current ICC, IGND VCC or GND current − ±100 mA Tstg storage temperature −65 +150 °C Ptot power dissipation − 500 mW Tamb = −40 to +85 °C; note 3 Notes 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed. 2. When VCC = 0 V (Power-down mode), the output voltage can be 3.6 V in normal operation. 3. For SO14 packages: above 70 °C derate linearly with 8 mW/K. For TSSOP14 packages: above 60 °C derate linearly with 5.5 mW/K. For DHVQFN14 packages: above 60 °C derate linearly with 4.5 mW/K. 2003 Jul 14 5 Philips Semiconductors Product specification Quad 2-input NOR gate 74ALVC02 DC CHARACTERISTICS At recommended operating conditions; voltages are referenced to GND (ground = 0 V). TEST CONDITIONS SYMBOL PARAMETER MIN. OTHER TYP.(1) MAX. UNIT VCC (V) Tamb = −40 to +85 °C VIH VIL VOL VOH 1.65 to 1.95 0.65 × VCC − − V 1.7 − − V 2 − − V 1.65 to 1.95 − − 0.35 × VCC V 2.3 to 2.7 − − 0.7 V 2.7 to 3.6 − − 0.8 V IO = 100 µA 1.65 to 3.6 − − 0.2 V IO = 6 mA 1.65 − 0.11 0.3 V IO = 12 mA 2.3 − 0.17 0.4 V IO = 18 mA 2.3 − 0.25 0.6 V IO = 12 mA 2.7 − 0.16 0.4 V IO = 18 mA 3.0 − 0.23 0.4 V IO = 24 mA 3.0 − 0.30 0.55 V IO = −100 µA 1.65 to 3.6 VCC − 0.2 − − V HIGH-level input voltage LOW-level input voltage LOW-level output voltage HIGH-level output voltage 2.3 to 2.7 2.7 to 3.6 VI = VIH or VIL VI = VIH or VIL IO = −6 mA 1.65 1.25 1.51 − V IO = −12 mA 2.3 1.8 2.10 − V IO = −18 mA 2.3 1.7 2.01 − V IO = −12 mA 2.7 2.2 2.53 − V IO = −18 mA 3.0 2.4 2.76 − V IO = −24 mA 3.0 2.2 2.68 − V VI = 3.6 V or GND 3.6 − ±0.1 ±5 µA ILI input leakage current Ioff power OFF leakage VI or VO = 3.6 V current 0.0 − ±0.1 ±10 µA ICC quiescent supply current 3.6 − 0.2 20 µA ∆ICC additional quiescent VI = VCC − 0.6 V; IO = 0 supply current per input pin 3.0 to 3.6 − 5 750 µA VI = VCC or GND; IO = 0 Note 1. All typical values are measured at Tamb = 25 °C. 2003 Jul 14 6 Philips Semiconductors Product specification Quad 2-input NOR gate 74ALVC02 AC CHARACTERISTICS TEST CONDITIONS SYMBOL PARAMETER MIN. WAVEFORMS TYP.(1) MAX. UNIT VCC (V) Tamb = −40 to +85 °C tPHL/tPLH propagation delay nA, nB to nY see Figs 6 and 7 1.65 to 1.95 1.0 2.8 4.7 ns 2.3 to 2.7 1.0 2.0 3.1 ns 2.7 1.0 2.5 2.9 ns 3.0 to 3.6 1.0 2.2 2.8 ns Note 1. All typical values are measured at Tamb = 25 °C. AC WAVEFORMS handbook, halfpage VI VM nA, nB input GND tPHL tPLH VOH VM nY output VOL tTHL tTLH MNA218 INPUT VCC VM VI tr = tf 1.65 to 1.95 V 0.5 × VCC VCC ≤ 2.0 ns 2.3 to 2.7 V 0.5 × VCC VCC ≤ 2.0 ns 2.7 V 1.5 V 2.7 V ≤ 2.5 ns 3.0 to 3.6 V 1.5 V 2.7 V ≤ 2.5 ns Fig.6 Inputs nA, nB to output nY propagation delay times. 2003 Jul 14 7 Philips Semiconductors Product specification Quad 2-input NOR gate 74ALVC02 VEXT handbook, full pagewidth VCC PULSE GENERATOR VI RL VO D.U.T. CL RT RL MNA616 VCC VI CL RL VEXT tPLH/tPHL tPZH/tPHZ tPZL/tPLZ 1.65 to 1.95 V VCC 30 pF 1 kΩ open GND 2 × VCC 2.3 to 2.7 V VCC 30 pF 500 Ω open GND 2 × VCC 2.7 V 2.7 V 50 pF 500 Ω open GND 6V 3.0 to 3.6 V 2.7 V 50 pF 500 Ω open GND 6V Definitions for test circuit: RL = Load resistor. CL = Load capacitance including jig and probe capacitance. RT = Termination resistance should be equal to the output impedance Zo of the pulse generator. Fig.7 Load circuitry for switching times. 2003 Jul 14 8 Philips Semiconductors Product specification Quad 2-input NOR gate 74ALVC02 PACKAGE OUTLINES SO14: plastic small outline package; 14 leads; body width 3.9 mm SOT108-1 D E A X c y HE v M A Z 8 14 Q A2 A (A 3) A1 pin 1 index θ Lp 1 L 7 e detail X w M bp 0 2.5 5 mm scale DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (1) e HE L Lp Q v w y Z (1) mm 1.75 0.25 0.10 1.45 1.25 0.25 0.49 0.36 0.25 0.19 8.75 8.55 4.0 3.8 1.27 6.2 5.8 1.05 1.0 0.4 0.7 0.6 0.25 0.25 0.1 0.7 0.3 0.01 0.019 0.0100 0.35 0.014 0.0075 0.34 0.16 0.15 0.010 0.057 inches 0.069 0.004 0.049 0.05 0.244 0.039 0.028 0.041 0.228 0.016 0.024 0.01 0.01 0.028 0.004 0.012 θ Note 1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included. REFERENCES OUTLINE VERSION IEC JEDEC SOT108-1 076E06 MS-012 2003 Jul 14 JEITA EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-19 9 o 8 0o Philips Semiconductors Product specification Quad 2-input NOR gate 74ALVC02 TSSOP14: plastic thin shrink small outline package; 14 leads; body width 4.4 mm SOT402-1 E D A X c y HE v M A Z 8 14 Q (A 3) A2 A A1 pin 1 index θ Lp L 1 7 detail X w M bp e 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (2) e HE L Lp Q v w y Z (1) θ mm 1.1 0.15 0.05 0.95 0.80 0.25 0.30 0.19 0.2 0.1 5.1 4.9 4.5 4.3 0.65 6.6 6.2 1 0.75 0.50 0.4 0.3 0.2 0.13 0.1 0.72 0.38 8 0o Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT402-1 2003 Jul 14 REFERENCES IEC JEDEC JEITA EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-18 MO-153 10 o Philips Semiconductors Product specification Quad 2-input NOR gate 74ALVC02 DHVQFN14: plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads; SOT762-1 14 terminals; body 2.5 x 3 x 0.85 mm A B D A A1 E c detail X terminal 1 index area terminal 1 index area C e1 e 2 6 y y1 C v M C A B w M C b L 1 7 Eh e 14 8 13 9 Dh X 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT A(1) max. A1 b c D (1) Dh E (1) Eh e e1 L v w y y1 mm 1 0.05 0.00 0.30 0.18 0.2 3.1 2.9 1.65 1.35 2.6 2.4 1.15 0.85 0.5 2 0.5 0.3 0.1 0.05 0.05 0.1 Note 1. Plastic or metal protrusions of 0.075 mm maximum per side are not included. REFERENCES OUTLINE VERSION IEC JEDEC JEITA SOT762-1 --- MO-241 --- 2003 Jul 14 11 EUROPEAN PROJECTION ISSUE DATE 02-10-17 03-01-27 Philips Semiconductors Product specification Quad 2-input NOR gate 74ALVC02 DATA SHEET STATUS LEVEL DATA SHEET STATUS(1) PRODUCT STATUS(2)(3) Development DEFINITION I Objective data II Preliminary data Qualification This data sheet contains data from the preliminary specification. Supplementary data will be published at a later date. Philips Semiconductors reserves the right to change the specification without notice, in order to improve the design and supply the best possible product. III Product data This data sheet contains data from the product specification. Philips Semiconductors reserves the right to make changes at any time in order to improve the design, manufacturing and supply. Relevant changes will be communicated via a Customer Product/Process Change Notification (CPCN). Production This data sheet contains data from the objective specification for product development. Philips Semiconductors reserves the right to change the specification in any manner without notice. Notes 1. Please consult the most recently issued data sheet before initiating or completing a design. 2. The product status of the device(s) described in this data sheet may have changed since this data sheet was published. The latest information is available on the Internet at URL http://www.semiconductors.philips.com. 3. For data sheets describing multiple type numbers, the highest-level product status determines the data sheet status. DEFINITIONS DISCLAIMERS Short-form specification The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook. Life support applications These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application. Limiting values definition Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 60134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Right to make changes Philips Semiconductors reserves the right to make changes in the products including circuits, standard cells, and/or software described or contained herein in order to improve design and/or performance. When the product is in full production (status ‘Production’), relevant changes will be communicated via a Customer Product/Process Change Notification (CPCN). Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no licence or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified. Application information Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification. 2003 Jul 14 12 Philips Semiconductors – a worldwide company Contact information For additional information please visit http://www.semiconductors.philips.com. Fax: +31 40 27 24825 For sales offices addresses send e-mail to: [email protected]. SCA75 © Koninklijke Philips Electronics N.V. 2003 All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights. Printed in The Netherlands 613508/02/pp13 Date of release: 2003 Jul 14 Document order number: 9397 750 11272