74ABT646A Octal bus transceiver/register; 3-state Rev. 03 — 15 March 2010 Product data sheet 1. General description The 74ABT646A high-performance BiCMOS device combines low static and dynamic power dissipation with high speed and high output drive. The 74ABT646A transceiver/register consists of bus transceiver circuits with 3-state outputs, D-type flip-flops, and control circuitry arranged for multiplexed transmission of data directly from the input bus or the internal registers. Data on the A bus or B bus will be clocked into the registers as the appropriate clock pin (CPAB or CPBA) goes HIGH. Output Enable (OE) and Direction (DIR) pins are provided to control the transceiver function. In the transceiver mode, data present at the high-impedance port may be stored in either the A or B register or both. The Select (SAB, SBA) pins determine whether data is stored or transferred through the device in real-time. The DIR pin determines which bus receives data when OE is active (LOW). In isolation mode (OE = HIGH), data from bus A may be stored in the B register and/or data from bus B may be stored in the A register. When an output function is disabled, the input function is still enabled and may be used to store and transmit data. Only one of the two buses, A or B, may be driven at a time. The examples in Figure 5 “Real time bus transfer and storage” on page 6 demonstrate the four fundamental bus management functions that can be performed with the 74ABT646A. 2. Features and benefits n n n n n n n n n Combines 74ABT245 and 74ABT373A type functions in one device Independent registers for A and B buses Multiplexed real-time and stored data Live insertion and extraction permitted Output capability: +64 mA to −32 mA Power-up 3-state Power-up reset Latch-up protection exceeds 500 mA per JESD78B class II level A ESD protection: u HBM JESD22-A114F exceeds 2000 V u MM JESD22-A115-A exceeds 200 V 74ABT646A NXP Semiconductors Octal bus transceiver/register; 3-state 3. Ordering information Table 1. Ordering information Type number Package Temperature range Name Description Version 74ABT646AD −40 °C to +85 °C SO24 plastic small outline package; 24 leads; body width 7.5 mm SOT137-1 74ABT646ADB −40 °C to +85 °C SSOP24 plastic shrink small outline package; 24 leads; body width 5.3 mm SOT340-1 74ABT646APW −40 °C to +85 °C TSSOP24 plastic thin shrink small outline package; 24 leads; body width 4.4 mm SOT355-1 4. Functional diagram 21 G3 3EN1[BA] 3 22 4 5 6 7 8 9 2 10 11 3EN2[AB] G6 G7 23 1 A0 A1 A2 A3 A4 A5 A6 A7 CPAB 2 SAB 3 DIR 23 CPBA 22 SBA 21 OE C4 1 C5 4 5 B0 B1 B2 B3 B4 B5 B6 B7 20 19 18 17 16 15 14 13 001aae891 1 ≥1 5D 7 1 7 6 4D 6 1 ≥1 20 2 19 6 18 7 17 8 16 9 15 10 14 11 13 001aae892 Fig 1. Logic symbol 74ABT646A_3 Product data sheet Fig 2. IEC logic symbol All information provided in this document is subject to legal disclaimers. Rev. 03 — 15 March 2010 © NXP B.V. 2010. All rights reserved. 2 of 19 74ABT646A NXP Semiconductors Octal bus transceiver/register; 3-state OE DIR CPBA SBA CPAB SAB 21 3 23 22 1 2 1 of 8 channels 1D C1 Q A0 20 4 B0 1D C1 Q A1 A2 A3 A4 A5 A6 A7 5 6 7 8 9 10 11 19 18 17 16 15 14 13 DETAIL A × 7 B1 B2 B3 B4 B5 B6 B7 001aae894 Fig 3. Logic diagram 74ABT646A_3 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 03 — 15 March 2010 © NXP B.V. 2010. All rights reserved. 3 of 19 74ABT646A NXP Semiconductors Octal bus transceiver/register; 3-state 5. Pinning information 5.1 Pinning 74ABT646A CPAB 1 24 VCC SAB 2 23 CPBA DIR 3 22 SBA A0 4 21 OE A1 5 20 B0 A2 6 19 B1 A3 7 18 B2 A4 8 17 B3 A5 9 16 B4 A6 10 15 B5 A7 11 14 B6 GND 12 13 B7 001aae890 Fig 4. Pin configuration 5.2 Pin description Table 2. Pin description Symbol Pin Description CPAB 1 A to B clock input SAB 2 A to B select input DIR 3 direction control input A0, A1, A2, A3, A4, A5, A6, A7 4, 5, 6, 7, 8, 9, 10, 11 data input/output (A side) GND 12 ground (0 V) B0, B1, B2, B3, B4, B5, B6, B7 20, 19, 18, 17, 16, 15, 14, 13 data input/output (B side) OE 21 output enable input (active LOW) SBA 22 B to A select input CPBA 23 B to A clock input VCC 24 positive supply voltage 74ABT646A_3 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 03 — 15 March 2010 © NXP B.V. 2010. All rights reserved. 4 of 19 74ABT646A NXP Semiconductors Octal bus transceiver/register; 3-state 6. Functional description Table 3. Function table[1] Inputs Data I/O Operating mode OE DIR CPAB CPBA SAB SBA An Bn X X ↑ X X X input unspecified output[2] store A, B unspecified X X X ↑ X X unspecified output[2] input store B, A unspecified H X ↑ ↑ X X input input store A and B data H X H or L H or L X X input input isolation, hold storage L L X X X L output input real time B data to A bus L L X H or L X H output input stored B data to A bus L H X X L X input output real time A data to B bus L H H or L X H X input output stored A data to B bus [1] H = HIGH voltage level; L = LOW voltage level; X = don’t care; ↑ = LOW-to-HIGH clock transition; [2] The data output function may be enabled or disabled by various signals at the OE input. Data input functions are always enabled, i.e. data at the bus pins will be stored on every LOW-to-HIGH transition of the clock. 74ABT646A_3 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 03 — 15 March 2010 © NXP B.V. 2010. All rights reserved. 5 of 19 xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx NXP Semiconductors 74ABT646A_3 Product data sheet REAL TIME BUS TRANSFER BUS B TO BUS A Rev. 03 — 15 March 2010 OE L CPAB CPBA X X SAB X SBA L OE L Real time bus transfer and storage DIR H B CPAB CPBA X X SAB L A SBA X OE L L H DIR H L X B CPAB CPBA X X SAB X X X A SBA X X X OE L L DIR L H B CPAB CPBA X H/L H/L X SAB X H SBA H X 001aae893 74ABT646A 6 of 19 © NXP B.V. 2010. All rights reserved. Fig 5. DIR L A B TRANSFER STORED DATA TO A OR B Octal bus transceiver/register; 3-state All information provided in this document is subject to legal disclaimers. A STORAGE FROM A, B, OR A AND B REAL TIME BUS TRANSFER BUS A TO BUS B 74ABT646A NXP Semiconductors Octal bus transceiver/register; 3-state 7. Limiting values Table 4. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol Parameter VCC supply voltage Conditions Min Max Unit −0.5 +7.0 V [1] −1.2 +7.0 V [1] −0.5 +5.5 V VI input voltage VO output voltage output in OFF-state or HIGH-state IIK input clamping current VI < 0 V −18 - mA IOK output clamping current VO < 0 V −50 - mA IO output current output in LOW-state Tj junction temperature Tstg storage temperature [2] - 128 mA - 150 °C −65 +150 °C [1] The input and output voltage ratings may be exceeded if the input and output current ratings are observed. [2] The performance capability of a high-performance integrated circuit in conjunction with its thermal environment can create junction temperatures which are detrimental to reliability. The maximum junction temperature of this integrated circuit should not exceed 150 °C. 8. Recommended operating conditions Table 5. Recommended operating conditions Symbol Parameter VCC supply voltage Conditions Min Typ Max Unit 4.5 - 5.5 V VI input voltage 0 - VCC V VIH HIGH-level input voltage 2.0 - - V VIL LOW-level input voltage - - 0.8 V IOH HIGH-level output current −32 - - mA IOL LOW-level output current - - 64 mA ∆t/∆V input transition rise and fall rate 0 - 10 ns/V Tamb ambient temperature −40 - +85 °C 74ABT646A_3 Product data sheet in free air All information provided in this document is subject to legal disclaimers. Rev. 03 — 15 March 2010 © NXP B.V. 2010. All rights reserved. 7 of 19 74ABT646A NXP Semiconductors Octal bus transceiver/register; 3-state 9. Static characteristics Table 6. Static characteristics Symbol Parameter 25 °C Conditions −40 °C to 85 °C Unit Min Typ Max Min Max −1.2 −0.9 - −1.2 - V VCC = 4.5 V; IOH = −3 mA 2.5 3.0 - 2.5 - V VCC = 5.0 V; IOH = −3 mA 3.0 3.5 - 3.0 - V VCC = 4.5 V; IOH = −32 mA 2.0 2.4 - 2.0 - V - 0.3 0.55 - 0.55 V - 0.13 0.55 - 0.55 V control pins - ±0.0 1 ±1.0 - ±1.0 µA data pins - ±5 ±100 - ±100 µA VIK input clamping voltage VCC = 4.5 V; IIK = −18 mA VOH HIGH-level output voltage VI = VIL or VIH VOL LOW-level output voltage VCC = 4.5 V; IOL = 64 mA; VI = VIL or VIH VOL(pu) power-up LOW-level output voltage VCC = 5.5 V; IO = 1 mA; VI = GND or VCC II input leakage current VCC = 5.5 V; VI = GND or 5.5 V IOFF power-off leakage current VCC = 0 V; VI or VO ≤ 4.5 V IO(pu/pd) power-up/power-down output current VCC = 2.1 V; VO = 0.5 V; VI = GND or VCC; OE HIGH IOZ OFF-state output current VCC = 5.5 V; VI = VIL or VIH [1] [2] - ±5.0 ±100 - ±100 µA - ±5.0 ±50 - ±50 µA VO = 2.7 V - 5.0 50 - 50 µA VO = 0.5 V - −5.0 −50 - −50 µA - 5.0 50 - 50 µA −180 −65 −40 −180 −40 mA outputs HIGH-state - 110 250 - 250 µA outputs LOW-state - 20 30 - 30 mA outputs disabled - 110 250 - 250 µA - 0.6 1.5 - 1.5 mA ILO output leakage current VCC = 5.5 V; HIGH-state; VO = 5.5 V; VCC = 5.5 V; VI = GND or VCC IO output current VCC = 5.5 V; VO = 2.5 V ICC supply current VCC = 5.5 V; VI = GND or VCC [3][5] ∆ICC additional supply current per input pin; VCC = 5.5 V; one input at 3.4 V; other inputs at VCC or GND CI input capacitance control pins; VI = 0 V or VCC - 4 - - - pF CI/O input/output capacitance I/O pins; outputs disabled; VO = 0 V or VCC - 7 - - - pF [4] [1] For valid test results, data must not be loaded into the flip-flops (or latches) after applying the power. [2] This parameter is valid for any VCC between 0 V and 2.1 V with a transition time of up to 10 ms. For VCC = 2.1 V to VCC = 5 V ± 10 %, a transition time of up to 100 µs is permitted. [3] Not more than one output should be tested at a time, and the duration of the test should not exceed one second. [4] This is the increase in supply current for each input at 3.4 V. [5] This data sheet limit may vary among suppliers. 74ABT646A_3 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 03 — 15 March 2010 © NXP B.V. 2010. All rights reserved. 8 of 19 74ABT646A NXP Semiconductors Octal bus transceiver/register; 3-state 10. Dynamic characteristics Table 7. Dynamic characteristics GND = 0 V; for test circuit, see Figure 11. Symbol Parameter 25 °C; VCC = 5.0 V Conditions −40 °C to +85 °C; Unit VCC = 5.0 V ± 0.5 V Min Typ Max Min Max fmax maximum frequency see Figure 6 125 350 - 125 - tPLH LOW to HIGH propagation delay CPAB to Bn or CPBA to An; see Figure 6 2.2 3.9 5.1 2.2 5.6 HIGH to LOW propagation delay tPHL tPZH tPZL MHz ns An to Bn or Bn to An; see Figure 7 1.5 3.2 4.3 1.5 4.8 ns SAB to Bn or SBA to An; see Figure 7 1.5 3.8 5.1 1.5 6.5 ns CPAB to Bn or CPBA to An; see Figure 6 1.7 4.4 5.2[1] 1.7 5.6 ns An to Bn or Bn to An; see Figure 7 1.5 3.7 4.6 1.5 5.4 ns SAB to Bn or SBA to An; see Figure 7 1.5 4.4 5.3[1] 1.5 5.9 ns OFF-state to HIGH propagation delay OE to An or Bn; see Figure 8 1.5 3.5 5.3 1.5 6.3 ns DIR to An or Bn; see Figure 8 1.5 3.9 5.7 1.2 6.7 ns OFF-state to LOW propagation delay OE to An or Bn; see Figure 9 3.0 4.5 7.4 3.0 8.8 ns DIR to An or Bn; see Figure 9 2.5 4.7 9.0 2.5 9.5 ns 1.5 5.3[1] ns HIGH to OFF-state propagation delay OE to An or Bn; see Figure 8 1.5 4.0 4.8[1] DIR to An or Bn; see Figure 8 1.5 4.0 5.0 1.5 5.7 ns LOW to OFF-state propagation delay OE to An or Bn; see Figure 9 1.5 3.3 4.0 1.5 4.5 ns DIR to An or Bn; see Figure 9 1.5 3.5 4.7 1.5 6.0 ns tsu(H) set-up time HIGH An to CPAB, Bn to CPBA; see Figure 10 3.0 0.7 - 3.0 - ns tsu(L) set-up time LOW An to CPAB, Bn to CPBA; see Figure 10 3.0 0.7 - 3.0 - ns th(H) hold time HIGH An to CPAB, Bn to CPBA; see Figure 10 +0.0 −0.5 - 0.0 - ns th(L) hold time LOW An to CPAB, Bn to CPBA; see Figure 10 +0.0 −0.5 - 0.0 - ns tWH pulse width HIGH CPAB, CPBA; see Figure 6 4.0 0.9 - 4.0 - ns tWL pulse width LOW LE; see Figure 6 4.0 1.4 - 4.0 - ns tPHZ tPLZ [1] This data sheet limit may vary among suppliers. 74ABT646A_3 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 03 — 15 March 2010 © NXP B.V. 2010. All rights reserved. 9 of 19 74ABT646A NXP Semiconductors Octal bus transceiver/register; 3-state 11. Waveforms 1 / fmax VI CPBA or CPAB VM VM VM GND tWH tWL tPLH tPHL VOH An or Bn VM VM VOL 001aae839 VM = 1.5 V VOL and VOH are typical voltage output levels that occur with the output load. Fig 6. Propagation delay clock input to output and clock pulse width, maximum clock frequency VI SBA or SAB, An or Bn VM VM GND tPLH tPHL VOH An or Bn VM VM VOL 001aae895 VM = 1.5 V VOL and VOH are typical voltage output levels that occur with the output load. Fig 7. Propagation delay, SAB to Bn or SBA to An, An to Bn or Bn to An VI VM VM OE, DIR GND tPZH tPHZ VOH An or Bn VM VOH − 0.3 V GND 001aae896 VM = 1.5 V VOL and VOH are typical voltage output levels that occur with the output load. Fig 8. 3-state output enable time to HIGH-level and output disable time from HIGH-level 74ABT646A_3 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 03 — 15 March 2010 © NXP B.V. 2010. All rights reserved. 10 of 19 74ABT646A NXP Semiconductors Octal bus transceiver/register; 3-state VI VM VM OE, DIR GND tPZL tPLZ 3.5 V An or Bn VM VOL + 0.3 V VOL 001aae898 VM = 1.5 V VOL and VOH are typical voltage output levels that occur with the output load. Fig 9. 3-state output enable time to LOW-level and output disable time from LOW-level VI VM An, Bn GND tsu(H) VM th(H) tsu(L) VM th(L) tWL VI CPBA or CPAB VM VM GND VM 001aae849 VM = 1.5 V VOL and VOH are typical voltage output levels that occur with the output load. The shaded areas indicate when the input is permitted to change for predictable output performance. Fig 10. Data set-up and hold times 74ABT646A_3 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 03 — 15 March 2010 © NXP B.V. 2010. All rights reserved. 11 of 19 74ABT646A NXP Semiconductors Octal bus transceiver/register; 3-state VI tW 90 % 90 % negative pulse VM 0V VCC 10 % tf tr tr tf VI 90 % positive pulse 0V VEXT VM 10 % VI RL VO G DUT RT 90 % CL RL VM VM 10 % mna616 10 % tW 001aai298 a. Input pulse definition b. Test circuit Test data is given in Table 8. RL = Load resistance. CL = Load capacitance including jig and probe capacitance. RT = Termination resistance should be equal to output impedance Zo of the pulse generator. VEXT = Test voltage for switching times. Fig 11. Load circuitry for switching times Table 8. Test data Input Load VEXT VI fI tW tr, tf CL RL tPHL, tPLH tPZH, tPHZ tPZL, tPLZ 3.0 V 1 MHz 500 ns ≤ 2.5 ns 50 pF 500 Ω open open 7.0 V 74ABT646A_3 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 03 — 15 March 2010 © NXP B.V. 2010. All rights reserved. 12 of 19 74ABT646A NXP Semiconductors Octal bus transceiver/register; 3-state 12. Package outline SO24: plastic small outline package; 24 leads; body width 7.5 mm SOT137-1 D E A X c HE y v M A Z 24 13 Q A2 A (A 3) A1 pin 1 index θ Lp L 1 12 e detail X w M bp 0 5 10 mm scale DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (1) e HE L Lp Q v w y mm 2.65 0.3 0.1 2.45 2.25 0.25 0.49 0.36 0.32 0.23 15.6 15.2 7.6 7.4 1.27 10.65 10.00 1.4 1.1 0.4 1.1 1.0 0.25 0.25 0.1 0.01 0.019 0.013 0.014 0.009 0.61 0.60 0.30 0.29 0.05 0.419 0.043 0.055 0.394 0.016 inches 0.1 0.012 0.096 0.004 0.089 0.043 0.039 0.01 0.01 Z (1) 0.9 0.4 0.035 0.004 0.016 θ o 8 o 0 Note 1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included. REFERENCES OUTLINE VERSION IEC JEDEC SOT137-1 075E05 MS-013 JEITA EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-19 Fig 12. Package outline SOT137-1 (SO24) 74ABT646A_3 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 03 — 15 March 2010 © NXP B.V. 2010. All rights reserved. 13 of 19 74ABT646A NXP Semiconductors Octal bus transceiver/register; 3-state SSOP24: plastic shrink small outline package; 24 leads; body width 5.3 mm D SOT340-1 E A X c HE y v M A Z 24 13 Q A2 A (A 3) A1 pin 1 index θ Lp L 1 12 bp e detail X w M 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (1) e HE L Lp Q v w y Z (1) θ mm 2 0.21 0.05 1.80 1.65 0.25 0.38 0.25 0.20 0.09 8.4 8.0 5.4 5.2 0.65 7.9 7.6 1.25 1.03 0.63 0.9 0.7 0.2 0.13 0.1 0.8 0.4 8 o 0 o Note 1. Plastic or metal protrusions of 0.2 mm maximum per side are not included. OUTLINE VERSION SOT340-1 REFERENCES IEC JEDEC JEITA EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-19 MO-150 Fig 13. Package outline SOT340-1 (SSOP24) 74ABT646A_3 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 03 — 15 March 2010 © NXP B.V. 2010. All rights reserved. 14 of 19 74ABT646A NXP Semiconductors Octal bus transceiver/register; 3-state TSSOP24: plastic thin shrink small outline package; 24 leads; body width 4.4 mm D SOT355-1 E A X c HE y v M A Z 13 24 Q A2 (A 3) A1 pin 1 index A θ Lp L 1 12 bp e detail X w M 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (2) e HE L Lp Q v w y Z (1) θ mm 1.1 0.15 0.05 0.95 0.80 0.25 0.30 0.19 0.2 0.1 7.9 7.7 4.5 4.3 0.65 6.6 6.2 1 0.75 0.50 0.4 0.3 0.2 0.13 0.1 0.5 0.2 8o 0o Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT355-1 REFERENCES IEC JEDEC JEITA EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-19 MO-153 Fig 14. Package outline SOT355-1 (TSSOP24) 74ABT646A_3 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 03 — 15 March 2010 © NXP B.V. 2010. All rights reserved. 15 of 19 74ABT646A NXP Semiconductors Octal bus transceiver/register; 3-state 13. Abbreviations Table 9. Abbreviations Acronym Description BiCMOS Bipolar Complementary Metal-Oxide Semiconductor DUT Device Under Test ESD ElectroStatic Discharge HBM Human Body Model MM Machine Model 14. Revision history Table 10. Revision history Document ID Release date Data sheet status Change notice Supersedes 74ABT646A_3 20100315 Product data sheet - 74ABT646A_2 Modifications: • The format of this data sheet has been redesigned to comply with the new identity guidelines of NXP Semiconductors. • • Legal texts have been adapted to the new company name where appropriate. DIP 24 (SOT222-1) package removed from Section 3 “Ordering information” and Section 12 “Package outline”. 74ABT646A_2 19980217 Product specification - 74ABT646A_1 74ABT646A_1 19950906 Product specification - - 74ABT646A_3 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 03 — 15 March 2010 © NXP B.V. 2010. All rights reserved. 16 of 19 74ABT646A NXP Semiconductors Octal bus transceiver/register; 3-state 15. Legal information 15.1 Data sheet status Document status[1][2] Product status[3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification. [1] Please consult the most recently issued document before initiating or completing a design. [2] The term ‘short data sheet’ is explained in section “Definitions”. [3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com. 15.2 Definitions Draft — The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet — A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. Product specification — The information and data provided in a Product data sheet shall define the specification of the product as agreed between NXP Semiconductors and its customer, unless NXP Semiconductors and customer have explicitly agreed otherwise in writing. In no event however, shall an agreement be valid in which the NXP Semiconductors product is deemed to offer functions and qualities beyond those described in the Product data sheet. 15.3 Disclaimers Limited warranty and liability — Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. In no event shall NXP Semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation lost profits, lost savings, business interruption, costs related to the removal or replacement of any products or rework charges) whether or not such damages are based on tort (including negligence), warranty, breach of contract or any other legal theory. Notwithstanding any damages that customer might incur for any reason whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards customer for the products described herein shall be limited in accordance with the Terms and conditions of commercial sale of NXP Semiconductors. Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use in automotive applications — This NXP Semiconductors product has been qualified for use in automotive applications. The product is not designed, authorized or warranted to be 74ABT646A_3 Product data sheet suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk. Applications — Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. NXP Semiconductors does not accept any liability related to any default, damage, costs or problem which is based on a weakness or default in the customer application/use or the application/use of customer’s third party customer(s) (hereinafter both referred to as “Application”). It is customer’s sole responsibility to check whether the NXP Semiconductors product is suitable and fit for the Application planned. Customer has to do all necessary testing for the Application in order to avoid a default of the Application and the product. NXP Semiconductors does not accept any liability in this respect. Limiting values — Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) will cause permanent damage to the device. Limiting values are stress ratings only and (proper) operation of the device at these or any other conditions above those given in the Recommended operating conditions section (if present) or the Characteristics sections of this document is not warranted. Constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device. Terms and conditions of commercial sale — NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, unless otherwise agreed in a valid written individual agreement. In case an individual agreement is concluded only the terms and conditions of the respective agreement shall apply. NXP Semiconductors hereby expressly objects to applying the customer’s general terms and conditions with regard to the purchase of NXP Semiconductors products by customer. No offer to sell or license — Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. Export control — This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from national authorities. 15.4 Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. All information provided in this document is subject to legal disclaimers. Rev. 03 — 15 March 2010 © NXP B.V. 2010. All rights reserved. 17 of 19 74ABT646A NXP Semiconductors Octal bus transceiver/register; 3-state 16. Contact information For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: [email protected] 74ABT646A_3 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 03 — 15 March 2010 © NXP B.V. 2010. All rights reserved. 18 of 19 74ABT646A NXP Semiconductors Octal bus transceiver/register; 3-state 17. Contents 1 2 3 4 5 5.1 5.2 6 7 8 9 10 11 12 13 14 15 15.1 15.2 15.3 15.4 16 17 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features and benefits . . . . . . . . . . . . . . . . . . . . 1 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2 Pinning information . . . . . . . . . . . . . . . . . . . . . . 4 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4 Functional description . . . . . . . . . . . . . . . . . . . 5 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 7 Recommended operating conditions. . . . . . . . 7 Static characteristics. . . . . . . . . . . . . . . . . . . . . 8 Dynamic characteristics . . . . . . . . . . . . . . . . . . 9 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 13 Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Revision history . . . . . . . . . . . . . . . . . . . . . . . . 16 Legal information. . . . . . . . . . . . . . . . . . . . . . . 17 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 17 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Contact information. . . . . . . . . . . . . . . . . . . . . 18 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. © NXP B.V. 2010. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: [email protected] Date of release: 15 March 2010 Document identifier: 74ABT646A_3