PCF2119x LCD controllers/drivers Rev. 05 — 13 August 2009 Product data sheet 1. General description The PCF2119x is a low power CMOS1 LCD controller and driver, designed to drive a dot matrix LCD display of 2-lines by 16 characters or 1-line by 32 characters with 5 × 8 dot format. All necessary functions for the display are provided in a single chip, including on-chip generation of LCD bias voltages, resulting in a minimum of external components and lower system current consumption. The PCF2119x interfaces to most microcontrollers via a 4-bit or 8-bit bus or via the 2-wire I2C-bus. The chip contains a character generator and displays alphanumeric and kana (Japanese) characters. The letter ‘x’ in PCF2119x characterizes the built-in character set. Various character sets can be manufactured on request. In addition 16 user defined symbols (5 × 8 dot format) are available. 2. Features n Single-chip LCD controller and driver n 2-line display of up to 16 characters plus 160 icons or 1-line display of up to 32 characters plus 160 icons n 5 × 7 character format plus cursor; 5 × 8 for kana (Japanese) and user defined symbols n Reduced current consumption while displaying icons only n Icon blink function n On-chip: u Configurable 4, 3 or 2 times voltage multiplier generating LCD supply voltage, independent of VDD, programmable by instruction (external supply also possible) u Temperature compensation of on-chip generated VLCDOUT: −0.16 %/K to −0.24 %/K (programmable by instruction) u Generation of intermediate LCD bias voltages u Oscillator requires no external components (external clock also possible) n Display Data RAM (DDRAM): 80 characters n Character Generator ROM (CGROM): 240 characters (5 × 8) n Character Generator RAM (CGRAM): 16 characters (5 × 8); 4 characters used to drive 160 icons, 8 characters used if icon blink feature is used in application n 4-bit or 8-bit parallel bus and 2-wire I2C-bus interface n CMOS compatible n 18 row and 80 column outputs n Multiplex rates 1:18 (2-line display or 1-line display), 1:9 (for 1-line display of up to 16 characters and 80 icons) and 1:2 (for icon only mode) 1. The definition of the abbreviations and acronyms used in this data sheet can be found in Section 20. PCF2119x NXP Semiconductors LCD controllers/drivers n Uses common 11 code instruction set (extended) n Logic supply voltage: VDD1 − VSS1 = 1.5 V to 5.5 V (chip may be driven with two battery cells) n LCD supply voltage: VLCDOUT − VSS2 = 2.2 V to 6.5 V n VLCD generator supply voltage: VDD2 − VSS2 = 2.2 V to 4 V and VDD3 − VSS2 = 2.2 V to 4 V n Direct mode to save current consumption for icon mode and multiplex drive mode 1:9 (depending on VDD2 value and LCD liquid properties) n Very low current consumption (20 µA to 200 µA): u Icon mode: < 25 µA u Power-down mode: < 2 µA n Icon mode is used to save current. When only icons are displayed, a much lower LCD operating voltage can be used and the switching frequency of the LCD outputs is reduced; in most applications it is possible to use VDD as LCD supply voltage 3. Applications n Telecom equipment n Portable instruments n Point-of-sale terminals 4. Ordering information Table 1. Ordering information Type number Package Name Description Version PCF2119AU/2DA/2 PCF2119x bare die: 168 bumps; 7.59 × 1.71 × 0.38 mm PCF2119x PCF2119DU/2/2 PCF2119x bare die: 168 bumps; 7.59 × 1.71 × 0.38 mm PCF2119x PCF2119FU/2/F2 PCF2119x bare die: 168 bumps; 7.59 × 1.71 × 0.38 mm PCF2119x PCF2119RU/2/F2 PCF2119x bare die: 168 bumps; 7.59 × 1.71 × 0.38 mm PCF2119x PCF2119SU/2/F2 PCF2119x bare die: 168 bumps; 7.59 × 1.71 × 0.38 mm PCF2119x PCF2119VU/2/F2 PCF2119x bare die: 168 bumps; 7.59 × 1.71 × 0.38 mm PCF2119x 5. Marking Table 2. Marking codes Type number Marking code PCF2119AU/2DA/2 PC2119-2 PCF2119DU/2/2 PC2119-2 PCF2119FU/2/F2 PC2119-2 PCF2119RU/2/F2 PC2119-2 PCF2119SU/2/F2 PC2119-2 PCF2119VU/2/F2 PC2119-2 PCF2119X_5 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 05 — 13 August 2009 2 of 79 PCF2119x NXP Semiconductors LCD controllers/drivers 6. Block diagram C1 to C80 R17DUP 60 to 99, 101 to 140 R1 to R18 51 to 59, 141 to 149 100 80 VLCDIN 44 to 49 18 COLUMN DRIVERS BIAS VOLTAGE GENERATOR ROW DRIVERS 80 18 DATA LATCHES VLCDOUT VLCDSENSE 37 to 43 80 VLCD 36 SHIFT REGISTER 18-BIT SHIFT REGISTER 5 × 12 BIT GENERATOR 5 OSCILLATOR 168 OSC CURSOR AND DATA CONTROL VDD1 VDD2 VDD3 5 1 to 6 7 to 14 VSS1 22 to 29 VSS2 30 to 35 T1 T2 T3 CHARACTER GENERATOR RAM (128 × 5) (CGRAM) 16 CHARACTERS 15 to 18 CHARACTER GENERATOR ROM (CGROM) 240 CHARACTERS TIMING GENERATOR 8 20 DISPLAY DATA RAM (DDRAM) 80 CHARACTERS/BYTES 7 21 155 PD 153 7 7 DISPLAY ADDRESS COUNTER ADDRESS COUNTER (AC) 7 7 INSTRUCTION DECODER 8 DATA REGISTER (DR) INSTRUCTION REGISTER BUSY FLAG 8 PCF2119X 154 8 POR 163 DB3/SA0 I/O BUFFER 160 to 162 DB0 to DB2 Fig 1. 164 to 167 DB4 to DB7 19 E 158 R/W 159 RS 156, 157 151, 152 SCL SDA mgw571 Block diagram PCF2119X_5 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 05 — 13 August 2009 3 of 79 PCF2119x NXP Semiconductors LCD controllers/drivers 7. Pinning information 7.1 Pinning dummy R8 49 50 VLCDIN 44 R1 R17 C80 VLCDOUT 60 37 35 VLCDSENSE VSS2 34 VSS2 30 C66 74 C65 75 VSS1 22 21 T2 20 T1 19 E VDD3 15 VDD2 7 C41 R17DUP C40 100 VDD1 1 168 OSC DB7 DB6 DB5 DB4 DB3/SA0 C16 C15 DB2 125 126 DB1 DB0 RS 158 R/W PC2119 C1 R18 R9 SDA 142 PD R16 149 dummy 150 POR T3 151 SCL mgw572 Top view. For mechanical details, see Figure 49. Fig 2. Pinning diagram of PCF2119x (bare die) PCF2119X_5 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 05 — 13 August 2009 4 of 79 PCF2119x NXP Semiconductors LCD controllers/drivers 7.2 Pin description Table 3. Pin description Symbol Pin VDD1 1 to 6 Description supply voltage 1 (logic) 7 to 14 [1] supply voltage 2 (for high voltage generator) VDD3 15 to 18 [1] supply voltage 3 (for high voltage generator) E 19 [2] data bus clock input VDD2 • • T1 and T2 20 and 21 • VSS1 22 to 29 VSS2 30 to 35 [3] ground supply voltage 2 • VLCDIN 36 must be connected to VSS1 ground supply voltage 1 • VLCDOUT data is clocked in or out of the chip on the negative edge of the clock test pins [3] VLCDSENSE set HIGH to signal the start of a read or write operation for all circuits, except of high voltage generator for high voltage generator input for voltage multiplier regulation circuitry and for the bias level generation 37 to 43 • if VLCD is generated internally then this pin must be connected to VLCDOUT and VLCDIN • if VLCD is generated externally then this pin must be connected to VLCDIN only VLCD output 44 to 49 • if VLCD is generated internally then this pin must be connected to VLCDIN and to VLCDSENSE • if VLCD is generated externally then this pin must be left open-circuit input for LCD bias level generator [4] - dummy 50 R8 to R1, R17, R17DUP, R18, R9 to R16 51 to 58, 59, 100 141, 142 to 149 LCD row driver output C80 to C41, 60 to 99, LCD column driver output • • R17 has two pins: R17 and R17DUP R17 and R18 drive the icons C40 to C1 101 to 140 dummy 150 [4] - SCL 151 and 152 [5] I2C-bus serial clock input T3 153 test pin • • open-circuit not user accessible POR 154 external Power-On Reset (POR) input PD 155 power-down mode select • SDA 156 and 157 [5] for normal operation pin PD must be LOW I2C-bus serial data input/output PCF2119X_5 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 05 — 13 August 2009 5 of 79 PCF2119x NXP Semiconductors LCD controllers/drivers Table 3. Pin description …continued Symbol Pin Description R/W 158 read/write input • • • RS 159 OSC pin R/W = LOW selects the write operation this pin has an internal pull-up resistor register select pin; • DB0 to DB2, DB3/SA0, DB4 to DB7 pin R/W = HIGH selects the read operation 160 to 162, 163, 164 to 167 [6][7 ] 168 this pin has an internal pull-up resistor 8 bit bidirectional data bus (bit 0 to bit 7) • the 8-bit bidirectional data bus (3-state) transfers data between the microcontroller and the PCF2119x • pin DB7 may be used as the busy flag, signalling that internal operations are not yet completed • 4-bit operations the 4 higher order lines DB7 to DB4 are used, DB3 to DB0 must be left open-circuit • data bus line DB3 has an alternative function (SA0) as the I2C-bus address pin • each data line has its own internal pull-up resistor oscillator or external clock input • when the on-chip oscillator is used this pin must be connected to VDD1 [1] Always put VDD2 = VDD3. [2] When the I2C-bus is used, the parallel interface pin E must be LOW. [3] The substrate (rear side of the die) is wired to VSS but should not be electrically connected. [4] On the device connected to VSS1. [5] When the parallel bus is used, the pins SCL and SDA must be connected to VSS1 or VDD1; they must not be left open-circuit. [6] In the I2C-bus read mode, ports DB7 to DB4 and DB2 to DB0 should be connected to VDD1 or left open-circuit. [7] When the 4-bit interface is used without reading out from the PCF2119x (bit R/W is set permanently to logic 0), the unused ports DB4 to DB0 can either be set to VSS1 or VDD1 instead of leaving them open-circuit. PCF2119X_5 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 05 — 13 August 2009 6 of 79 PCF2119x NXP Semiconductors LCD controllers/drivers 8. Functional description 8.1 Oscillator and timing generator The internal logic and the LCD drive signals of the PCF2119x are timed by the frequency fclk which equals either the built in oscillator frequency fosc or an external clock frequency fclk(ext). 8.1.1 Timing generator The timing generator produces the various signals required to drive the internal circuitry. Internal chip operation is not disturbed by operations on the data buses. 8.1.2 Internal clock To use the on-chip oscillator, pin OSC must be connected to VDD1. The on-chip oscillator provides the clock signal for the display system. No external components are required. 8.1.3 External clock If an external clock will be used, the input is at pin OSC. The resulting display frame frequency is given by: f osc f fr = ----------3072 (1) Remark: Only in the power-down mode the clock is allowed to be stopped (pin OSC connected to VSS), otherwise the LCD is frozen in a DC state, which is not suitable for the liquid crystals. 8.2 Reset function and Power-On Reset (POR) The PCF2119x must be reset externally when power is turned on. If no external reset is performed, the chip might start-up in an unwanted state. For the external reset, pin POR has to be active HIGH. The reset has to be active for at least 3 oscillator periods in order for the reset to be executed. If the internal oscillator is used, the minimum reset activity time follows from the lowest possible oscillator frequency (fosc = 140 kHz, Tosc ~ 71 µs, 3 × Tosc ~ 215 µs). The internal oscillator start-up time is 200 µs (typ) up to 300 µs (max) after power-on. In case that an external oscillator is used, Tosc is dependent from fosc(ext). Afterwards the chip executes the Clear_display instruction, which requires 165 oscillator cycles. After the reset the chip has the state shown in Table 4 and is then ready for use. PCF2119X_5 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 05 — 13 August 2009 7 of 79 PCF2119x NXP Semiconductors LCD controllers/drivers Table 4. State after reset Step Function 1 Clear_display 2 Entry_mode_set 3 4 Control bit and register state Description bit I_D = 1 incremental cursor move direction bit S = 0 no display shift bit D = 0 display off bit C = 0 cursor off bit B = 0 cursor character blink off bit DL = 1 8-bit interface bit M = 0 1-line display Reference Table 16 Display_ctl Function_set bit SL = 0 1:18 multiplex drive mode bit H = 0 normal instruction set Table 18 Table 19 Table 12 5 default address pointer to DDRAM [1] 6 Icon_ctl bit IM = 0 character mode, full display bit IB = 0 icon blink disabled 7 Screen_conf bit L = 0 default configuration Table 23 Disp_conf bit P = 0; bit Q = 0 default configurations Table 24 8 Temp_ctl bit TC1 = 0; bit TC2 = 0 default temperature coefficient Table 28 9 VLCD_set register VA = 0; register VB = 0 VLCD generator off Table 32 10 I2C-bus interface reset 11 HV_gen bit S1 = 1; bit S0 = 0 VLCD generator set to 3 internal stages (4 voltage multipliers) Table 30 [1] Table 22 Table 25 The Busy Flag (BF) indicates the busy state (bit BF = 1) until initialization ends. The busy state lasts 2 ms. The chip may also be initialized by software (see Table 43 and Table 44). 8.3 Power-down mode The chip can be put into power-down mode by applying a HIGH-level to pin PD. In power-down mode all static currents are switched off (no internal oscillator, no bias level generation and all LCD outputs are internally connected to VSS). During power-down, information in the RAMs and the chip state are preserved. Instruction execution during power-down is possible when pin OSC is externally clocked. 8.4 LCD supply voltage generator The LCD supply voltage may be generated on-chip. The VLCD generator is controlled by two internal 6-bit registers: VA and VB. Register VA is programmed with the voltage for character mode and register VB with the voltage for icon mode. The nominal LCD operating voltage at room temperature is given by Equation 2: V LCD ( nom ) = V x × 0.08 + 1.82 (2) Where Vx is the integer value of the register VA or VB. It should be noted that VLCD is sometimes referred as the LCD operating voltage (Voper). PCF2119X_5 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 05 — 13 August 2009 8 of 79 PCF2119x NXP Semiconductors LCD controllers/drivers 8.4.1 Programming ranges Possible values for VA and VB are between 0 to 63. Remarks: • Values producing more than 6.5 V at operating temperature are not allowed. Operation above this voltage may damage the device. When programming the operating voltage the temperature coefficient of VLCDOUT must be taken into account. • Values below 2.2 V are below the specified operating range of the chip and are therefore not allowed. Table 5. Values of VA and VB and the corresponding VLCD values All values at Tref = 27 °C; allowed values are highlighted. Integer values of VA and VB Corresponding value of VLCD in V Integer values of VA and VB Corresponding value of VLCD in V Integer values of VA and VB Corresponding value of VLCD in V 0 VLCD switched off 22 3.58 44 5.34 1 1.90 23 3.66 45 5.42 2 1.98 24 3.74 46 5.50 3 2.06 25 3.82 47 5.58 4 2.14 26 3.90 48 5.66 5 2.22 27 3.98 49 5.74 6 2.30 28 4.06 50 5.82 7 2.38 29 4.14 51 5.90 8 2.46 30 4.22 52 5.98 9 2.54 31 4.30 53 6.06 10 2.62 32 4.38 54 6.14 11 2.70 33 4.46 55 6.22 12 2.78 34 4.54 56 6.30 13 2.86 35 4.62 57 6.38 14 2.94 36 4.70 58 6.46 15 3.02 37 4.78 59 6.54 16 3.10 38 4.86 60 6.62 17 3.18 39 4.94 61 6.70 18 3.26 40 5.02 62 6.78 19 3.34 41 5.10 63 6.86 20 3.42 42 5.18 21 3.50 43 5.26 When the LCD supply voltage is generated on-chip, the VLCD pins should be decoupled to VSS with a suitable capacitor. The generated VLCDOUT is independent of VDD and is temperature compensated. In Equation 2 the internal charge pump is not considered. However, if the supplied voltage to VDD2 and VDD3 is below the required VLCD it is necessary to use the internal charge pump. The multiplication factor has to be set such, that VDD2 and VDD3 (which are equal) multiplied with the programmed multiplication factor exceeds the required VLCD under all circumstances (i.e. at low temperatures and along with the temperature compensation PCF2119X_5 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 05 — 13 August 2009 9 of 79 PCF2119x NXP Semiconductors LCD controllers/drivers see Section 10.2.3.4). If still a higher multiplication factor is chosen, VLCD will not increase (it is set by Equation 2) but the current that can be delivered will be higher. Also current consumption increases (see Section 16.6). When the VLCD generator and the direct mode are switched off, an external voltage may be supplied at connected pins VLCDIN and VLCDOUT. VLCDIN and VLCDOUT may be higher or lower than VDD2. In direct mode (see Icon_ctl instruction, Section 10.2.3.3) the internal VLCD generator is turned off and the VLCDOUT output voltage is directly connected to VDD2. This reduces the current consumption depending on VDD2 value and LCD liquid properties. The VLCD generator ensures that, as long as VDD is in the valid range (2.2 V to 4 V), the required peak voltage VLCD = 6.5 V can be generated at any time. 8.5 LCD bias voltage generator The intermediate bias voltages for the LCD display are also generated on-chip. This removes the need for an external resistive bias chain and significantly reduces the system current consumption. The optimum value of VLCD depends on the multiplex rate, the LCD threshold voltage (Vth) and the number of bias levels. Using a 5-level bias scheme for the 1:18 multiplex rate allows VLCD < 5 V for most LCD liquids. The intermediate bias levels for the different multiplex rates are shown in Table 6. These bias levels are automatically set to the given values when switching to the corresponding multiplex rate. Table 6. Bias levels as a function of multiplex rate Multiplex rate Number of bias levels Bias voltages V1 V2 V3 V4 V5 V6 1:18 5 VLCD 3 --- ( V LCD – V SS ) 4 1 --- ( V LCD – V SS ) 2 1 --- ( V LCD – V SS ) 2 1 --- ( V LCD – V SS ) 4 VSS 1:9 5 VLCD 3 --- ( V LCD – V SS ) 4 1 --- ( V LCD – V SS ) 2 1 --- ( V LCD – V SS ) 2 1 --- ( V LCD – V SS ) 4 VSS 1:2 4 VLCD 2 --- ( V LCD – V SS ) 3 2 --- ( V LCD – V SS ) 3 1 --- ( V LCD – V SS ) 3 1 --- ( V LCD – V SS ) 3 VSS 8.6 LCD row and column drivers The PCF2119x contains 18 row and 80 column drivers, which drive the appropriate LCD bias voltages in sequence to the display in accordance with the data to be displayed. R17 and R18 drive the icon rows. Unused outputs should be left open. The bias voltages and the timing are selected automatically when the number of lines in the display is selected. Figure 3 to Figure 5 show typical waveforms. PCF2119X_5 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 05 — 13 August 2009 10 of 79 PCF2119x NXP Semiconductors LCD controllers/drivers frame n VLCD V2 ROW 17 V3/V4 V5 VSS frame n +1 state 1 (on) state 2 (off) R1 R2 R3 VLCD V2 ROW 18 V3/V4 V5 VSS ROW 1 R4 R5 R6 R7 VLCD V2 V3/V4 V5 VSS ROW 9 VLCD V2 V3/V4 V5 VSS ROW 2 VLCD V2 V3/V4 V5 VSS R8 R9 R10 R17 R18 C1 C2 C3 C4 C5 VLCD V2 ROW 10 V3/V4 V5 VSS COL 1 VLCD V2 V3/V4 V5 VSS COL 2 VLCD V2 V3/V4 V5 VSS VLCD state 1 0.5VLCD 0.25VLCD 0 −0.25VLCD −0.5VLCD −VLCD VLCD state 2 0.5VLCD 0.25VLCD 0 −0.25VLCD −0.5VLCD −VLCD 12 3 18 1 2 3 18 013aaa140 Vstate(t) = VCOL(t) − VROW(t). Fig 3. Waveforms for the 1:18 multiplex drive mode; character mode PCF2119X_5 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 05 — 13 August 2009 11 of 79 PCF2119x NXP Semiconductors LCD controllers/drivers frame n frame n +1 state 1 (off) VLCD V2 ROW 17 V3/V4 V5 VSS state 2 (on) R1 R2 R3 VLCD V2 V3/V4 V5 VSS R4 R8 ROW 2 VLCD V2 V3/V4 V5 VSS ROW 3 VLCD V2 V3/V4 V5 VSS ROW 1 ROW 4 VLCD V2 V3/V4 V5 VSS COL 1 VLCD V2 V3/V4 V5 VSS COL 2 VLCD V2 V3/V4 V5 VSS R5 R6 R7 R17 C1 C2 C3 C4 C5 VLCD state 1 0.5VLCD 0.25VLCD 0 −0.25VLCD −0.5VLCD −VLCD VLCD state 2 0.5VLCD 0.25VLCD 0 −0.25VLCD −0.5VLCD −VLCD 1 2 3 9 1 2 3 9 013aaa141 Vstate(t) = VCOL(t) − VROW(t). Fig 4. Waveforms for the 1:9 multiplex drive mode; character mode, R9 to R16 and R18 open PCF2119X_5 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 05 — 13 August 2009 12 of 79 PCF2119x NXP Semiconductors LCD controllers/drivers frame n ROW 17 VLCD 2/3 1/3 VSS ROW 18 VLCD 2/3 1/3 VSS ROW 1 to 16 VLCD 2/3 1/3 VSS COL 1 ON/OFF VLCD 2/3 1/3 VSS COL 2 ON/OFF VLCD 2/3 1/3 VSS COL 3 ON/OFF VLCD 2/3 1/3 VSS COL 4 ON/OFF VLCD 2/3 1/3 VSS frame n +1 only icons are driven (MUX 1: 2) state 1 (ON) state 2 (OFF) state 1 COL 1 - ROW 17 VLCD 0.66VLCD 0.33VLCD 0 −0.33VLCD −0.66VLCD −VLCD state 3 (OFF) state 2 COL 2 - ROW 17 VLCD 0.66VLCD 0.33VLCD 0 −0.33VLCD −0.66VLCD −VLCD COL 2 COL 1 VLCD 0.66VLCD 0.33VLCD state 3 0 COL 3 - ROW 1 to ROW 16 −0.33VLCD −0.66VLCD −VLCD 013aaa142 Vstate(t) = VCOL(t) − VROW(t). Von(RMS) = 0.745VLCD. Voff(RMS) = 0.333VLCD. V on D = --------- = 2.23 V off Fig 5. Waveforms for the 1:2 multiplex drive mode; icon mode PCF2119X_5 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 05 — 13 August 2009 13 of 79 PCF2119x NXP Semiconductors LCD controllers/drivers 9. Display data RAM and ROM 9.1 DDRAM The Display Data RAM (DDRAM) stores up to 80 characters of display data represented by 8-bit character codes. RAM locations which are not used for storing display data can be used as general purpose RAM. The basic RAM to display addressing scheme is shown in Figure 6, Figure 7 and Figure 8. With no display shift the characters represented by the codes in the first 32 RAM locations starting at address 00h are displayed in line 1. display position DDRAM address non-displayed DDRAM addresses 1 2 3 4 5 30 31 32 00 01 02 03 04 1D 1E 1F 20 21 4C 4D 4E 4F 1-line display non-displayed DDRAM address DDRAM address 1 2 3 4 5 14 15 16 00 01 02 03 04 0D 0E 0F 10 11 1 2 3 4 5 14 15 16 40 41 42 43 44 4D 4E 4F 50 51 24 25 26 27 line 1 64 65 66 67 line 2 2-line display/MUX 1 : 9 mode mgk892 All addresses are shown in hex. Fig 6. DDRAM to display mapping: no shift 1 DDRAM address 5 14 15 16 27 00 01 02 03 2 3 0C 0D 0E 1 5 14 15 16 67 40 41 42 43 4C 4D 4E 2 3 4 4 2-line display/MUX 1 : 9 mode line 1 line 2 mgl536 All addresses are shown in hex. Fig 7. DDRAM to display mapping: right shift PCF2119X_5 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 05 — 13 August 2009 14 of 79 PCF2119x NXP Semiconductors LCD controllers/drivers display position DDRAM address 5 30 31 32 01 02 03 04 05 1 2 3 4 1E 1F 20 1-line display 1 DDRAM address 5 14 15 16 01 02 03 04 05 2 0E 0F 10 1 5 14 15 16 41 42 43 44 45 4E 4F 50 2 3 3 4 4 2-line display/MUX 1 : 9 mode line 1 line 2 mgk894 All addresses are shown in hex. Fig 8. DDRAM to display mapping: left shift When data is written to or read from the DDRAM, wrap-around occurs from the end of one line to the start of the next line. When the display is shifted each line wraps around within itself, independently of the others. Thus all lines are shifted and wrapped around together. The address ranges and wrap-around operations for the various modes are shown in Table 7. Table 7. Address space and wrap-around operation Mode 1 × 32 2 × 16 1 × 16 Address space 00h to 4Fh 00h to 27h; 40h to 67h 00h to 27h Read/write wrap-around (moves to next line) 4Fh to 00h 27h to 40h; 67h to 00h 27h to 00h Display shift wrap-around (stays within line) 4Fh to 00h 27h to 00h; 67h to 40h 27h to 00h 9.2 CGROM The Character Generator ROM (CGROM) contains 240 character patterns in a 5 × 8 dot format from 8-bit character codes. Figure 9 to Figure 14 show the character sets that are currently implemented. PCF2119X_5 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 05 — 13 August 2009 15 of 79 PCF2119x NXP Semiconductors LCD controllers/drivers lower 4 bits upper 4 bits 0000 xxxx 0000 1 xxxx 0001 2 xxxx 0010 3 xxxx 0011 4 xxxx 0100 5 xxxx 0101 6 xxxx 0110 7 xxxx 0111 8 xxxx 1000 9 xxxx 1001 10 xxxx 1010 11 xxxx 1011 12 xxxx 1100 13 xxxx 1101 14 xxxx 1110 15 xxxx 1111 16 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 mce190 The first column (0000) is the CGRAM, the other 15 columns (0001 to 1111) are the CGROM. Fig 9. Character set ‘A’ in CGROM PCF2119X_5 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 05 — 13 August 2009 16 of 79 PCF2119x NXP Semiconductors LCD controllers/drivers lower 4 bits upper 4 bits 0000 xxxx 0000 1 xxxx 0001 2 xxxx 0010 3 xxxx 0011 4 xxxx 0100 5 xxxx 0101 6 xxxx 0110 7 xxxx 0111 8 xxxx 1000 9 xxxx 1001 10 xxxx 1010 11 xxxx 1011 12 xxxx 1100 13 xxxx 1101 14 xxxx 1110 15 xxxx 1111 16 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 mce173 The first column (0000) is the CGRAM, the other 15 columns (0001 to 1111) are the CGROM. Fig 10. Character set ‘D’ in CGROM PCF2119X_5 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 05 — 13 August 2009 17 of 79 PCF2119x NXP Semiconductors LCD controllers/drivers lower 4 bits upper 4 bits 0000 xxxx 0000 1 xxxx 0001 2 xxxx 0010 3 xxxx 0011 4 xxxx 0100 5 xxxx 0101 6 xxxx 0110 7 xxxx 0111 8 xxxx 1000 9 xxxx 1001 10 xxxx 1010 11 xxxx 1011 12 xxxx 1100 13 xxxx 1101 14 xxxx 1110 15 xxxx 1111 16 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 mgu552 The first column (0000) is the CGRAM, the other 15 columns (0001 to 1111) are the CGROM. Fig 11. Character set ‘F’ in CGROM PCF2119X_5 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 05 — 13 August 2009 18 of 79 PCF2119x NXP Semiconductors LCD controllers/drivers lower 4 bits upper 4 bits 0000 xxxx 0000 1 xxxx 0001 2 xxxx 0010 3 xxxx 0011 4 xxxx 0100 5 xxxx 0101 6 xxxx 0110 7 xxxx 0111 8 xxxx 1000 9 xxxx 1001 10 xxxx 1010 11 xxxx 1011 12 xxxx 1100 13 xxxx 1101 14 xxxx 1110 15 xxxx 1111 16 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 mgl535 The first column (0000) is the CGRAM, the other 15 columns (0001 to 1111) are the CGROM. Fig 12. Character set ‘R’ in CGROM PCF2119X_5 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 05 — 13 August 2009 19 of 79 PCF2119x NXP Semiconductors LCD controllers/drivers upper 4 bits 0000 xxxx 0000 1 xxxx 0001 2 xxxx 0010 3 xxxx 0011 4 xxxx 0100 5 xxxx 0101 6 xxxx 0110 7 xxxx 0111 8 xxxx 1000 9 xxxx 1001 10 xxxx 1010 11 xxxx 1011 12 xxxx 1100 13 xxxx 1101 14 xxxx 1110 15 xxxx 1111 16 lower 4 bits 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 mgl534 The first column (0000) is the CGRAM, the other 15 columns (0001 to 1111) are the CGROM. Fig 13. Character set ‘S’ in CGROM PCF2119X_5 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 05 — 13 August 2009 20 of 79 PCF2119x NXP Semiconductors LCD controllers/drivers lower 4 bits upper 4 bits 0000 xxxx 0000 1 xxxx 0001 2 xxxx 0010 3 xxxx 0011 4 xxxx 0100 5 xxxx 0101 6 xxxx 0110 7 xxxx 0111 8 xxxx 1000 9 xxxx 1001 10 xxxx 1010 11 xxxx 1011 12 xxxx 1100 13 xxxx 1101 14 xxxx 1110 15 xxxx 1111 16 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 mgl597 The first column (0000) is the CGRAM, the other 15 columns (0001 to 1111) are the CGROM. Fig 14. Character set ‘V’ in CGROM PCF2119X_5 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 05 — 13 August 2009 21 of 79 PCF2119x NXP Semiconductors LCD controllers/drivers 9.3 CGRAM Up to 16 user defined characters may be stored in the Character Generator RAM (CGRAM). Some CGRAM characters (see Figure 21) are also used to drive icons: • 6 CGRAM characters if icons blink and both icon rows are used in the application • 3 CGRAM characters if no icons blink but both icon rows are used in the application • 0 CGRAM characters if no icons are driven by the icon rows When the icons blink option is enabled, double the number of CGRAM characters are used since both the on and off state of an icon is defined. The CGROM and CGRAM use a common address space, of which the first column is reserved for the CGRAM (see Figure 9 to Figure 14). Figure 15 shows the addressing principle for the CGRAM. character codes (DDRAM data) 7 6 5 4 3 2 higher order bits 0 0 0 CGRAM address 1 0 6 lower order bits 0 0 0 0 5 4 3 higher order bits 0 0 0 0 0 (2) 0 0 0 0 0 0 1 0 0 (1) 0 1 (1) (5) 0 0 0 0 0 0 1 0 0 0 1 1 0 lower order bits (4) 0 2 character patterns (CGRAM data) 0 4 3 higher order bits 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 0 0 0 0 1 2 1 character code (CGRAM data) 0 4 3 2 1 0 0 1 1 1 1 1 1 1 0 1 0 0 1 0 0 0 0 1 0 0 1 1 0 0 0 1 0 0 1 0 1 0 0 0 1 1 0 0 0 1 0 1 0 1 0 1 0 0 0 0 1 1 0 1 0 0 0 0 0 1 1 1 1 1 0 0 1 1 0 1 0 0 0 1 0 1 0 1 0 0 0 lower order bits 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 character pattern example 1 cursor position character pattern example 2 (3) coa072 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 1 1 0 1 0 1 (1) Character code bit 0 to bit 3 correspond to CGRAM address bit 3 to bit 6. (2) CGRAM address bit 0 to bit 2 designate the character pattern line position. The 8th line is the cursor position and display is performed by logical OR with the cursor. Data in the 8th line will appear in the cursor position. Lines are numbered from 0 to 7. (3) Character pattern column positions correspond to CGRAM data bit 0 to bit 4, as shown in Figure 9 to Figure 14. (4) As shown in Figure 9 to Figure 14, CGRAM character patterns are selected when character code bit 4 to bit 7 are all logic 0. CGRAM data = logic 1 corresponds to selection for display. (5) Only bit 0 to bit 5 of the CGRAM address are set by the Set_CGRAM command. Bit 6 can be set using the Set_DDRAM command in the valid address range or by using the auto-increment feature during CGRAM write. All bits from bit 0 to bit 6 can be read using the BF_AC instruction. Fig 15. Relationship between CGRAM addresses, data and display patterns PCF2119X_5 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 05 — 13 August 2009 22 of 79 PCF2119x NXP Semiconductors LCD controllers/drivers 9.4 Cursor control circuit The cursor control circuit generates the cursor underline and/or cursor blink as shown in Figure 16 at the DDRAM address contained in the address counter. cursor 013aaa139 5 × 7 dot character font alternating display cursor display example blink display example Fig 16. Cursor and blink display examples icon 1 row 18 icon 5 row 17 row 17 row 8 row 8 row 2 row 2 row 1 row 1 cursor 013aaa156 Fig 17. Example of a displays with icons PCF2119X_5 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 05 — 13 August 2009 23 of 79 PCF2119x NXP Semiconductors LCD controllers/drivers 10. Registers The PCF2119x has two 8-bit registers, an instruction register and a data register. Only these two registers can be directly controlled by the microcontroller. Before an internal operation, the control information is stored temporarily in these registers, to allow interfacing to various types of microcontrollers which operate at different speeds or to allow interface to peripheral control ICs. The instruction set for the parallel interface is shown in Table 11 together with their execution time. Details about the parallel interface can be found in Section 11.1. Examples of operations on a 4-bit bus are given in Table 38, on a 8-bit bus in Table 39, Table 40 and Table 41. When using the I2C-bus, the instruction has to be commenced with a control byte as shown in Table 8. Details about the I2C-bus interface can be found in Section 11.2. An example of operations on the I2C-bus is given in Table 42. Instruction set for I2C-bus commands Table 8. Control byte CO [1] RS 0 0 0 0 0 0 Command byte I2C-bus command DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 [1] R/W is set together with the slave address (see Figure 30). Table 9. Control byte bit description Bit Symbol Value Description 7 CO 0 last control byte 1 another control byte follows after data/command 6 RS 0 instruction register selected 1 data register selected 0 default logic 0 4 to 0 - Instructions are of 4 types, those that: 1. Designate PCF2119x functions like display format, data length, etc. 2. Set internal RAM addresses 3. Perform data transfer with internal RAM 4. Others, like read ‘busy flag’ and read ‘address counter’ In normal use, type 3 instructions are used most frequently. However, automatic incrementing by 1 (or decrementing by 1) of internal RAM addresses after each data write lessens the microcontroller program load. The display shift in particular can be performed concurrently with display data write, enabling the designer to develop systems in minimum time with maximum programming efficiency. During internal operation, no instructions other than the BF_AC instruction will be executed. Because the busy flag is set to logic 1 while an instruction is being executed, check to ensure it is logic 0 before sending the next instruction or wait for the maximum instruction execution time, as given in Table 11. An instruction sent while the busy flag is logic 1 will not be executed. PCF2119X_5 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 05 — 13 August 2009 24 of 79 PCF2119x NXP Semiconductors LCD controllers/drivers The RS bit determines which register will be accessed and the R/W bit indicates if it is a read or a write operation (see Table 10). Table 10. Symbol Register access selection Value Description RS register select 0 instruction register[1] 1 data register[2] R/W read/write 0 write operation 1 read operation [1] There is only write access to the instruction register, but read access to the busy flag (BF) and the address counter (AC) of the BF_AC instruction (see Section 10.2.1.2). [2] Write and read access. Details of the instructions are explained in subsequent sections. 10.1 Data register The data register temporarily stores data to be read from the DDRAM and CGRAM. Prior to being read by the Read_data instruction, data from the DDRAM or CGRAM, corresponding to the address in the instruction register, is written to the data register. 10.2 Instruction register The instruction register stores instruction codes such as Clear_display, Curs_disp_shift, and address information for the Display Data RAM (DDRAM) and Character Generator RAM (CGRAM). The instruction register can be written to but not read from by the system controller. The instruction register is sectioned into basic, standard and extended instructions. Bit H = 1 of the Function_set instruction (see Section 10.2.1.1) sets the chip into extended instruction set mode. PCF2119X_5 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 05 — 13 August 2009 25 of 79 PCF2119x NXP Semiconductors LCD controllers/drivers Table 11. Instruction register overview Bits[1] Instruction RS R/W 7 6 5 4 3 2 1 0 Required clock cycles[2] Reference Basic instructions (bit H = 0 or 1) [3] 0 0 0 0 0 0 0 0 0 0 3 - Function_set 0 0 0 0 1 DL 0 M SL H 3 Section 10.2.1.1 BF_AC 0 1 BF AC 0 Section 10.2.1.2 Read_data 1 1 READ_DATA 3 Section 10.2.1.3 Write_data 1 0 WRITE_DATA 3 Section 10.2.1.4 NOP Standard instructions (bit H = 0) Clear_display 0 0 0 0 0 0 0 0 0 1 165 Section 10.2.2.1 Return_home 0 0 0 0 0 0 0 0 1 0 3 Section 10.2.2.2 Entry_mode_set 0 0 0 0 0 0 0 1 I_D S 3 Section 10.2.2.3 Display_ctl 0 0 0 0 0 0 1 D C B 3 Section 10.2.2.4 Curs_disp_shift 0 0 0 0 0 1 SC RL 0 0 Set_CGRAM 0 0 0 1 ACG Set_DDRAM 0 0 1 ADD 3 Section 10.2.2.5 3 Section 10.2.2.6 3 Section 10.2.2.7 Extended instructions (bit H = 1) [4] 0 0 0 0 0 0 0 0 0 1 - - Screen_conf 0 0 0 0 0 0 0 0 1 L 3 Section 10.2.3.1 Disp_conf 0 0 0 0 0 0 0 1 P Q 3 Section 10.2.3.2 Icon_ctl 0 0 0 0 0 0 1 IM IB DM 3 Section 10.2.3.3 Temp_ctl 0 0 0 0 0 1 0 0 TC1 TC2 3 Section 10.2.3.4 HV_gen 0 0 0 1 0 0 0 0 S1 S0 3 Section 10.2.3.5 VLCD_set 0 0 1 V VA or VB 3 Section 10.2.3.6 Reserved [1] The bits 0 to 7 correspond with the data bus lines DB0 to CB7. [2] fosc cycles. [3] No operation. [4] Do not use. PCF2119X_5 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 05 — 13 August 2009 26 of 79 PCF2119x NXP Semiconductors LCD controllers/drivers 10.2.1 Basic instructions (bit H = 0 or 1) 10.2.1.1 Function_set Table 12. Function_set bit description Bit Symbol Value Description RS - 0 see Table 10 R/W - 0 7 to 5 - 001 4 DL 3 - 2 fixed value interface data length (for parallel mode only) 0 [1] 2 × 4 bits (DB7 to DB4) 1 [2] 8 bits (DB7 to DB0) 0 unused [3] M 1 1 [4] SL 1 1:18 multiplex drive mode, 1 × 32 or 2 × 16 character display [4][5] H 1:9 multiplex drive mode, 1 × 16 character display instruction set control 0 1 10.2.1.2 2 line × 16 characters multiplex mode 0 0 number of display lines 1 line × 32 characters 0 basic instruction set plus standard instruction set [4] basic instruction set plus extended instruction set [1] When 4-bit width is selected, data is transmitted in two cycles using the parallel-bus. In a 4-bit application ports DB3 to DB0 should be left open-circuit (internal pull-ups). [2] Default value after power-on in I2C-bus mode. [3] No impact if SL = 1. [4] Due to the internal pull-ups on DB3 to DB0 in a 4-bit application, the first Function_set after power-on sets bits M, SL and H to logic 1. A second Function_set must be sent to set bits M, SL and H to the required values. [5] Independent of bit M and bit L of the Screen_conf instruction (see Section 10.2.3.1). Only row 1 to row 8 and row 17 are used. All other rows must be left open-circuit. The DDRAM map is the same as in the 2 × 16 character display mode, however, the second line cannot be displayed. BF_AC instructions Table 13. BF_AC bit Bit Symbol Value Description RS - 0 see Table 10 R/W - 1 7 BF 6 to 0 [1] AC [1] read busy flag 0 next instruction will be executed 1 internal operation is in progress; next instruction will not be executed until BF = 0 0000000 to 1111111 read address counter It is recommended that the BF status is checked before the next write operation is started. PCF2119X_5 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 05 — 13 August 2009 27 of 79 PCF2119x NXP Semiconductors LCD controllers/drivers Busy flag: The busy flag indicates the internal status of the PCF2119x. A logic 1 indicates that the chip is busy and further instructions will not be accepted. The busy flag is output to pin DB7 when bit RS = 0 and bit R/W = 1. Instructions should only be started after checking that the busy flag is at logic 0 or after waiting for the required number of cycles. Address counter: The address counter is used by both CGRAM and DDRAM, and its value is determined by the previous Set_CGRAM and Set_DDRAM instruction. After a read/write operation the address counter is automatically incremented or decremented by 1. The address counter value is output to the bus (DB6 to DB0) when bit RS = 0 and bit R/W = 1. 10.2.1.3 Read_data Table 14. Bit Read_data bit description Symbol Value Description see Table 10 RS - 1 R/W - 1 7 to 0 READ_DATA 00000000 to 11111111 read data from CGRAM or DDRAM Read_data from CGRAM or DDRAM: Read_data reads binary 8-bit data from the CGRAM or DDRAM. The most recent ‘set address’ command (Set_CGRAM or Set_DDRAM) determines whether the CGRAM or DDRAM is to be read. The Read_data instruction gates the content of the data register to the bus while pin E is HIGH. After pin E goes LOW again, internal operation increments (or decrements) the address counter and stores RAM data corresponding to the new address counter into the data register. There are only three instructions that update the data register: • Set_CGRAM • Set_DDRAM • Read_data from CGRAM or DDRAM Other instructions (e.g. Write_data, Curs_disp_shift, Clear_display and Return_home) do not modify the value of the data register. 10.2.1.4 Write_data Table 15. Bit Write_data bit description Symbol Value Description see Table 10 RS - 1 R/W - 0 7 to 0 WRITE_DATA 00000000 to 11111111 write data to CGRAM or DDRAM Write_data to CGRAM or DDRAM: Write_data writes binary 8-bit data to the CGRAM or the DDRAM. PCF2119X_5 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 05 — 13 August 2009 28 of 79 PCF2119x NXP Semiconductors LCD controllers/drivers The previous Set_CGRAM or Set_DDRAM command determines if data is written into CGRAM or DDRAM. After writing, the address counter automatically increments or decrements by 1, in accordance with the Entry_mode_set (see Section 10.2.2.3). Only bit 4 to bit 0 of CGRAM data are valid, bit 7 to bit 5 are ‘don’t care’. 10.2.2 Standard instructions (bit H = 0) 10.2.2.1 Clear_display Table 16. Bit Clear_display bit description Symbol Value Description see Table 10 RS - 0 R/W - 0 7 to 0 - 00000001 fixed value Clear_display: writes usually the character code 20h (blank pattern) into all DDRAM addresses except for the character sets ‘R’ and ‘V’ where the character code 20h is not a blank pattern. In addition Clear_display • sets the DDRAM address counter to logic 0 • returns the display to its original position, if it was shifted. Thus, the display disappears and the cursor or blink position goes to the left edge of the display • sets entry mode bit I_D = 1 (increment mode); bit S of entry mode does not change The instruction Clear_display requires extra execution time. This may be allowed by checking the busy flag bit BF or by waiting until the 165 clock cycles have elapsed. The latter must be applied where no read-back options are foreseen, as in some Chip-On-Glass (COG) applications. Remark: When using the character sets ‘R’ or ‘V’, where the character code 20h is not the blank pattern, the following alternative instruction set has to be used: 1. Switch display off (Display_ctl, bit D = 0). 2. Write a blank pattern into all DDRAM addresses (Write_data). 3. Switch display on (Display_ctl, bit D = 1). 10.2.2.2 Return_home Table 17. Bit Return_home bit description Symbol Value Description see Table 10 RS - 0 R/W - 0 7 to 0 - 00000010 fixed value Return_home: Sets the DDRAM address counter to logic 0 and switches a shifted display back to an unshifted state. The DDRAM content remain unchanged. The cursor or blink position goes to the left of the first display line. Bit I_D and bit S of the Entry_mode_set instruction remain unchanged. PCF2119X_5 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 05 — 13 August 2009 29 of 79 PCF2119x NXP Semiconductors LCD controllers/drivers 10.2.2.3 Entry_mode_set Table 18. Bit Entry_mode_set bit description Symbol Value Description see Table 10 RS - 0 R/W - 0 7 to 2 - 000001 1 I_D 0 fixed value address increment or decrement 0 DDRAM or CGRAM address decrements by 1, cursor moves to the left 1 DDRAM or CGRAM address increments by 1, cursor moves to the right S shift display to the left or right 0 display does not shift 1 display shifts Bit I_D: When bit I_D = 1 the DDRAM or CGRAM address increments by 1 when data is written into or read from the DDRAM or CGRAM. The cursor or blink position moves to the right. When bit I_D = 0 the DDRAM or CGRAM address decrements by 1 when data is written into or read from the DDRAM or CGRAM. The cursor or blink position moves to the left. The cursor underline and cursor character blink are inhibited when the CGRAM is accessed. Bit S: When bit S = 0, the display does not shift. During DDRAM write, when bit S = 1 and bit I_D = 0, the entire display shifts to the right; when bit S = 1 and bit I_D = 1, the entire display shifts to the left. Thus it appears as if the cursor stands still and the display moves. The display does not shift when reading from the DDRAM, or when writing to or reading from the CGRAM. 10.2.2.4 Display_ctl instructions Table 19. Display_ctl bit description Bit Symbol Value Description RS - 0 see Table 10 R/W - 0 7 to 3 2 00001 D display on or off 0 1 1 0 fixed value C display is off; chip is in power-down mode display is on cursor on or off 0 cursor is off 1 cursor is on B character blink on or off 0 character blink is off 1 character blink is on PCF2119X_5 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 05 — 13 August 2009 30 of 79 PCF2119x NXP Semiconductors LCD controllers/drivers Bit D: The display is on when bit D = 1 and off when bit D = 0. Display data in the DDRAM is not affected and can be displayed immediately by setting bit D = 1. When the display is off (bit D = 0) the chip is in partial power-down mode: • The LCD outputs are connected to VSS • The VLCD generator and bias generator are turned off Three oscillator cycles are required after sending the ‘display off’ instruction to ensure all outputs are at VSS, afterwards the oscillator can be stopped. If the oscillator is running during partial power-down mode (‘display off’) the chip can still execute instructions. Even lower current consumption is obtained by inhibiting the oscillator (pin OSC to VSS). To ensure IDD < 1 µA: • the parallel bus ports DB7 to DB0 should be connected to VDD • pins RS and R/W should be connected to VDD or left open-circuit • pin PD should be connected to VDD Recovery from power-down mode: • pin PD should be connected back to VSS • if necessary pin OSC should be connected back to VDD • a Display_ctl instruction with bit D = 1 should be sent Bit C: The cursor is displayed when bit C = 1 and inhibited when bit C = 0. Even if the cursor disappears, bit I_D and bit S (see Section 10.2.2.3) remain in operation during display data write. The cursor is displayed using 5 dots in the 8th line (see Figure 16). Bit B: The character indicated by the cursor blinks when bit B = 1. The character blink is displayed by switching between display characters and all dots on with a period of f osc approximately 1 second, with f blink = -------------52224 10.2.2.5 Curs_disp_shift Table 20. Curs_disp_shift bit description Bit Symbol Value Description RS - 0 see Table 10 R/W - 0 7 to 4 3 2 0001 SC cursor move or display shift 0 move cursor 1 shift display RL shift or move to the right or left 0 1 1 to 0 - fixed value 00 left shift or move right shift or move fixed value PCF2119X_5 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 05 — 13 August 2009 31 of 79 PCF2119x NXP Semiconductors LCD controllers/drivers Bits SC and RL: Curs_disp_shift moves the cursor position or the display to the right or left without writing or reading display data. This function is used to correct a character or move the cursor through the display. In 2-line displays, the cursor moves to the next line when it passes the last position (40) of the line. When the displayed data is shifted repeatedly all lines shift at the same time; displayed characters do not shift into the next line. The address counter content does not change if the only action performed is shift display (SC = 1) but increments or decrements with the shift cursor (SC = 0). 10.2.2.6 Set_CGRAM Table 21. Set_CGRAM bit description Bit Symbol Value Description see Table 10 RS - 0 R/W - 0 7 to 6 - 01 fixed value 5 to 0 ACG 000000 to 111111 set CGRAM address Set_CGRAM: Sets the CGRAM address bits ACG[5:0] into the address counter. Data can then be written to or read from the CGRAM. Remark: The CGRAM address uses the same address register as the DDRAM address. This register consists of 7 bits. But with the Set_CGRAM command, only bit 5 to bit 0 are set. Bit 6 can be set using the Set_DDRAM command first, or by using the auto-increment feature during CGRAM write. All bits 6 to 0 can be read using the BF_AC instruction. When writing to the lower part of the CGRAM, ensure that bit 6 of the address is not set (e.g. by an earlier DDRAM write). 10.2.2.7 Set_DDRAM Table 22. Set_DDRAM bit description Bit Symbol Value Description RS - 0 see Table 10 R/W - 0 7 - 1 fixed value 6 to 0 ADD 0000000 to 1111111 set DDRAM address Set_DDRAM: Sets the DDRAM address bits ADD[6:0] into the address counter. Data can then be written to or read from the DDRAM. PCF2119X_5 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 05 — 13 August 2009 32 of 79 PCF2119x NXP Semiconductors LCD controllers/drivers 10.2.3 Extended instructions (bit H = 1) 10.2.3.1 Screen_conf Table 23. Screen_conf bit description Bit Symbol Value Description RS - 0 see Table 10 R/W - 0 7 to 1 0 0000001 L fixed value screen configuration 0 split screen standard connection 1 split screen mirrored connection Screen_conf: • If bit L = 0, then the two halves of a split screen are connected in a standard way i.e. column 1/81, 2/82 to 80/160. • If bit L = 1, then the two halves of a split screen are connected in a mirrored way i.e. column 1/160, 2/159 to 80/81. This allows single layer PCB or glass layout. 10.2.3.2 Disp_conf Table 24. Disp_conf bit description Bit Symbol Value Description RS - 0 see Table 10 R/W - 0 7 to 2 1 000001 P fixed value display column configuration 0 column data: left to right; column data is displayed from column 1 to column 80 1 column data: right to left; column data is displayed from column 80 to column 1 0 Q display row configuration 0 row data: top to bottom; row data is displayed from row 1 to row 16 and icon row data in row 17 and row 18 in single line mode (SL = 1) row data is displayed from row 1 to row 8 and icon row data in row 17 1 row data: bottom to top; row data is displayed from row 16 to row 1 and icon row data in row 18 and row 17 in single line mode (SL = 1) row data is displayed from row 8 to row 1 and icon row data in row 17 Bit P: The P bit is used to flip the display left to right by mirroring the column data, as shown in Figure 18. This allows the display to be viewed from behind instead of front and enhances the flexibility in the assembly of equipment and avoids complicated data manipulation within the controller. PCF2119X_5 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 05 — 13 August 2009 33 of 79 PCF2119x NXP Semiconductors LCD controllers/drivers 0 P= =0 Q 1 P= =0 Q 013aaa122 Fig 18. Use of bit P Bit Q: The Q bit flips the display top to bottom by mirroring the row data, as shown in Figure 19. 0 P= =0 Q 0 P= =1 Q 013aaa113 Fig 19. Use of bit Q Combination of bit P and bit Q: A combination of P and Q allows the display to be rotated horizontally and vertically by 180 degree, as shown in Figure 20. This is useful for viewing the display from the opposite edge. 0 P= 0 = Q 1 P= =1 Q 013aaa123 Fig 20. Use of bit P and bit Q PCF2119X_5 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 05 — 13 August 2009 34 of 79 PCF2119x NXP Semiconductors LCD controllers/drivers 10.2.3.3 Icon_ctl Table 25. Icon_ctl bit description Bit Symbol Value Description see Table 10 RS - 0 R/W - 0 7 to 3 - 00001 2 IM 1 icon mode 0 character mode, full display 1 icon mode, only icons displayed IB icon blink 0 1 0 fixed value DM icon blink disabled icon blink enabled direct mode 0 off 1 on The PCF2119x can drive up to 160 icons. See Figure 21 and Figure 22 for CGRAM to icon mapping. Bit IM: When bit IM = 0, the chip is in character mode. In the character mode characters and icons are driven (multiplex drive mode 1:18 or 1:9). The VLCD generator, if used, produces the VLCDOUT voltage programmed with register VA. When bit IM = 1, the chip is in icon mode. In the icon mode only the icons are driven (multiplex drive mode 1:2). The VLCD generator, if used, produces the VLCDOUT voltage as programmed with register VB. Table 26. Normal/icon mode operation Bit IM Mode VLCDOUT 0 character mode generated from VA 1 icon mode generated from VB Bit IB: Icon blink control is independent of the cursor/character blink function. When bit IB = 0, the icon blink is disabled. Icon data is stored in CGRAM character 0 to 3 (4 × 8 × 5 = 160 bits for 160 icons). When bit IB = 1, the icon blink is enabled. In this case each icon is controlled by two bits. Blink consists of two half phases (corresponding to the cursor on and off phases called even and odd phases hereafter). Icon states for the even phase are stored in CGRAM characters 0 to 3 (4 × 8 × 5 = 160 bits for 160 icons). These bits also define icon state when icon blink is not used (see Table 27). Icon states for the odd phase are stored in CGRAM character 4 to 7 (another 160 bits for the 160 icons). When icon blink is disabled CGRAM characters 4 to 7 may be used as normal CGRAM characters. PCF2119X_5 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 05 — 13 August 2009 35 of 79 PCF2119x NXP Semiconductors LCD controllers/drivers Table 27. Blink effect for icons and cursor character blink Parameter Even phase Odd phase cursor character blink block (all on) normal (display character) icons state 1; CGRAM character 0 to 3 state 2; CGRAM character 4 to 7 display: COL 1 to 5 COL 6 to 10 COL 76 to 80 ROW 17 – 1 2 3 4 5 6 7 8 9 10 ROW 18 – 81 82 83 84 85 86 87 88 89 90 76 77 78 79 80 156 157 158 159 160 mgl249 block of 5 columns Fig 21. CGRAM to icon mapping (a) icon no. phase ROW/COL character codes 7 6 5 4 3 2 CGRAM address 1 MSB 0 6 LSB MSB 5 4 3 2 1 CGRAM data 0 4 3 2 1 LSB MSB icon view 0 LSB 1-5 even 17/1-5 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 1 6-10 even 17/6-10 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 1 0 11-15 even 17/11-15 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 1 1 0 76-80 even 17/76-80 0 0 0 0 0 0 0 1 0 0 0 1 1 1 1 1 1 1 1 1 81-85 even 18/1-5 0 0 0 0 0 0 1 0 0 0 1 0 0 0 0 1 1 0 0 0 156-160 even 18/76-80 0 0 0 0 0 0 1 1 0 0 1 1 1 1 1 1 1 1 0 1 1-5 odd (blink) 17/1-5 0 0 0 0 0 1 0 0 0 1 0 0 0 0 0 0 0 0 0 0 156-160 odd (blink) 18/76-80 0 0 0 0 0 1 1 1 0 1 1 1 1 1 1 0 0 1 1 0 mgk999 CGRAM data: logic 1 of a data bit turns the icon on and logic 0 turns the icon off. Character codes: bits 0 to 3 define the icon state when icon blink is disabled or during the even phase when icon blink is enabled. Bits 4 to 7 define the icon state during the odd phase when icon blink is enabled (not used for icons when icon blink is disabled) Fig 22. CGRAM to icon mapping (b) Bit DM: When DM = 0, the chip is not in the direct mode. Either the internal VLCD generator or an external voltage may be used to achieve VLCD. When DM = 1, the chip is in direct mode. The internal VLCD generator is turned off and the output VLCDOUT is directly connected VDD2 (i.e. the VLCD generator supply voltage). PCF2119X_5 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 05 — 13 August 2009 36 of 79 PCF2119x NXP Semiconductors LCD controllers/drivers Remark: In direct mode, no external VLCD is possible. The direct mode can be used to reduce the current consumption when the required output voltage VLCDOUT is close to the VDD2 supply voltage. This can be the case in icon mode or in MUX 1:9 (depending on LCD liquid properties). 10.2.3.4 Temp_ctl Table 28. Temp_ctl bit description Bit Symbol Value Description RS - 0 see Table 10 R/W - 0 7 to 2 - 000100 1 to 0 TC[1:0] 00 to 11 temperature coefficient The bit-field TC[1:0] selects the temperature coefficient for the internally generated VLCDOUT (see Table 29). TC[1:0] selection of VLCD temperature coefficient Table 29. 10.2.3.5 TC[1:0] Typical value Description 00 −0.16 %/K VLCD temperature coefficient 0 (default value) 10 −0.18 %/K VLCD temperature coefficient 1 01 −0.21 %/K VLCD temperature coefficient 2 11 −0.24 %/K VLCD temperature coefficient 3 HV_gen Table 30. HV_gen bit description Bit Symbol Value Description see Table 10 RS - 0 R/W - 0 7 to 2 - 010000 fixed value 1 to 0 S[1:0] 00 to 11 voltage multiplier A software configurable voltage multiplier is incorporated in the VLCD generator and can be set via the HV_gen command. The voltage multiplier control can be used to reduce current consumption by disconnecting internal voltage multiplier stages, depending on the required VLCDOUT output voltage (see Table 31). Table 31. Voltage multiplier control bits S[1:0] Description 00 set VLCD generator stages to 1 (2 × voltage multiplier) 01 set VLCD generator stages to 2 (3 × voltage multiplier) 10 set VLCD generator stages to 3 (4 × voltage multiplier) 11 do not use PCF2119X_5 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 05 — 13 August 2009 37 of 79 PCF2119x NXP Semiconductors LCD controllers/drivers 10.2.3.6 VLCD_set Table 32. VLCD_set bit description Bit Symbol Value Description see Table 10 RS - 0 R/W - 0 7 - 1 6 V 5 to 0 VA or VB fixed value set register VA or VB 0 set register VA 1 set register VB 000000 to 111111 factor for calculating VLCD The VLCD value is calculated with the Equation 2 on page 8. The multiplication factor is programmed by instruction. Two on-chip registers (VA and VB) hold the multiplication factor for the character mode and the icon mode, respectively. The generated VLCDOUT value is independent of VDD, allowing battery operation of the chip. Vx programming: 1. Send Function_set instruction with bit H = 1. 2. Send VLCD_set instruction to write to the voltage register: a. Bit 7 = 1 and bit 6 = 0: bit 5 to bit 0 are the multiplication factor for VLCD of character mode (VA). b. Bit 7 = 1 and bit 6 = 1: bit 5 to bit 0 are the multiplication factor for VLCD of icon mode (VB). c. Bit 5 to bit 0 = 0 switches VLCD generator off (when selected). d. During ‘display off’/power-down the VLCD generator is also disabled. 3. Send Function_set instruction with bit H = 0 to resume normal programming. PCF2119X_5 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 05 — 13 August 2009 38 of 79 PCF2119x NXP Semiconductors LCD controllers/drivers 11. Basic architecture 11.1 Parallel interface The PCF2119x can send data in either two 4-bit operations or one 8-bit operation and can thus interface to 4-bit or 8-bit microcontrollers. In 8-bit mode data is transferred as 8-bit bytes using the 8 ports DB7 to DB0. Three further control lines E, RS and R/W are required. In 4-bit mode data is transferred in two cycles of 4 bits each using ports DB7 to DB4 for the transaction. The higher order bits (corresponding to range of bit 7 to bit 4 in 8-bit mode) are sent in the first cycle and the lower order bits (bit 3 to bit 0 in 8-bit mode) in the second cycle. Data transfer is complete after two 4-bit data transfers. It should be noted that two cycles are also required for the busy flag check. 4-bit operation is selected by instruction (see Figure 23 to Figure 25 for examples of bus protocol). In 4-bit mode, ports DB3 to DB0 must be left open-circuit. They are pulled up to VDD internally. RS R/W E DB7 IR7 IR3 BF AC3 DR7 DR3 DB6 IR6 IR2 AC6 AC2 DR6 DR2 DB5 IR5 IR1 AC5 AC1 DR5 DR1 DB4 IR4 IR0 AC4 AC0 DR4 DR0 instruction write busy flag and address counter read data register read mga804 Fig 23. 4-bit transfer example PCF2119X_5 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 05 — 13 August 2009 39 of 79 PCF2119x NXP Semiconductors LCD controllers/drivers RS R/W E internal DB7 internal operation IR7 IR3 busy instruction write AC3 not busy busy flag check AC3 D7 busy flag check D3 instruction write mga805 IR7, IR3: instruction 7th, 3rd bit. AC3: address counter 3rd bit. D7, D3: data 7th, 3rd bit. Fig 24. An example of 4-bit data transfer timing sequence RS R/W E internal DB7 internal operation data instruction write busy busy busy flag check busy flag check not busy busy flag check data instruction write mga806 Fig 25. Example of busy flag checking timing sequence PCF2119X_5 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 05 — 13 August 2009 40 of 79 PCF2119x NXP Semiconductors LCD controllers/drivers 11.2 I2C-bus interface The I2C-bus is for bidirectional, two-line communication between different ICs or modules. The two lines are the Serial Data line (SDA) and the Serial Clock Line (SCL). Both lines must be connected to a positive supply via pull-up resistors. Data transfer may be initiated only when the bus is not busy. Each byte of eight bits is followed by an acknowledge bit. A slave receiver which is addressed must generate an acknowledge after the reception of each byte. Also a master receiver must generate an acknowledge after the reception of each byte that has been clocked out of the slave transmitter. The device that acknowledges must pull-down the SDA line during the acknowledge clock pulse, so that the SDA line is stable LOW during the HIGH period of the acknowledge related clock pulse (set-up and hold times must be taken into consideration). A master receiver must signal an end of data to the transmitter by not generating an acknowledge bit on the last byte that has been clocked out of the slave. In this event the transmitter must leave the data line HIGH to enable the master to generate a STOP condition. MASTER TRANSMITTER/ RECEIVER SLAVE RECEIVER SLAVE TRANSMITTER/ RECEIVER MASTER TRANSMITTER/ RECEIVER MASTER TRANSMITTER SDA SCL mga807 Fig 26. System configuration SDA SCL data line stable; data valid change of data allowed mbc621 Fig 27. Bit transfer SDA SDA SCL SCL S P START condition STOP condition mbc622 Fig 28. Definition of START and STOP conditions PCF2119X_5 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 05 — 13 August 2009 41 of 79 PCF2119x NXP Semiconductors LCD controllers/drivers data output by transmitter not acknowledge data output by receiver acknowledge SCL from master 1 2 8 9 S clock pulse for acknowledgement START condition mbc602 Fig 29. Acknowledgement on the I2C-bus 11.2.1 I2C-bus protocol One I2C-bus slave address is reserved for the PCF2119x (see Figure 30). S 0 1 1 1 0 1 A 0 0 slave address R/W 013aaa143 Fig 30. PCF2119x I2C-bus slave address Before any data is transmitted on the I2C-bus, the device which should respond is addressed first. The addressing is always carried out with the first byte transmitted after the START procedure. The I2C-bus configuration for the different PCF2119x read and write cycles is shown in Figure 31 to Figure 33. The slow down feature of the I2C-bus protocol (receiver holds SCL line LOW during internal operations) is not used in the PCF2119x. 11.2.2 I2C-bus definitions Definitions: • Transmitter: the device which sends the data to the bus. • Receiver: the device which receives the data from the bus. • Master: the device which initiates a transfer, generates clock signals and terminates a transfer. • Slave: the device addressed by a master. • Multi-master: more than one master can attempt to control the bus at the same time without corrupting the message. PCF2119X_5 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 05 — 13 August 2009 42 of 79 PCF2119x NXP Semiconductors LCD controllers/drivers • Arbitration: procedure to ensure that if more than one master simultaneously tries to control the bus, only one is allowed to do so and the message is not corrupted. • Synchronization: procedure to synchronize the clock signals of two or more devices. acknowledgement from PCF2119x S S 0 1 1 1 0 1 A 0 A 1 RS CONTROL BYTE A A 0 RS CONTROL BYTE A DATA BYTE A P DATA BYTE 0 2n ≥ 0 bytes slave address R/W Co n ≥ 0 bytes 1 byte Co update data pointer mgk899 Fig 31. Master transmits to slave receiver; write mode acknowledgement S S 0 1 1 1 0 1 A 0 A 1 RSCONTROL BYTE A DATA BYTE A 0 RSCONTROL BYTE A DATA BYTE(1) A 0 2n ≥ 0 bytes slave address Co acknowledgement S n ≥ 0 bytes 1 byte R/W Co SLAVE ADDRESS S A 1 A 0 acknowledgement DATA BYTE A n bytes R/W Co no acknowledgement DATA BYTE 1 P last byte update data pointer update data pointer mgg003 Last data byte is a dummy byte (may be omitted). Fig 32. Master reads after setting word address; writes word address, set RS; Read_data PCF2119X_5 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 05 — 13 August 2009 43 of 79 PCF2119x NXP Semiconductors LCD controllers/drivers acknowledgement from PCF2119x S SLAVE ADDRESS S A 1 A 0 acknowledgement from master DATA BYTE A n bytes R/W Co no acknowledgement from master DATA BYTE 1 P last byte update data pointer update data pointer 013aaa155 Fig 33. Master reads slave immediately after first byte; read mode (RS previously defined) PCF2119X_5 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 05 — 13 August 2009 44 of 79 PCF2119x NXP Semiconductors LCD controllers/drivers 12. Internal circuitry Table 33. Device protection circuits Symbol Pin VDD1 1 to 6 Internal circuit VDD1 VSS1 013aaa169 VDD2 7 to 14 VDD2 VSS1 VDD3 VSS2 013aaa170 15 to 18 VDD3 VSS1 013aaa171 VSS1 22 to 29 VSS2 30 to 35 VSS2 VSS1 013aaa172 VLCDSENSE 36 VLCDIN 44 to 49 VLCDOUT 37 to 43 SCL 151 to 152 SDA 156 to 157 OSC 168 PD 155 POR 154 T1 20 T2 21 VDD1 VSS1 013aaa174 T3 153 E 19 RS 159 R/W 158 DB0 to DB7 160 to 167 R1 to R18 58, 57 to 51, 142 to 149, 59, 100, 141 C1 to C80 VSS1 013aaa173 VLCDIN 140 to 101, 99 to 60 VSS1 013aaa175 PCF2119X_5 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 05 — 13 August 2009 45 of 79 PCF2119x NXP Semiconductors LCD controllers/drivers 13. Limiting values Table 34. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol Parameter Conditions Min Max Unit VDD1 supply voltage 1 logic −0.5 +6.5 V VLCD generator −0.5 +4.5 V −0.5 +7.5 V VDD related −0.5 VDD + 0.5 V VDD2 supply voltage 2 VDD3 supply voltage 3 VLCD LCD supply voltage VI/O(n) input/output voltage on any other pin VLCD related −0.5 VLCD + 0.5 V II input current DC level −10 +10 mA IO output current DC level −10 +10 mA IDD supply current −50 +50 mA ISS ground supply current −50 +50 mA IDD(LCD) LCD supply current −50 +50 mA Ptot total power dissipation - 400 mW Po output power - 100 mW VESD electrostatic discharge voltage HBM [1] - ±3000 V [2] - ±300 V latch-up current [3] - 200 mA storage temperature [4] −65 +150 °C dissipation per output MM Ilu Tstg [1] Pass level; Human Body Model (HBM) according to Ref. 5 “JESD22-A114”. [2] Pass level; Machine Model (MM), according to Ref. 6 “JESD22-A115”. [3] Pass level; latch-up testing, according to Ref. 7 “JESD78”. [4] According to the NXP store and transport conditions (see Ref. 9 “SNW-SQ-623”) the devices have to be stored at a temperature of +5 °C to +45 °C and a humidity of 25 % to 75 %. PCF2119X_5 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 05 — 13 August 2009 46 of 79 PCF2119x NXP Semiconductors LCD controllers/drivers 14. Static characteristics Table 35. Static characteristics VDD1 = 1.5 V to 5.5 V; VDD2 = VDD3 = 2.2 V to 4.0 V; VSS = 0 V; VLCD = 2.2 V to 6.5 V; Tamb = −40 °C to +85 °C; unless otherwise specified. Symbol Parameter Conditions Min Typ Max Unit VDD1 supply voltage 1 logic 1.5 - 5.5 V VDD2 supply voltage 2 2.2 - 4.0 V VDD3 supply voltage 3 internal VLCD generation; VLCD > VDD2 = VDD3 VLCD LCD supply voltage 2.2 - 6.5 V Supplies Ground supply current using external VLCD[1] ISS - 70 120 µA VDD = 3 V; VLCD = 5 V [2] - 35 80 µA icon mode; VDD = 3 V; VLCD = 2.5 V [2] - 25 45 µA - 0.5 5 µA - 190 400 µA ground supply current power-down mode; VDD = 3 V; VLCD = 2.5 V; DB7 to DB0, RS and R/W = 1; OSC = 0; PD = 1 Ground supply current using internal VLCD[1][3] ISS ground supply current VDD = 3 V; VLCD = 5 V [2] - 135 400 µA icon mode; VDD = 2.5 V; VLCD = 2.5 V [2] - 85 - µA Logic VIL LOW-level input voltage VSS1 - 0.3VDD1 V VIH HIGH-level input voltage 0.7VDD1 - VDD1 V Oscillator input; pin OSC VIL LOW-level input voltage VSS1 - VDD1 − 1. 2 V VIH HIGH-level input voltage VDD1 − 0. 1 - VDD1 V Data bus; pins DB7 to DB0 IOL LOW-level output current VOL = 0.4 V; VDD1 = 5 V 1.6 4 - mA IOH HIGH-level output current VOH = 4 V; VDD1 = 5 V −1 −8 - mA Ipu pull-up current VI = VSS1 0.04 0.15 1 µA IL leakage current VI = VDD1, 2, 3 or VSS1, 2 −1 - +1 µA 0 - 0.3VDD1 V I2C-bus; pins SDA and SCL Inputs: pins SDA and SCL VIL LOW-level input voltage VIH HIGH-level input voltage ILI input leakage current Ci input capacitance VI = VDD1, 2, 3 or VSS1, 2 PCF2119X_5 Product data sheet 0.7VDD1 - 5.5 V −1 - +1 µA - 5 - pF © NXP B.V. 2009. All rights reserved. Rev. 05 — 13 August 2009 47 of 79 PCF2119x NXP Semiconductors LCD controllers/drivers Table 35. Static characteristics …continued VDD1 = 1.5 V to 5.5 V; VDD2 = VDD3 = 2.2 V to 4.0 V; VSS = 0 V; VLCD = 2.2 V to 6.5 V; Tamb = −40 °C to +85 °C; unless otherwise specified. Symbol Parameter Conditions Min Typ Max Unit 3 - - mA 2 - - mA Output: pin SDA LOW-level output current VOL = 0.4 V; VDD1 > 2 V IOL VOL = 0.2 VDD1; VDD1 < 2 V LCD outputs output resistance RO row output, pins R1 to R18 [4] - 10 30 kΩ - 15 40 kΩ - 20 130 mV column output, pins C1 to C80 [4] ∆Vbias bias voltage variation on pins R1 to R18 and C1 to C80 [5] ∆VLCD LCD voltage variation Tamb = 25 °C [3] VLCD < 3 V - - 160 mV VLCD < 4 V - - 200 mV VLCD < 5 V - - 260 mV VLCD < 6 V - - 340 mV [1] LCD outputs are open-circuit; inputs at VDD or VSS; bus inactive. [2] Tamb = 25 °C; fosc = 200 kHz. [3] LCD outputs are open-circuit; VLCD generator is on; load current ILCD = 5 µA. [4] Resistance of output pins (R1 to R18 and C1 to C80) with a load current of 10 µA; outputs measured one at a time; external LCD supply VLCD = 3 V; VDD1 = VDD2 = VDD3 = 3 V. [5] LCD outputs open-circuit; external LCD supply. PCF2119X_5 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 05 — 13 August 2009 48 of 79 PCF2119x NXP Semiconductors LCD controllers/drivers 15. Dynamic characteristics Table 36. Dynamic characteristics VDD1 = 1.5 V to 5.5 V; VDD2 = VDD3 = 2.2 V to 4.0 V; VSS = 0 V; VLCD = 2.2 V to 6.5 V; Tamb = −40 °C to +85 °C; unless otherwise specified. Symbol Parameter Conditions Min Typ Max Unit Clock and oscillator ffr(LCD) LCD frame frequency internal clock; VDD = 5.0 V 45 95 147 Hz fosc oscillator frequency not available at any pin 140 250 450 kHz fosc(ext) external oscillator frequency 140 - 450 kHz - 200 300 µs - - ns td(startup)(OSC) [1] start-up delay time on pin OSC oscillator, after power-down Timing characteristics of parallel interface[2] Write operation (writing data from microcontroller to PCF2119x); see Figure 34 tcy(en) enable cycle time 500 tw(en) enable pulse width 220 - - ns tsu(A) address set-up time 50 - - ns th(A) address hold time 25 - - ns tsu(D) data input set-up time 60 - - ns th(D) data input hold time 25 - - ns Read operation (reading data from PCF2119x to microcontroller); see Figure 35 tcy(en) enable cycle time 500 - - ns tw(en) enable pulse width 220 - - ns tsu(A) address set-up time 50 - - ns th(A) address hold time 25 - - ns td(DV) data input valid delay time VDD1 > 2.2 V - - 150 ns VDD1 > 1.5 V - - 250 ns 20 - 100 ns th(D) data input hold time Timing characteristics of I2C-bus interface[2]; see Figure 36 fSCL SCL clock frequency - - 400 kHz tLOW LOW period of the SCL clock 1.3 - - µs tHIGH HIGH period of the SCL clock 0.6 - - µs tSU;DAT data set-up time 100 - - ns tHD;DAT data hold time 0 - - ns 15 + 0.1 Cb - 300 ns 15 + 0.1 Cb - 300 ns tr rise time of both SDA and SCL signals [1][3] tf fall time of both SDA and SCL signals [1][3] Cb capacitive load for each bus line - - 400 pF tSU;STA set-up time for a repeated START condition 0.6 - - µs tHD;STA hold time (repeated) START condition 0.6 - - µs PCF2119X_5 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 05 — 13 August 2009 49 of 79 PCF2119x NXP Semiconductors LCD controllers/drivers Table 36. Dynamic characteristics …continued VDD1 = 1.5 V to 5.5 V; VDD2 = VDD3 = 2.2 V to 4.0 V; VSS = 0 V; VLCD = 2.2 V to 6.5 V; Tamb = −40 °C to +85 °C; unless otherwise specified. Symbol Parameter tSU;STO Conditions Min Typ Max Unit set-up time for STOP condition 0.6 - - µs tSP pulse width of spikes that must be suppressed by the input filter - - 50 ns tBUF bus free time between a STOP and START condition 1.3 - - µs [1] Tested on sample base. [2] All timing values are valid within the operating supply voltage and ambient temperature range and are referenced to VIL and VIH with an input voltage swing of VSS to VDD. [3] Cb = total capacitance of one bus line in pF. RS VIH VIL VIH VIL tsu(A) R/W th(A) VIL VIL tw(en) E VIH th(A) VIH VIL VIL VIL th(D) tsu(D) VIH valid data VIL DB0 to DB7 VIH VIL mbk474 tcy(en) Fig 34. Parallel bus write operation sequence; writing data from microcontroller to PCF2119x RS VIH VIL VIH VIL tsu(A) R/W th(A) VIH VIH tw(en) VIH E th(A) VIH VIL VIL td(DV) VOH VOL DB0 to DB7 VIL th(D) VOH VOL mbk475 tcy(en) Fig 35. Parallel bus read operation sequence; writing data from PCF2119x to microcontroller PCF2119X_5 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 05 — 13 August 2009 50 of 79 PCF2119x NXP Semiconductors LCD controllers/drivers SDA tBUF tLOW tf SCL tHD;STA tr tHD;DAT tHIGH tSU;DAT SDA tSU;STA tSU;STO mga728 Fig 36. I2C-bus timing diagram PCF2119X_5 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 05 — 13 August 2009 51 of 79 PCF2119x NXP Semiconductors LCD controllers/drivers 16. Application information 16.1 General application information The required minimum value for the external capacitors in an application with the PCF2119x are: Cext from pins VLCD to VSS = 100 nF and for pins VDD to VSS = 470 nF. Higher capacitor values are recommended for ripple reduction. For COG applications the recommended ITO track resistance is to be minimized for the I/O and supply connections. Optimized values for these tracks are below 50 Ω for the supply and below 100 Ω for the I/O connections. Higher track resistance reduce performance and increase current consumption. To avoid accidental triggering of Power-On Reset (POR) (especially in COG applications), the supplies must be adequately decoupled. Depending on power supply quality, VDD1 may have to be risen above the specified minimum. When external LCD supply voltage is supplied, VLCDOUT should be left open-circuit to avoid any stray current, and VLCDIN must be connected to VLCDSENSE. 16.2 Power supply connections for internal VLCD generation 1.5 V to 5.5 V VDD1 2.2 V to 4.0 V VDD2 VDD3 2.2 V to 4.0 V VDD2 VDD3 GND VSS1 VSS2 GND VSS1 VSS2 VDD1 013aaa114 013aaa115 Decoupling capacitors are not shown in the drawings. Fig 37. Recommended VDD connections for internal VLCD generation VLCDIN VLCDOUT VSS2 VLCDSENSE 013aaa116 Fig 38. Recommended VLCD connections for internal VLCD generation PCF2119X_5 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 05 — 13 August 2009 52 of 79 PCF2119x NXP Semiconductors LCD controllers/drivers 16.3 Power supply connections for external VLCD generation 1.5 V to 5.5 V VDD1 2.2 V to 4.0 V VDD2 VDD3 GND VSS1 VSS2 2.2 V to 4.0 V VDD1 VDD2 VDD3 GND VSS1 VSS2 013aaa114 013aaa117 Decoupling capacitors are not shown in the drawings. Remark: When using an external VLCD, the internal VLCD generator must never be switched on otherwise damages will occur. Fig 39. Recommended VDD connections for external VLCD generation VLCDIN n.c. VSS2 VLCDOUT VLCDSENSE 013aaa118 Fig 40. Recommended VLCD connections for external VLCD generation 16.4 Information about VLCD connections VLCDIN — This input is used for generating the 5 LCD bias levels. It is the power supply for the bias level buffers. VLCDOUT — This is the VLCD output if VLCD is generated internally. In this case pin VLCDOUT must be connected to VLCDIN and to VLCDSENSE. VLCDSENSE — This input is used for the voltage multiplier’s regulation circuitry. When using the internal VLCD generation, this pin must be connected to VLCDOUT and VLCDIN. When using an external VLCD supply it must be connected to VLCDIN only. 16.5 Reducing current consumption Reducing current consumption can be achieved by one of the options given in Table 37. When VLCD lies outside the VDD range and must be generated, it is usually more efficient to use the on-chip VLCD generator than an external regulator. Table 37. Reducing current consumption Original mode Alternative mode character mode icon mode (control bit IM) display on display off (control bit D) VLCD generator operating direct mode any mode power-down mode (pin PD) PCF2119X_5 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 05 — 13 August 2009 53 of 79 PCF2119x NXP Semiconductors LCD controllers/drivers 16.6 Charge pump characteristics Typical graphs of the total power consumption of the PCF2119x using the internal charge pump are illustrated in Figure 41, Figure 42 and Figure 43. The graphs were obtained under the following conditions: • • • • • • Tamb = 25 °C VDD1 = VDD2 = VDD3 = 2.2 V (minimum), 2.7 V (typical) and 4.0 V (maximum) Normal mode fosc = internal oscillator multiplex drive mode 1:18 Typical current load for ILCD = 10 µA. For each multiplication factor there is a separate line. The line ends where it is not possible to get a higher voltage under its conditions (a higher multiplication factor is needed to get higher voltages). Connecting different displays may result in different current consumption. This affects the efficiency and the optimum multiplication factor to be used to generate a certain output voltage. mgw573 400 IDD (µA) 300 (2) 200 (3) (1) 100 0 1.25 2.75 4.25 5.75 7.25 VLCD (V) (1) 2 × multiplication factor. (2) 3 × multiplication factor. (3) 4 × multiplication factor. Fig 41. Typical charge pump characteristics (a), VDD = 2.2 V PCF2119X_5 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 05 — 13 August 2009 54 of 79 PCF2119x NXP Semiconductors LCD controllers/drivers mgw574 300 IDD (µA) (3) 200 (2) (1) 100 0 1.25 2.75 4.25 5.75 7.25 VLCD (V) (1) 2 × multiplication factor. (2) 3 × multiplication factor. (3) 4 × multiplication factor. Fig 42. Typical charge pump characteristics (b), VDD = 2.7 V mgw575 300 IDD (µA) (3) 200 (2) (1) 100 0 1.25 2.75 4.25 5.75 7.25 VLCD (V) (1) 2 × multiplication factor. (2) 3 × multiplication factor. (3) 4 × multiplication factor. Fig 43. Typical charge pump characteristics (c), VDD = 4.0 V PCF2119X_5 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 05 — 13 August 2009 55 of 79 PCF2119x NXP Semiconductors LCD controllers/drivers 16.7 Interfaces OSC R17, R18 VDD VDD 2 × 16 CHARACTER LCD DISPLAY PLUS 160 ICONS 2 PCF2119X 470 nF R1 to R16 VLCD 16 100 nF C1 to C80 VSS VSS 80 4,8 DB7 to DB4 DB3 to DB0 E 013aaa119 RS R/W Fig 44. Typical application using parallel interface, 4 or 8 bit bus possible VDD VDD VDD OSC VDD DB3/SAO R17, R18 2 R1 to R16 2 × 16 CHARACTER LCD DISPLAY PLUS 160 ICONS VDD PCF2119X 100 nF 16 VLCD 100 nF VSS VSS C1 to C80 80 R17, R18 2 R1 to R16 1 × 32 CHARACTER LCD DISPLAY PLUS 160 ICONS SCL SDA VSS OSC VDD DB3/SAO VDD PCF2119X 100 nF VLCD 100 nF VSS SCL SDA 16 C1 to C80 VSS 80 SCL SDA I2C MASTER, MICROCONTROLLER mgk898 Fig 45. Application using I2C-bus interface PCF2119X_5 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 05 — 13 August 2009 56 of 79 PCF2119x NXP Semiconductors LCD controllers/drivers 16.8 Connections with LCD modules R17 Icons R1 to R8 8 Character row 1 PCF2119X Character row 2 C1 to C80 80 R9 to R16 8 R18 013aaa120 Fig 46. Connecting PCF2119x with 2 × 16 character LCD C1 to C80 R17 R1 to R8 8 Icons Icons Character row 1 Character row 1 PCF2119X C1 to C80 80 R9 to R16 8 R18 013aaa121 Fig 47. Connecting PCF2119x with 1 × 32 character LCD PCF2119X_5 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 05 — 13 August 2009 57 of 79 PCF2119x NXP Semiconductors LCD controllers/drivers 16.9 4-bit operation, 1-line display using external reset The program must set functions prior to a 4-bit operation (see Table 38). When power is turned on, 8-bit operation is automatically selected and the PCF2119x attempts to perform the first write as an 8-bit operation. Since nothing is connected to ports DB0 to DB3, a rewrite is then required. However, since one operation is completed in two accesses of 4-bit operation, a rewrite is required to set the functions (see Table 38 step 3). Thus, DB4 to DB7 of the Function_set are written twice. Table 38. Step 4-bit operation, 1-line display example; using external reset (character set ‘A’) Instruction RS 1 2 4 5 6 Operation R/W DB7 DB6 DB5 DB4 power supply on initialized by the external reset; no display appears Function_set 0 3 Display 0 0 0 1 sets to 4-bit operation; in this instance operation is handled as 8-bit by initialization and only this instruction completes with one write 0 sets to 4-bit operation, selects 1-line display and VLCD = V0; 4-bit operation starts from this point and resetting is needed Function_set 0 0 0 0 1 0 0 0 0 0 0 0 Display_ctl 0 0 0 0 0 0 0 0 1 1 1 0 turns display and cursor on; entire display is blank after initialization Entry_mode_set 0 0 0 0 0 0 0 0 0 1 1 0 sets mode to increment the address by 1 and to shift the cursor to the right at the time of write to the DDRAM or CGRAM; display is not shifted Write_data to CGRAM/DDRAM 1 0 0 1 0 1 1 0 0 0 0 0 writes ‘P’; the DDRAM has already been selected by initialization at power-on; the cursor is incremented by 1 and shifted to the right P 16.10 8-bit operation, 1-line display using external reset Table 39 and Table 40 show an example of a 1-line display in 8-bit operation. The PCF2119x functions must be set by the Function_set instruction prior to display. Since the DDRAM can store data for 80 characters, the RAM can be used for advertising displays when combined with display shift operation. Since the display shift operation changes display position only and the DDRAM contents remain unchanged, display data entered first can be displayed when the Return_home operation is performed. Table 39. Step 8-bit operation, 1-line display example; using external reset (character set ‘A’) Instruction RS Display Operation R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 1 power supply on initialized by the external reset; no display appears 2 Function_set 0 3 0 0 0 1 1 0 0 0 0 sets to 8-bit operation, selects 1-line display and VLCD = V0 0 0 0 0 1 1 1 0 turns on display and cursor; entire display is blank after initialization Display_ctl 0 0 PCF2119X_5 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 05 — 13 August 2009 58 of 79 PCF2119x NXP Semiconductors LCD controllers/drivers Table 39. Step 8-bit operation, 1-line display example; using external reset (character set ‘A’) …continued Instruction RS 4 0 0 0 0 0 0 1 0 0 0 1 0 7 to 10 1 0 0 0 1 0 1 Entry_mode_set 13 Write_data to CGRAM/DDRAM 0 1 0 0 0 0 0 0 0 1 1 writes ‘H’ 1 0 0 0 PH PHILIP writes ‘ILIP’ 0 0 writes ‘S’ 0 0 0 1 1 1 1 1 PHILIPS PHILIPS 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HILIPS writes ‘M’ 1 1 0 1 ILIPS M MICROK 0 1 0 0 1 1 1 1 MICROKO 0 0 1 0 0 0 0 MICROKO shifts only the cursor position to the left shifts only the cursor position to the left 0 0 1 0 0 0 0 MICROKO 1 0 0 0 0 1 1 ICROCO writes ‘C’ correction; display moves to the left shifts the display and cursor to the right 0 0 1 1 1 0 0 MICROCO 0 0 1 0 1 0 0 MICROCO shifts only the cursor to the right Write_data to CGRAM/DDRAM 1 0 0 writes ‘M’ 1 0 0 1 1 0 1 ICROCOM 0 0 0 0 0 1 0 PHILIPS M Return_home 0 0 0 PCF2119X_5 Product data sheet writes ‘ICROK’ writes ‘O’ Curs_disp_shift 0 sets mode for display shift at the time of write writes space Curs_disp_shift 0 27 P Write_data to CGRAM/DDRAM 0 26 0 Curs_disp_shift 1 25 0 Curs_disp_shift 0 24 0 Write_data to CGRAM/DDRAM 0 23 0 writes ‘P’; the DDRAM has already been selected by initialization at power-on; the cursor is incremented by 1 and shifted to the right : 1 22 0 Write_data to CGRAM/DDRAM 15 to 19 21 1 : 12 20 1 Write_data to CGRAM/DDRAM 1 14 0 Write_data to CGRAM/DDRAM 1 11 0 sets mode to increment the address by 1 and to shift the cursor to the right at the time of the write to the DDRAM/CGRAM; display is not shifted Write_data to CGRAM/DDRAM 1 6 Operation Entry_mode_set 0 5 Display R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 returns both display and cursor to the original position (address 0) © NXP B.V. 2009. All rights reserved. Rev. 05 — 13 August 2009 59 of 79 PCF2119x NXP Semiconductors LCD controllers/drivers Table 40. Step 8-bit operation, 1-line display and icon example; using external reset (character set ‘A’) Instruction RS Display Operation R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 1 power supply on initialized by the external reset; no display appears 2 Function_set 0 3 1 1 0 0 0 0 0 0 0 0 0 1 1 1 0 turns on display and cursor; entire display is blank after initialization 0 0 0 0 0 0 0 1 0 0 0 0 0 7 0 0 Set_CGRAM 9 Write_data to CGRAM/DDRAM 0 1 0 0 0 0 1 0 1 0 10 0 1 0 1 0 writes data to CGRAM for icon even phase; icons appears 0 sets the CGRAM address to position of character 4; the CGRAM is selected 1 writes data to CGRAM for icon odd phase 0 0 0 0 1 0 1 0 0 0 0 0 0 1 sets bit H = 1 0 1 1 0 icons blink 0 0 0 0 1 0 1 0 0 0 0 1 1 0 0 0 1 sets bit H = 0 Set_DDRAM 0 1 0 0 0 0 0 0 0 0 0 0 0 sets the DDRAM address to the first position; DDRAM is selected Write_data to CGRAM/DDRAM 1 0 0 1 0 1 P Write_data to CGRAM/DDRAM 1 0 0 1 0 17 to 21 22 0 Function_set 0 16 0 Icon_ctl 0 15 0 sets the CGRAM address to position of character 0; the CGRAM is selected Function_set 0 14 0 : 0 13 1 : 8 12 1 Write_data to CGRAM/DDRAM 1 11 0 sets mode to increment the address by 1 and to shift the cursor to the right at the time of the write to the DD/CGRAM; display is not shifted Set_CGRAM 0 6 0 Entry_mode_set 0 5 0 Display_ctl 0 4 0 sets to 8-bit operation, selects 1-line display and VLCD = V0 0 writes ‘H’ 1 0 0 0 : PH PHILIPS writes ‘ILIPS’ PHILIPS returns both display and cursor to the original position (address 0) Return_home 0 0 0 0 0 0 0 0 1 0 PCF2119X_5 Product data sheet writes ‘P’; the cursor is incremented by 1 and shifted to the right © NXP B.V. 2009. All rights reserved. Rev. 05 — 13 August 2009 60 of 79 PCF2119x NXP Semiconductors LCD controllers/drivers 16.11 8-bit operation, 2-line display For a 2-line display the cursor automatically moves from the first to the second line after the 40th digit of the first line has been written. Thus, if there are only 8 characters in the first line, the DDRAM address must be set after the 8th character is completed (see Table 41). It should be noted that both lines of the display are always shifted together; data does not shift from one line to the other. Table 41. 8-bit operation, 2-line display example; using external reset (character set ‘A’) Instruction Step RS 1 power supply on initialized by the external reset; no display appears 2 Function_set 0 sets to 8-bit operation; selects 2-line display and VLCD generator off 0 turns on display and cursor; entire display is blank after initialization 0 3 0 0 1 0 0 0 0 0 0 0 0 0 0 1 0 6 to 10 0 0 1 1 0 0 1 1 1 0 0 0 0 1 0 0 0 0 P writes ‘P’; the DDRAM has already been selected by initialization at power-on; the cursor is incremented by 1 and shifted to the right PHILIP writes ‘HILIP’ writes ‘S’ 0 1 0 0 1 1 PHILIPS 1 0 0 0 0 0 0 PHILIPS 1 0 0 1 1 0 1 PHILIPS M PHILIPS MICROC Write_data to CGRAM/DDRAM 0 1 0 0 0 0 0 0 0 1 1 1 PHILIPS MICROCO 0 1 1 1 PHILIPS MICROCO Write_data to CGRAM/DDRAM 1 0 0 1 0 0 1 1 0 1 HILIPS ICROCOM PCF2119X_5 Product data sheet writes ‘ICROC’ writes ‘O’ 1 Write_data to CGRAM/DDRAM 0 sets DDRAM address to position the cursor at the head of the 2nd line writes ‘M’ : 0 Operation sets mode to increment the address by 1 and to shift the cursor to the right at the time of write to the CG/DDRAM; display is not shifted Write_data to CGRAM/ DDRAM 1 21 1 1 14 to 18 20 0 Set_DDRAM 1 19 0 Write_data to CGRAM/DDRAM 0 13 1 : 1 12 0 Write_data to CGRAM/DDRAM 1 11 1 Entry_mode_set 0 5 0 display mode on/off control 0 4 R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Display sets mode for display shift at the time of write writes ‘M’; display is shifted to the left; the first and second lines shift together © NXP B.V. 2009. All rights reserved. Rev. 05 — 13 August 2009 61 of 79 PCF2119x NXP Semiconductors LCD controllers/drivers Table 41. 8-bit operation, 2-line display example; using external reset (character set ‘A’) …continued Instruction Step RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Display 22 23 : Operation : Return_home 0 0 0 0 0 0 0 0 1 0 PHILIPS MICROCOM returns both display and cursor to the original position (address 0) 16.12 I2C-bus operation, 1-line display A control byte is required with most commands (see Table 42). Example of I2C-bus operation; 1-line display (using external reset, assuming pin SA0 = VSS)[1] Table 42. Step I2C-bus byte 1 I2C-bus 2 slave address for write Display start initialized; no display appears during the acknowledge cycle SDA will be pulled-down by the PCF2119x SA6 SA5 SA4 SA3 SA2 SA1 SA0 R/W Ack 0 3 4 1 1 1 0 1 0 0 1 send a control byte for Function_set control byte sets RS for following data bytes CO RS 0 0 0 0 0 0 Ack 0 0 0 0 0 0 0 0 1 selects 1-line display and VLCD = V0; SCL pulse during acknowledge cycle starts execution of instruction Function_set DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Ack 0 5 0 1 X 0 0 0 0 1 Display_ctl turns on display and cursor; entire display shows character code 20h (blank in ASCII-like character sets) DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Ack 0 6 0 0 0 1 1 1 0 1 Entry_mode_set sets mode to increment the address by 1 and to shift the cursor to the right at the time of write to the DDRAM or CGRAM; display is not shifted DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Ack 0 0 0 Operation 0 7 I2C-bus start 8 slave address for write 0 1 1 0 1 for writing data to DDRAM, RS must be set to 1; therefore a control byte is needed SA6 SA5 SA4 SA3 SA2 SA1 SA0 R/W Ack 0 9 10 1 1 1 0 1 0 0 1 send a control byte for Write_data CO RS 0 0 0 0 0 0 Ack 0 1 0 0 0 0 0 0 1 Write_data to DDRAM DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Ack 0 11 1 0 1 0 0 0 0 P 1 Write_data to DDRAM writes ‘H’ DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Ack 0 1 12 to 15 0 0 1 : 0 0 0 PH 1 PHILIP PCF2119X_5 Product data sheet writes ‘P’; the DDRAM has been selected at power-on; the cursor is incremented by 1 and shifted to the right writes ‘ILIP’ © NXP B.V. 2009. All rights reserved. Rev. 05 — 13 August 2009 62 of 79 PCF2119x NXP Semiconductors LCD controllers/drivers Example of I2C-bus operation; 1-line display (using external reset, assuming pin SA0 = VSS)[1] …continued Table 42. Step I2C-bus byte 16 Write_data to DDRAM Display DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Ack 0 1 0 l2C-bus 1 0 0 1 1 optional 18 I2C-bus start 19 slave address for write PHILIPS PHILIPS SA6 SA5 SA4 SA3 SA2 SA1 SA0 R/W Ack 0 20 1 PHILIPS 1 STOP 17 Operation writes ‘S’ 1 1 0 1 0 0 1 PHILIPS control byte 21 CO RS 0 0 0 0 0 0 Ack 1 0 0 0 0 0 0 0 1 PHILIPS Return_home DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Ack 0 0 0 0 22 I2C-bus start 23 slave address for read 0 0 1 0 1 24 1 1 1 0 1 0 1 PHILIPS 1 control byte for read CO RS 0 0 0 0 0 0 Ack 0 1 1 0 0 0 0 0 1 Read_data: 8 × SCL + master 25 X X X X PHILIPS acknowledge[2] DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Ack X X X X PHILIPS 0 Read_data: 8 × SCL + master acknowledge[2] 26 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Ack 0 1 0 0 1 0 0 0 PHILIPS 0 Read_data: 8 × SCL + no master acknowledge[2] 27 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Ack 0 1 0 I2C-bus STOP 28 0 1 0 0 1 PHILIPS 1 during the acknowledge cycle the content of the data register is loaded into the internal I2C-bus interface to be shifted out; in the previous instruction neither a ‘set address’ nor a Read_data has been performed; therefore the content of the data register was unknown; bit R/W has to be set to logic 1 while still in I2C-write mode DDRAM content will be read from following instructions 8 × SCL; content loaded into interface during previous acknowledge cycle is shifted out over SDA; MSB is DB7; during master acknowledge content of DDRAM address 01 is loaded into the I2C-bus interface 8 × SCL; code of letter ‘H’ is read first; during master acknowledge code of ‘I’ is loaded into the I2C-bus interface no master acknowledge; after the content of the I2C-bus interface register is shifted out no internal action is performed; no new data is loaded to the interface register, data register is not updated, address counter is not incremented and cursor is not shifted PHILIPS [1] X = don’t care. [2] SDA is left at high-impedance by the microcontroller during the read acknowledge. PCF2119X_5 Product data sheet sets DDRAM address 0 in address counter (also returns shifted display to original position; DDRAM contents unchanged); this instruction does not update the data register PHILIPS SA6 SA5 SA4 SA3 SA2 SA1 SA0 R/W Ack 0 PHILIPS © NXP B.V. 2009. All rights reserved. Rev. 05 — 13 August 2009 63 of 79 PCF2119x NXP Semiconductors LCD controllers/drivers 16.13 Initialization Initialization by instruction, 8-bit interface ([1]) Table 43. Step Instruction RS Description R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 1 power-on or unknown state 2 wait 2 ms after internal reset has been applied 3 Function_set 0 4 0 0 0 1 1 X X X X interface is 8 bits long; BF cannot be checked before this instruction 0 1 1 X X X X interface is 8 bits long; BF cannot be checked before this instruction X interface is 8 bits long; BF cannot be checked before this instruction wait 2 ms 5 Function_set 0 0 0 6 wait more than 40 µs 7 Function_set 0 0 0 0 1 1 X X X BF can be checked after the following instructions; when BF is not checked, the waiting time between instructions is the specified instruction time (see Table 11) 8 Function_set (interface is 8 bits long) 0 9 0 0 1 1 0 M 0 H Display_ctl 0 10 0 display off 0 0 0 0 1 0 0 0 0 0 0 0 0 0 1 0 0 0 0 1 I_D S Clear_display 0 11 0 0 Entry_mode_set 0 12 [1] 0 specify number of display lines 0 0 initialization ends X = don’t care. PCF2119X_5 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 05 — 13 August 2009 64 of 79 PCF2119x NXP Semiconductors LCD controllers/drivers Initialization by instruction, 4-bit interface; not applicable for I2C-bus operation Table 44. Step Instruction RS Description R/W DB7 DB6 DB5 DB4 1 power-on or unknown state 2 wait 2 ms after internal reset has been applied 3 Function_set 0 0 0 4 wait 2 ms 5 Function_set 0 6 7 0 0 0 0 1 interface is 8 bits long; BF cannot be checked before this instruction 1 1 interface is 8 bits long; BF cannot be checked before this instruction 1 1 interface is 8 bits long; BF cannot be checked before this instruction 1 wait more than 40 µs Function_set 0 0 0 0 BF can be checked after the following instructions; when BF is not checked, the waiting time between instructions is the specified instruction time (see Table 11) 8 Function_set 0 9 10 11 12 0 0 0 1 0 set interface to 4 bit long interface is 8 bit long Function_set 0 0 0 0 1 0 set interface to 4 bits long 0 0 0 M 0 H specify number of display line Display_ctl 0 0 0 0 0 0 0 0 1 0 0 0 display off Clear_display 0 0 0 0 0 0 0 0 0 0 0 1 Entry_mode_set 0 0 0 0 0 0 0 0 0 1 I_D S : 13 Initialization ends PCF2119X_5 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 05 — 13 August 2009 65 of 79 PCF2119x NXP Semiconductors LCD controllers/drivers 16.14 User defined characters and symbols Up to 16 user defined characters may be stored in the CGRAM. The content of the CGRAM is lost during power-down, therefore the CGRAM has to be rewritten after every power-on. 0 0 1 1 0 0 1 0 0 1 0 1 0 0 0 1 1 1 1 0 1 1 1 1 0 0 1 0 0 0 0 1 0 0 1 0 0 1 1 0 013aaa144 Fig 48. User defined euro currency sign Below some source code is printed, which shows how a user defined character is defined - in this case the euro currency sign. The display used is a 2 lines by 16 characters display and the interface is the I2C-bus: // Write a user defined character into the CGRAM startI2C(); // PCF2119 slave address for write, SA0 is connected to Vdd SendI2CAddress(0x70); // MSB (Continuation bit Co) = 0, more than one byte may follow. Bit6, RS=0, next byte // is command byte i2c_write(0x00); // 2 lines x 16, 1/18 duty, basic instruction set. Next byte will be another command. i2c_write(0x24); // Set CGRAM address to 0 i2c_write(0x40); // Repeated Start condition startI2C(); SendI2CAddress(0x70); // RS=1, next byte is a data byte i2c_write(0x40); // Here the data bytes to define the character // Behind the write commands the 5x8 dot matrix is shown, the 1 represents a on pixel. // The Euro currency character can be recognized by the 0/1 pattern (see Figure 48) i2c_write(0x06); // 00110 i2c_write(0x09); // 01001 i2c_write(0x08); // 01000 i2c_write(0x1E); // 11110 i2c_write(0x1E); // 11110 i2c_write(0x08); // 01000 i2c_write(0x09); // 01001 PCF2119X_5 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 05 — 13 August 2009 66 of 79 PCF2119x NXP Semiconductors LCD controllers/drivers i2c_write(0x06); // 00110 i2c_stop(); // Until here the definition of the character and writing it into the CGRAM. Now it // still needs to be displayed. See below. // PCF2119, setting of proper display modes startI2C(); // PCF2119 slave address for write, SA0 is connected to Vdd SendI2CAddress(0x70); // MSB (Continuation bit Co) = 0, more than one byte may follow. Bit6, RS=0, next byte // is command byte i2c_write(0x00); // 2 lines x 16, 1/18 duty, extended instruction set. Next byte will be another // command. i2c_write(0x25); // Set display configuration to right to left, column 80 to 1. Row data displ. top to // bottom,1 to 16. i2c_write(0x06); // Set to character mode, full display, icon blink disabled i2c_write(0x08); // Set voltage multiplier to 2 i2c_write(0x40); // Set Vlcd and store in register VA i2c_write(0xA0); // Change from extended instruction set to basic instruction set i2c_write(0x24); // Display control: set display on, cursor off, no blink i2c_write(0x0C); // Entry mode set, increase DDRAM after access, no shift i2c_write(0x06); // Return home, set DDRAM address 0 in address counter i2c_write(0x02); // Clear entire display, set DDRAM address to 0 in address counter i2c_write(0x01); // Repeated Start condition because RS needs to be changed from 0 to 1 startI2C(); SendI2CAddress(0x70); // RS=1, next byte is data i2c_write(0x40); // Write the character at address 0, which is the previously defined Euro currency // character i2c_write(0x00); i2c_stop(); PCF2119X_5 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 05 — 13 August 2009 67 of 79 PCF2119x NXP Semiconductors LCD controllers/drivers 17. Bare die outline Bare die: 168 bumps; 7.59 x 1.71 x 0.38 mm PCF2119X AM3 Z 50 75 74 100 126 125 150 149 AM4 D x y X Y 49 35 34 AM1 22 10 168 1 160 AM1 155 151 PC2119-2 E 0 19 0 e1 e A A1 b1 b L detail X detail Y 0 detail Z 2.5 5 mm scale Dimensions Unit mm A(1) A1(1) b(1) max 0.0225 nom 0.380 0.0175 0.050 min 0.0125 b1(1) D E 0.100 7.59 1.71 e(1) e1(1) L(1) 0.070 0.350 0.090 Note 1. Dimension not drawn to scale Outline version pcf2119x_do References IEC JEDEC JEITA European projection Issue date 09-07-16 09-08-03 PCF2119X Fig 49. Bare die outline of PCF2119x PCF2119X_5 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 05 — 13 August 2009 68 of 79 PCF2119x NXP Semiconductors LCD controllers/drivers Table 45. Pin location All X and Y coordinates are referenced to the center of the chip (dimensions in µm). Symbol Pin X Y Description logic supply voltage 1 VDD1 1 +745 −274 VDD1 2 +745 −204 VDD1 3 +745 −134 VDD1 4 +745 −64 VDD1 5 +745 +6 VDD1 6 +745 +76 VDD2 7 +745 +146 VDD2 8 +745 +216 VDD2 9 +745 +286 VDD2 10 +745 +356 VDD2 11 +745 +426 VDD2 12 +745 +496 VDD2 13 +745 +566 VDD2 14 +745 +636 VDD3 15 +745 +706 VDD3 16 +745 +776 VDD3 17 +745 +846 VDD3 18 +745 +916 E 19 +745 +986 data bus clock input T1 20 +745 +1196 test pin 1 T2 21 +745 +1406 test pin 2 VSS1 22 +745 +1616 ground 1 VSS1 23 +745 +1686 VSS1 24 +745 +1756 VSS1 25 +745 +1826 VSS1 26 +745 +1896 VSS1 27 +745 +1966 VSS1 28 +745 +2036 VSS1 29 +745 +2106 VSS2 30 +745 +2176 VSS2 31 +745 +2246 VSS2 32 +745 +2316 VSS2 33 +745 +2386 VSS2 34 +745 +2456 VSS2 35 +745 +2666 VLCDSENSE 36 +745 +2736 input for voltage multiplier regulation VLCDOUT 37 +745 +2806 VLCD output VLCDOUT 38 +745 +2876 VLCDOUT 39 +745 +2946 VLCDOUT 40 +745 +3016 PCF2119X_5 Product data sheet VLCD generator supply voltage 2 ground 2 © NXP B.V. 2009. All rights reserved. Rev. 05 — 13 August 2009 69 of 79 PCF2119x NXP Semiconductors LCD controllers/drivers Table 45. Pin location …continued All X and Y coordinates are referenced to the center of the chip (dimensions in µm). Symbol Pin X Y Description VLCDOUT 41 +745 +3086 VLCD output VLCDOUT 42 +745 +3156 VLCDOUT 43 +745 +3226 VLCDIN 44 +745 +3296 VLCDIN 45 +745 +3366 VLCDIN 46 +745 +3436 VLCDIN 47 +745 +3506 VLCDIN 48 +745 +3576 VLCDIN 49 +745 +3646 dummy (VSS1) 50 −745 +3576 dummy R8 51 −745 +3506 LCD row driver output R7 52 −745 +3436 R6 53 −745 +3366 R5 54 −745 +3296 R4 55 −745 +3226 R3 56 −745 +3156 R2 57 −745 +3086 R1 58 −745 +3016 R17 59 −745 +2946 C80 60 −745 +2876 C79 61 −745 +2806 C78 62 −745 +2736 C77 63 −745 +2666 C76 64 −745 +2596 C75 65 −745 +2526 C74 66 −745 +2456 C73 67 −745 +2386 C72 68 −745 +2316 C71 69 −745 +2246 C70 70 −745 +2176 C69 71 −745 +2106 C68 72 −745 +2036 C67 73 −745 +1966 C66 74 −745 +1896 C65 75 −745 +1756 C64 76 −745 +1686 C63 77 −745 +1616 C62 78 −745 +1546 C61 79 −745 +1476 C60 80 −745 +1406 PCF2119X_5 Product data sheet input for generation of LCD bias levels LCD column driver output © NXP B.V. 2009. All rights reserved. Rev. 05 — 13 August 2009 70 of 79 PCF2119x NXP Semiconductors LCD controllers/drivers Table 45. Pin location …continued All X and Y coordinates are referenced to the center of the chip (dimensions in µm). Symbol Pin X Y Description C59 81 −745 +1336 LCD column driver output C58 82 −745 +1266 C57 83 −745 +1196 C56 84 −745 +1126 C55 85 −745 +1056 C54 86 −745 +986 C53 87 −745 +916 C52 88 −745 +846 C51 89 −745 +776 C50 90 −745 +706 C49 91 −745 +636 C48 92 −745 +566 C47 93 −745 +496 C46 94 −745 +426 C45 95 −745 +356 C44 96 −745 +286 C43 97 −745 +216 C42 98 −745 +146 C41 99 −745 +76 R17DUP 100 −745 +6 LCD row driver output C40 101 −745 −64 LCD column driver output C39 102 −745 −134 C38 103 −745 −204 C37 104 −745 −274 C36 105 −745 −344 C35 106 −745 −414 C34 107 −745 −484 C33 108 −745 −554 C32 109 −745 −624 C31 110 −745 −694 C30 111 −745 −764 C29 112 −745 −834 C28 113 −745 −904 C27 114 −745 −974 C26 115 −745 −1044 C25 116 −745 −1114 C24 117 −745 −1184 C23 118 −745 −1254 C22 119 −745 −1324 C21 120 −745 −1394 PCF2119X_5 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 05 — 13 August 2009 71 of 79 PCF2119x NXP Semiconductors LCD controllers/drivers Table 45. Pin location …continued All X and Y coordinates are referenced to the center of the chip (dimensions in µm). Symbol Pin X Y Description C20 121 −745 −1464 LCD column driver output C19 122 −745 −1534 C18 123 −745 −1604 C17 124 −745 −1674 C16 125 −745 −1744 C15 126 −745 −1884 C14 127 −745 −1954 C13 128 −745 −2024 C12 129 −745 −2094 C11 130 −745 −2164 C10 131 −745 −2234 C9 132 −745 −2304 C8 133 −745 −2374 C7 134 −745 −2444 C6 135 −745 −2514 C5 136 −745 −2584 C4 137 −745 −2654 C3 138 −745 −2724 C2 139 −745 −2794 C1 140 −745 −2864 R18 141 −745 −2934 R9 142 −745 −3004 R10 143 −745 −3074 R11 144 −745 −3144 R12 145 −745 −3214 R13 146 −745 −3284 R14 147 −745 −3354 R15 148 −745 −3424 R16 149 −745 −3494 dummy (VSS1) 150 −745 −3704 dummy SCL 151 +745 −3704 I2C-bus serial clock input SCL 152 +745 −3634 T3 153 +745 −3494 test pin 3 POR 154 +745 −3424 external Power-On Reset (POR) input PD 155 +745 −3214 power-down mode select input SDA 156 +745 −3004 I2C-bus serial data input/output SDA 157 +745 −2934 R/W 158 +745 −2584 RS 159 +745 −2374 register select input DB0 160 +745 −2164 8-bit bidirectional data bus; bit 0 PCF2119X_5 Product data sheet LCD row driver output read/write input © NXP B.V. 2009. All rights reserved. Rev. 05 — 13 August 2009 72 of 79 PCF2119x NXP Semiconductors LCD controllers/drivers Table 45. Pin location …continued All X and Y coordinates are referenced to the center of the chip (dimensions in µm). Symbol Pin X Y Description DB1 161 +745 −1954 8-bit bidirectional data bus; bit 1 DB2 162 +745 −1744 8-bit bidirectional data bus; bit 2 DB3/SA0 163 +745 −1534 8-bit bidirectional data bus; bit 3 DB4 164 +745 −1324 8-bit bidirectional data bus; bit 4 DB5 165 +745 −1114 8-bit bidirectional data bus; bit 5 DB6 166 +745 −904 8-bit bidirectional data bus; bit 6 DB7 167 +745 −694 8-bit bidirectional data bus; bit 7 OSC 168 +745 −484 oscillator or external clock input Table 46. Alignment mark location All X and Y coordinates are referenced to the center of the chip (dimensions in µm). Symbol Pin X Y AM1 - +745 −2689 AM2 - +745 +2561 AM3 - −745 +3681 AM4 - −745 −3599 18. Handling information All input and output pins are protected against ElectroStatic Discharge (ESD) under normal handling. When handling Metal-Oxide Semiconductor (MOS) devices ensure that all normal precautions are taken as described in JESD625-A, IEC 61340-5 or equivalent standards. PCF2119X_5 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 05 — 13 August 2009 73 of 79 PCF2119x NXP Semiconductors LCD controllers/drivers 19. Packing information A 1.1 2.1 1.2 2.2 3.1 C x.1 D 1.3 F B 1.y y E x 001aai624 For dimensions see Table 47. Fig 50. Tray details Table 47. Tray dimensions Dimension Description Value A pocket pitch x direction 10.16 mm B pocket pitch y direction 4.45 mm C pocket width x direction 7.74 mm D pocket width y direction 1.91 mm E tray width x direction 50.8 mm F tray width y direction 50.8 mm x pockets in x direction 4 y pockets in y direction 10 PCF2119X_5 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 05 — 13 August 2009 74 of 79 PCF2119x NXP Semiconductors LCD controllers/drivers marking code 001aaj623 The orientation of the IC in a pocket is indicated by the position of the IC type name on the die surface with respect to the chamfer on the upper left corner of the tray. Refer to the bonding pin location diagram for the orientating and position of the type name on the die surface. Fig 51. Tray alignment PCF2119X_5 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 05 — 13 August 2009 75 of 79 PCF2119x NXP Semiconductors LCD controllers/drivers 20. Abbreviations Table 48. Abbreviations Acronym Description CGRAM Character Generator RAM CGROM Character Generator ROM CMOS Complementary Metal Oxide Semiconductor COG Chip-On-Glass DC Direct Current DDRAM Display Data RAM HBM Human Body Model I2C Inter-Integrated Circuit IC Integrated Circuit ITO Indium Tin Oxide LCD Liquid Crystal Display LSB Least Significant Bit MM Machine Model MSB Most Significant Bit MSL Moisture Sensitivity Level MUX Multiplexer PCB Printed-Circuit Board POR Power-On Reset RAM Random Access Memory RMS Root Mean Square ROM Read Only Memory SCL Serial Clock Line SDA Serial Data Line PCF2119X_5 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 05 — 13 August 2009 76 of 79 PCF2119x NXP Semiconductors LCD controllers/drivers 21. References [1] AN10170 — Design guidelines for COG modules with NXP monochrome LCD drivers [2] AN10706 — Handling bare die [3] IEC 60134 — Rating systems for electronic tubes and valves and analogous semiconductor devices [4] IEC 61340-5 — Protection of electronic devices from electrostatic phenomena [5] JESD22-A114 — Electrostatic Discharge (ESD) Sensitivity Testing Human Body Model (HBM) [6] JESD22-A115 — Electrostatic Discharge (ESD) Sensitivity Testing Machine Model (MM) [7] JESD78 — IC Latch-Up Test [8] JESD625-A — Requirements for Handling Electrostatic-Discharge-Sensitive (ESDS) Devices [9] SNW-SQ-623 — NXP store and transport conditions [10] UM10204 — I2C-bus specification and user manual 22. Revision history Table 49. Revision history Document ID Release date Data sheet status Change notice Supersedes PCF2119X_5 20090813 Product data sheet - PCF2119X_4 Modifications: • The format of this data sheet has been redesigned to comply with the new identity guidelines of NXP Semiconductors. • • Legal texts have been adapted to the new company name where appropriate. The entire data sheet has been reworked for better readability and understandability PCF2119X_4 20030130 Product specification - PCF2119X_3 PCF2119X_3 20020116 Product specification - PCF2119X_2 PCF2119X_2 19990302 Product specification - PCF2119X_1 PCF2119X_1 19971121 Objective specification - - PCF2119X_5 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 05 — 13 August 2009 77 of 79 PCF2119x NXP Semiconductors LCD controllers/drivers 23. Legal information 23.1 Data sheet status Document status[1][2] Product status[3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification. [1] Please consult the most recently issued document before initiating or completing a design. [2] The term ‘short data sheet’ is explained in section “Definitions”. [3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com. 23.2 Definitions Draft — The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet — A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. 23.3 Disclaimers General — Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use — NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk. Applications — Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Limiting values — Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) may cause permanent damage to the device. Limiting values are stress ratings only and operation of the device at these or any other conditions above those given in the Characteristics sections of this document is not implied. Exposure to limiting values for extended periods may affect device reliability. Terms and conditions of sale — NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, including those pertaining to warranty, intellectual property rights infringement and limitation of liability, unless explicitly otherwise agreed to in writing by NXP Semiconductors. In case of any inconsistency or conflict between information in this document and such terms and conditions, the latter will prevail. No offer to sell or license — Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. Export control — This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from national authorities. Bare die — All die are tested on compliance with their related technical specifications as stated in this data sheet up to the point of wafer sawing and are handled in accordance with the NXP Semiconductors storage and transportation conditions. If there are data sheet limits not guaranteed, these will be separately indicated in the data sheet. There are no post-packing tests performed on individual die or wafers. NXP Semiconductors has no control of third party procedures in the sawing, handling, packing or assembly of the die. Accordingly, NXP Semiconductors assumes no liability for device functionality or performance of the die or systems after third party sawing, handling, packing or assembly of the die. It is the responsibility of the customer to test and qualify their application in which the die is used. All die sales are conditioned upon and subject to the customer entering into a written die sale agreement with NXP Semiconductors through its legal department. 23.4 Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. I2C-bus — logo is a trademark of NXP B.V. 24. Contact information For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: [email protected] PCF2119X_5 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 05 — 13 August 2009 78 of 79 PCF2119x NXP Semiconductors LCD controllers/drivers 25. Contents 1 General description . . . . . . . . . . . . . . . . . . . . . . 1 2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 3 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 4 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 5 Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 6 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 3 7 Pinning information . . . . . . . . . . . . . . . . . . . . . . 4 7.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 7.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 5 8 Functional description . . . . . . . . . . . . . . . . . . . 7 8.1 Oscillator and timing generator. . . . . . . . . . . . . 7 8.1.1 Timing generator. . . . . . . . . . . . . . . . . . . . . . . . 7 8.1.2 Internal clock. . . . . . . . . . . . . . . . . . . . . . . . . . . 7 8.1.3 External clock . . . . . . . . . . . . . . . . . . . . . . . . . . 7 8.2 Reset function and Power-On Reset (POR) . . . 7 8.3 Power-down mode . . . . . . . . . . . . . . . . . . . . . . 8 8.4 LCD supply voltage generator . . . . . . . . . . . . . 8 8.4.1 Programming ranges . . . . . . . . . . . . . . . . . . . . 9 8.5 LCD bias voltage generator . . . . . . . . . . . . . . 10 8.6 LCD row and column drivers . . . . . . . . . . . . . 10 9 Display data RAM and ROM . . . . . . . . . . . . . . 14 9.1 DDRAM. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 9.2 CGROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 9.3 CGRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 9.4 Cursor control circuit. . . . . . . . . . . . . . . . . . . . 23 10 Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 10.1 Data register . . . . . . . . . . . . . . . . . . . . . . . . . . 25 10.2 Instruction register . . . . . . . . . . . . . . . . . . . . . 25 10.2.1 Basic instructions (bit H = 0 or 1) . . . . . . . . . . 27 10.2.1.1 Function_set . . . . . . . . . . . . . . . . . . . . . . . . . . 27 10.2.1.2 BF_AC instructions . . . . . . . . . . . . . . . . . . . . . 27 10.2.1.3 Read_data . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 10.2.1.4 Write_data . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 10.2.2 Standard instructions (bit H = 0) . . . . . . . . . . . 29 10.2.2.1 Clear_display . . . . . . . . . . . . . . . . . . . . . . . . . 29 10.2.2.2 Return_home . . . . . . . . . . . . . . . . . . . . . . . . . 29 10.2.2.3 Entry_mode_set . . . . . . . . . . . . . . . . . . . . . . . 30 10.2.2.4 Display_ctl instructions . . . . . . . . . . . . . . . . . . 30 10.2.2.5 Curs_disp_shift . . . . . . . . . . . . . . . . . . . . . . . . 31 10.2.2.6 Set_CGRAM . . . . . . . . . . . . . . . . . . . . . . . . . . 32 10.2.2.7 Set_DDRAM . . . . . . . . . . . . . . . . . . . . . . . . . . 32 10.2.3 Extended instructions (bit H = 1) . . . . . . . . . . 33 10.2.3.1 Screen_conf . . . . . . . . . . . . . . . . . . . . . . . . . . 33 10.2.3.2 Disp_conf . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 10.2.3.3 Icon_ctl . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 10.2.3.4 Temp_ctl . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 10.2.3.5 HV_gen . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.2.3.6 VLCD_set. . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Basic architecture . . . . . . . . . . . . . . . . . . . . . . 11.1 Parallel interface. . . . . . . . . . . . . . . . . . . . . . . 11.2 I2C-bus interface. . . . . . . . . . . . . . . . . . . . . . . 11.2.1 I2C-bus protocol . . . . . . . . . . . . . . . . . . . . . . . 11.2.2 I2C-bus definitions . . . . . . . . . . . . . . . . . . . . . 12 Internal circuitry . . . . . . . . . . . . . . . . . . . . . . . 13 Limiting values . . . . . . . . . . . . . . . . . . . . . . . . 14 Static characteristics . . . . . . . . . . . . . . . . . . . 15 Dynamic characteristics . . . . . . . . . . . . . . . . . 16 Application information . . . . . . . . . . . . . . . . . 16.1 General application information . . . . . . . . . . . 16.2 Power supply connections for internal VLCD generation . . . . . . . . . . . . . . . . . . . . . . . 16.3 Power supply connections for external VLCD generation . . . . . . . . . . . . . . . . . . . . . . . 16.4 Information about VLCD connections . . . . . . . 16.5 Reducing current consumption . . . . . . . . . . . 16.6 Charge pump characteristics . . . . . . . . . . . . . 16.7 Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16.8 Connections with LCD modules . . . . . . . . . . . 16.9 4-bit operation, 1-line display using external reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16.10 8-bit operation, 1-line display using external reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16.11 8-bit operation, 2-line display . . . . . . . . . . . . . 16.12 I2C-bus operation, 1-line display . . . . . . . . . . 16.13 Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . 16.14 User defined characters and symbols . . . . . . 17 Bare die outline . . . . . . . . . . . . . . . . . . . . . . . . 18 Handling information . . . . . . . . . . . . . . . . . . . 19 Packing information . . . . . . . . . . . . . . . . . . . . 20 Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . 21 References . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Revision history . . . . . . . . . . . . . . . . . . . . . . . 23 Legal information . . . . . . . . . . . . . . . . . . . . . . 23.1 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 23.2 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . 23.3 Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . 23.4 Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Contact information . . . . . . . . . . . . . . . . . . . . 25 Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 38 39 39 41 42 42 45 46 47 49 52 52 52 53 53 53 54 56 57 58 58 61 62 64 66 68 73 74 76 77 77 78 78 78 78 78 78 79 Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. © NXP B.V. 2009. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: [email protected] Date of release: 13 August 2009 Document identifier: PCF2119X_5