PCA9306 Dual bidirectional I2C-bus and SMBus voltage-level translator Rev. 02 — 21 February 2007 Product data sheet 1. General description The PCA9306 is a dual bidirectional I2C-bus and SMBus voltage-level translator with an enable (EN) input, and is operational from 1.1 V to 3.6 V (Vref(1)) and 2.3 V to 5.5 V (Vbias(ref)(2)). The PCA9306 allows bidirectional voltage translations between 1.2 V and 5 V without the use of a direction pin. The low ON-state resistance (Ron) of the switch allows connections to be made with minimal propagation delay. When EN is HIGH, the translator switch is on, and the SCL1 and SDA1 I/O are connected to the SCL2 and SDA2 I/O, respectively, allowing bidirectional data flow between ports. When EN is LOW, the translator switch is off, and a high-impedance state exists between ports. In I2C-bus applications, the bus capacitance limit of 400 pF restricts the number of devices and bus length. Using the PCA9306 enables the system designer to isolate two halves of a bus, thus more I2C-bus devices or longer trace length can be accommodated by using the enable pin. The PCA9306 is not a bus buffer like the PCA9509 or PCA9517 that provides level translation and physically isolates the capacitance to either side of the bus even when both sides are connected. The PCA9306 can also be used to run two buses, one at 400 kHz operating frequency and the other at 100 kHz operating frequency. If the two buses are operating at different frequencies, the 100 kHz bus must be isolated when the 400 kHz operation of the other bus is required. If the master is running at 400 kHz, the maximum system operating frequency may be less than 400 kHz because of the delays added by the translator. As with the standard I2C-bus system, pull-up resistors are required to provide the logic HIGH levels on the translator’s bus. The PCA9306 has a standard open-collector configuration of the I2C-bus. The size of these pull-up resistors depends on the system, but each side of the translator must have a pull-up resistor. The device is designed to work with Standard-mode, Fast-mode and Fast mode Plus I2C-bus devices in addition to SMBus devices. When the SDA1 or SDA2 port is LOW, the clamp is in the ON-state and a low resistance connection exists between the SDA1 and SDA2 ports. Assuming the higher voltage is on the SDA2 port when the SDA2 port is HIGH, the voltage on the SDA1 port is limited to the voltage set by VREF1. When the SDA1 port is HIGH, the SDA2 port is pulled to the drain pull-up supply voltage (Vpu(D)) by the pull-up resistors. This functionality allows a seamless translation between higher and lower voltages selected by the user without the need for directional control. The SCL1/SCL2 channel also functions as the SDA1/SDA2 channel. PCA9306 NXP Semiconductors Dual bidirectional I2C-bus and SMBus voltage-level translator All channels have the same electrical characteristics and there is minimal deviation from one output to another in voltage or propagation delay. This is a benefit over discrete transistor voltage translation solutions, since the fabrication of the switch is symmetrical. The translator provides excellent ESD protection to lower voltage devices, and at the same time protects less ESD-resistant devices. 2. Features n 2-bit bidirectional translator for SDA and SCL lines in mixed-mode I2C-bus applications n Standard-mode, Fast-mode, and Fast-mode Plus I2C-bus and SMBus compatible n Less than 1.5 ns maximum propagation delay to accommodate Standard mode and Fast mode I2C-bus devices and multiple masters n Allows voltage level translation between: u 1.0 V Vref(1) and 1.8 V, 2.5 V, 3.3 V or 5 V Vbias(ref)(2) u 1.2 V Vref(1) and 2.5 V, 3.3 V or 5 V Vbias(ref)(2) u 1.8 V Vref(1) and 3.3 V or 5 V Vbias(ref)(2) u 2.5 V Vref(1) and 5 V Vbias(ref)(2) u 3.3 V Vref(1) and 5 V Vbias(ref)(2) n Provides bidirectional voltage translation with no direction pin n Low 3.5 Ω ON-state connection between input and output ports provides less signal distortion n Open-drain I2C-bus I/O ports (SCL1, SDA1, SCL2 and SDA2) n 5 V tolerant I2C-bus I/O ports to support mixed-mode signal operation n High-impedance SCL1, SDA1, SCL2 and SDA2 pins for EN = LOW n Lock-up free operation for isolation when EN = LOW n Flow through pinout for ease of printed-circuit board trace routing n ESD protection exceeds 2000 V HBM per JESD22-A114, 200 V MM per JESD22-A115, and 1000 V CDM per JESD22-C101 n Packages offered: SO8, TSSOP8, VSSOP8, XQFN8 PCA9306_2 Product data sheet © NXP B.V. 2007. All rights reserved. Rev. 02 — 21 February 2007 2 of 21 PCA9306 NXP Semiconductors Dual bidirectional I2C-bus and SMBus voltage-level translator 3. Ordering information Table 1. Ordering information Tamb = −40 °C to +85 °C. Type number Topside mark Package Name Description Version PCA9306D PCA9306 SO8 plastic small outline package; 8 leads; body width 3.9 mm SOT96-1 PCA9306DP 306P TSSOP8[1] plastic thin shrink small outline package; 8 leads; body width 3 mm SOT505-1 PCA9306DC 306C VSSOP8 plastic very thin shrink small outline package; 8 leads; body width 2.3 mm SOT765-1 PCA9306DP1[2] 306T TSSOP8 plastic thin shrink small outline package; 8 leads; body width 3 mm; lead length 0.5 mm SOT505-2 PCA9306DC1[3] 306U VSSOP8 plastic very thin shrink small outline package; 8 leads; body width 2.3 mm SOT765-1 PCA9306GM P6X[4] XQFN8 plastic extremely thin quad flat package; no leads; 8 terminals; body 1.6 × 1.6 × 0.5 mm SOT902-1 [1] Also known as MSOP8. [2] Same footprint and pinout as the Texas Instruments PCA9306DCT. [3] Same footprint and pinout as the Texas Instruments PCA9306DCU. [4] ‘X’ will change based on date code. 4. Functional diagram VREF1 VREF2 2 7 PCA9306 SCL1 SDA1 3 4 SW SW 8 6 5 EN SCL2 SDA2 1 GND 002aab844 Fig 1. Logic diagram of PCA9306 (positive logic) PCA9306_2 Product data sheet © NXP B.V. 2007. All rights reserved. Rev. 02 — 21 February 2007 3 of 21 PCA9306 NXP Semiconductors Dual bidirectional I2C-bus and SMBus voltage-level translator 5. Pinning information 5.1 Pinning GND 1 8 EN VREF1 2 7 VREF2 SCL1 3 6 SDA1 4 5 PCA9306DP1 GND 1 8 EN VREF1 2 7 VREF2 SCL2 SCL1 3 SDA2 SDA1 4 PCA9306DP 002aab842 6 SCL2 5 SDA2 002aac373 Fig 2. Pin configuration for TSSOP8 VREF1 1 8 EN SCL1 2 7 VREF2 SDA1 3 6 GND 4 5 PCA9306DC Fig 3. Pin configuration for TSSOP8 (MSOP8) GND 1 8 EN VREF1 2 7 VREF2 SCL2 SCL1 3 SDA2 SDA1 4 PCA9306DC1 002aac374 6 SCL2 5 SDA2 002aab843 Fig 5. Pin configuration for VSSOP8 (DC1) GND EN terminal 1 index area 1 8 Fig 4. Pin configuration for VSSOP8 (DC) 7 VREF2 PCA9306GM 1 VREF1 2 8 EN 7 VREF2 2 6 SCL2 SCL1 3 5 SDA2 4 GND VREF1 SCL1 3 6 SCL2 SDA1 4 5 SDA2 002aac372 Fig 6. Pin configuration for SO8 PCA9306_2 Product data sheet SDA1 PCA9306D 002aac375 Transparent top view Fig 7. Pin configuration for XQFN8 © NXP B.V. 2007. All rights reserved. Rev. 02 — 21 February 2007 4 of 21 PCA9306 NXP Semiconductors Dual bidirectional I2C-bus and SMBus voltage-level translator 5.2 Pin description Table 2. Symbol Pin description Pin Description SO8, VSSOP8 (DC) TSSOP8 (MSOP8), TSSOP8, VSSOP8 (DC1), XQFN8 GND 1 4 ground (0 V) VREF1 2 1 low-voltage side reference supply voltage for SCL1 and SDA1 SCL1 3 2 serial clock, low-voltage side; connect to VREF1 through a pull-up resistor SDA1 4 3 serial data, low-voltage side; connect to VREF1 through a pull-up resistor SDA2 5 5 serial data, high-voltage side; connect to VREF2 through a pull-up resistor SCL2 6 6 serial clock, high-voltage side; connect to VREF2 through a pull-up resistor VREF2 7 7 high-voltage side reference supply voltage for SCL2 and SDA2 EN 8 8 switch enable input; connect to VREF2 and pull-up through a high resistor 6. Functional description Refer to Figure 1 “Logic diagram of PCA9306 (positive logic)”. 6.1 Function table Table 3. Function selection (example) H = HIGH level; L = LOW level. Input EN[1] Function H SCL1 = SCL2; SDA1 = SDA2 L disconnect [1] EN is controlled by the Vbias(ref)(2) logic levels and should be at least 1 V higher than Vref(1) for best translator operation. PCA9306_2 Product data sheet © NXP B.V. 2007. All rights reserved. Rev. 02 — 21 February 2007 5 of 21 PCA9306 NXP Semiconductors Dual bidirectional I2C-bus and SMBus voltage-level translator 7. Limiting values Table 4. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Over operating free-air temperature range. Symbol Parameter Vref(1) Vbias(ref)(2) Min Max Unit reference voltage (1) −0.5 +6 V reference bias voltage (2) −0.5 +6 V input voltage −0.5[1] +6 V VI/O voltage on an input/output pin −0.5[1] +6 V VI Ich channel current (DC) IIK input clamping current Tstg storage temperature [1] Conditions VI < 0 V - 128 mA - −50 mA −65 +150 °C The input and input/output negative voltage ratings may be exceeded if the input and input/output clamp current ratings are observed. 8. Recommended operating conditions Table 5. Operating conditions Symbol Parameter Conditions Min Typ Max Unit VI/O voltage on an input/output pin SCL1, SDA1, SCL2, SDA2 0 - 5 V Vref(1)[1] reference voltage (1) VREF1 0 - 5 V Vbias(ref)(2)[1] reference bias voltage (2) VREF2 0 - 5 V VI(EN) input voltage on pin EN 0 - 5 V Isw(pass) pass switch current - - 64 mA Tamb ambient temperature −40 - +85 °C [1] operating in free-air Vref(1) ≤ Vbias(ref)(2) − 1 V for best results in level shifting applications. PCA9306_2 Product data sheet © NXP B.V. 2007. All rights reserved. Rev. 02 — 21 February 2007 6 of 21 PCA9306 NXP Semiconductors Dual bidirectional I2C-bus and SMBus voltage-level translator 9. Static characteristics Table 6. Static characteristics Tamb = −40 °C to +85 °C, unless otherwise specified. Symbol Parameter Conditions Min Typ[1] Max Unit VIK input clamping voltage II = −18 mA; VI(EN) = 0 V - - −1.2 V IIH HIGH-level input current VI = 5 V; VI(EN) = 0 V - - 5 µA Ci(EN) input capacitance on pin EN VI = 3 V or 0 V - 7.1 - pF Cio(off) off-state input/output capacitance SCLn, SDAn; VO = 3 V or 0 V; VI(EN) = 0 V - 4 6 pF Cio(on) on-state input/output capacitance SCLn, SDAn; VO = 3 V or 0 V; VI(EN) = 3 V - 9.3 12.5 pF Ron ON-state resistance[2] SCLn, SDAn; VI = 0 V; IO = 64 mA [3] VI(EN) = 4.5 V - 2.4 5.0 Ω VI(EN) = 3 V - 3.0 6.0 Ω VI(EN) = 2.3 V - 3.8 8.0 Ω VI(EN) = 1.5 V - 9.0 20 Ω VI(EN) = 4.5 V - 4.8 7.5 Ω VI(EN) = 3 V - 46 80 Ω - 40 80 Ω VI = 2.4 V; IO = 15 mA VI = 1.7 V; IO = 15 mA VI(EN) = 2.3 V [1] All typical values are at Tamb = 25 °C. [2] Measured by the voltage drop between the SCL1 and SCL2, or SDA1 and SDA2 terminals at the indicated current through the switch. ON-state resistance is determined by the lowest voltage of the two terminals. [3] Guaranteed by design. PCA9306_2 Product data sheet © NXP B.V. 2007. All rights reserved. Rev. 02 — 21 February 2007 7 of 21 PCA9306 NXP Semiconductors Dual bidirectional I2C-bus and SMBus voltage-level translator 10. Dynamic characteristics Table 7. Dynamic characteristics (translating down) Tamb = −40 °C to +85 °C, unless otherwise specified. Values guaranteed by design. Symbol Parameter Conditions CL = 50 pF CL = 30 pF CL = 15 pF Min Max Min Max Min Max Unit VI(EN) = 3.3 V; VIH = 3.3 V; VIL = 0 V; VM = 1.15 V (see Figure 8) tPLH LOW-to-HIGH propagation delay from (input) SCL2 or SDA2 to (output) SCL1 or SDA1 0 2.0 0 1.2 0 0.6 ns tPHL HIGH-to-LOW propagation delay from (input) SCL2 or SDA2 to (output) SCL1 or SDA1 0 2.0 0 1.5 0 0.75 ns VI(EN) = 2.5 V; VIH = 2.5 V; VIL = 0 V; VM = 0.75 V (see Figure 8) tPLH LOW-to-HIGH propagation delay from (input) SCL2 or SDA2 to (output) SCL1 or SDA1 0 2.0 0 1.2 0 0.6 ns tPHL HIGH-to-LOW propagation delay from (input) SCL2 or SDA2 to (output) SCL1 or SDA1 0 2.5 0 1.5 0 0.75 ns Table 8. Dynamic characteristics (translating up) Tamb = −40 °C to +85 °C, unless otherwise specified. Values guaranteed by design. Symbol Parameter Conditions CL = 50 pF CL = 30 pF CL = 15 pF Min Min Max Min Max Max Unit VI(EN) = 3.3 V; VIH = 2.3 V; VIL = 0 V; VTT = 3.3 V; VM = 1.15 V; RL = 300 Ω (see Figure 8) tPLH LOW-to-HIGH propagation delay from (input) SCL1 or SDA1 to (output) SCL2 or SDA2 0 1.75 0 1.0 0 0.5 ns tPHL HIGH-to-LOW propagation delay from (input) SCL1 or SDA1 to (output) SCL2 or SDA2 0 2.75 0 1.65 0 0.8 ns VI(EN) = 2.5 V; VIH = 1.5 V; VIL = 0 V; VTT = 2.5 V; VM = 0.75 V; RL = 300 Ω (see Figure 8) tPLH LOW-to-HIGH propagation delay from (input) SCL1 or SDA1 to (output) SCL2 or SDA2 0 1.75 0 1.0 0 0.5 ns tPHL HIGH-to-LOW propagation delay from (input) SCL1 or SDA1 to (output) SCL2 or SDA2 0 3.3 0 2.0 0 1.0 ns VIH VTT input VM VM VIL RL S1 S2 (open) from output under test VOH output CL VM VM VOL 002aab846 002aab845 a. Load circuit b. Timing diagram S1 = translating up; S2 = translating down. CL includes probe and jig capacitance. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz; Zo = 50 Ω; tr ≤ 2 ns; tf ≤ 2 ns. The outputs are measured one at a time, with one transition per measurement. Fig 8. Load circuit for outputs PCA9306_2 Product data sheet © NXP B.V. 2007. All rights reserved. Rev. 02 — 21 February 2007 8 of 21 PCA9306 NXP Semiconductors Dual bidirectional I2C-bus and SMBus voltage-level translator 11. Application information Vpu(D) = 3.3 V(1) 200 kΩ PCA9306 Vref(1) = 1.8 V(1) VREF1 RPU 2 8 EN 7 RPU RPU VREF2 RPU VCC VCC SCL1 SCL I2C-BUS MASTER SDA SDA1 3 4 SW SW 6 5 SCL2 SCL I2C-BUS DEVICE SDA SDA2 1 GND GND GND 002aab847 (1) The applied voltages at Vref(1) and Vpu(D) should be such that Vbias(ref)(2) is at least 1 V higher than Vref(1) for best translator operation. Fig 9. Typical application circuit (switch always enabled) Vpu(D) = 3.3 V 3.3 V enable signal(1) on off 200 kΩ PCA9306 Vref(1) = 1.8 V(1) VREF1 RPU 2 8 EN 7 RPU RPU VCC VCC SCL I2C-BUS MASTER SDA GND RPU VREF2 SCL1 SDA1 3 4 SW SW 6 5 SCL2 SDA2 1 GND SCL I2C-BUS DEVICE SDA GND 002aab848 (1) In the Enabled mode, the applied enable voltage and the applied voltage at Vref(1) should be such that Vbias(ref)(2) is at least 1 V higher than Vref(1) for best translator operation. Fig 10. Typical application circuit (switch enable control) PCA9306_2 Product data sheet © NXP B.V. 2007. All rights reserved. Rev. 02 — 21 February 2007 9 of 21 PCA9306 NXP Semiconductors Dual bidirectional I2C-bus and SMBus voltage-level translator 11.1 Bidirectional translation For the bidirectional clamping configuration (higher voltage to lower voltage or lower voltage to higher voltage), the EN input must be connected to VREF2 and both pins pulled to HIGH side Vpu(D) through a pull-up resistor (typically 200 kΩ). This allows VREF2 to regulate the EN input. A filter capacitor on VREF2 is recommended. The I2C-bus master output can be totem-pole or open-drain (pull-up resistors may be required) and the I2C-bus device output can be totem-pole or open-drain (pull-up resistors are required to pull the SCL2 and SDA2 outputs to Vpu(D)). However, if either output is totem-pole, data must be unidirectional or the outputs must be 3-stateable and be controlled by some direction-control mechanism to prevent HIGH-to-LOW contentions in either direction. If both outputs are open-drain, no direction control is needed. The reference supply voltage (Vref(1)) is connected to the processor core power supply voltage. When VREF2 is connected through a 200 kΩ resistor to a 3.3 V to 5.5 V Vpu(D) power supply, and Vref(1) is set between 1.0 V and (Vpu(D) − 1 V), the output of each SCL1 and SDA1 has a maximum output voltage equal to VREF1, and the output of each SCL2 and SDA2 has a maximum output voltage equal to Vpu(D). Table 9. Application operating conditions Refer to Figure 9. Min Typ[1] Max Unit reference bias voltage (2) Vref(1) + 0.6 2.1 5 V VI(EN) input voltage on pin EN Vref(1) + 0.6 2.1 5 V Vref(1) reference voltage (1) 0 1.5 4.4 V Isw(pass) pass switch current - 14 - mA Iref reference current transistor - 5 - µA Tamb ambient temperature operating in free-air −40 - +85 °C Symbol Parameter Vbias(ref)(2) [1] Conditions All typical values are at Tamb = 25 °C. 11.2 Sizing pull-up resistor The pull-up resistor value needs to limit the current through the pass transistor when it is in the ON state to about 15 mA. This ensures a pass voltage of 260 mV to 350 mV. If the current through the pass transistor is higher than 15 mA, the pass voltage also is higher in the ON state. To set the current through each pass transistor at 15 mA, the pull-up resistor value is calculated as: V pu ( D ) – 0.35 V R PU = -------------------------------------0.015 A Table 10 summarizes resistor reference voltages and currents at 15 mA, 10 mA, and 3 mA. The resistor values shown in the +10 % column or a larger value should be used to ensure that the pass voltage of the transistor would be 350 mV or less. The external driver must be able to sink the total current from the resistors on both sides of the PCA9306 device at 0.175 V, although the 15 mA only applies to current flowing through the PCA9306 device. PCA9306_2 Product data sheet © NXP B.V. 2007. All rights reserved. Rev. 02 — 21 February 2007 10 of 21 PCA9306 NXP Semiconductors Dual bidirectional I2C-bus and SMBus voltage-level translator Table 10. Pull-up resistor values Calculated for VOL = 0.35 V; assumes output driver VOL = 0.175 V at stated current. Vpu(D) Pull-up resistor value (Ω) 15 mA 10 mA +10 %[1] Nominal +10 %[1] Nominal +10 %[1] 5V 310 341 465 512 1550 1705 3.3 V 197 217 295 325 983 1082 2.5 V 143 158 215 237 717 788 1.8 V 97 106 145 160 483 532 1.5 V 77 85 115 127 383 422 1.2 V 57 63 85 94 283 312 [1] +10 % to compensate for VCC range and resistor tolerance. PCA9306_2 Product data sheet 3 mA Nominal © NXP B.V. 2007. All rights reserved. Rev. 02 — 21 February 2007 11 of 21 PCA9306 NXP Semiconductors Dual bidirectional I2C-bus and SMBus voltage-level translator 12. Package outline SO8: plastic small outline package; 8 leads; body width 3.9 mm SOT96-1 D E A X c y HE v M A Z 5 8 Q A2 A (A 3) A1 pin 1 index θ Lp 1 L 4 e detail X w M bp 0 2.5 5 mm scale DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (2) e HE L Lp Q v w y Z (1) mm 1.75 0.25 0.10 1.45 1.25 0.25 0.49 0.36 0.25 0.19 5.0 4.8 4.0 3.8 1.27 6.2 5.8 1.05 1.0 0.4 0.7 0.6 0.25 0.25 0.1 0.7 0.3 inches 0.069 0.010 0.057 0.004 0.049 0.01 0.019 0.0100 0.014 0.0075 0.20 0.19 0.16 0.15 0.05 0.01 0.01 0.004 0.028 0.012 0.244 0.039 0.028 0.041 0.228 0.016 0.024 θ 8o o 0 Notes 1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included. 2. Plastic or metal protrusions of 0.25 mm (0.01 inch) maximum per side are not included. REFERENCES OUTLINE VERSION IEC JEDEC SOT96-1 076E03 MS-012 JEITA EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-18 Fig 11. Package outline SOT96-1 (SO8) PCA9306_2 Product data sheet © NXP B.V. 2007. All rights reserved. Rev. 02 — 21 February 2007 12 of 21 PCA9306 NXP Semiconductors Dual bidirectional I2C-bus and SMBus voltage-level translator TSSOP8: plastic thin shrink small outline package; 8 leads; body width 3 mm D E SOT505-1 A X c y HE v M A Z 5 8 A2 pin 1 index (A3) A1 A θ Lp L 1 4 detail X e w M bp 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max. A1 A2 A3 bp c D(1) E(2) e HE L Lp v w y Z(1) θ mm 1.1 0.15 0.05 0.95 0.80 0.25 0.45 0.25 0.28 0.15 3.1 2.9 3.1 2.9 0.65 5.1 4.7 0.94 0.7 0.4 0.1 0.1 0.1 0.70 0.35 6° 0° Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION REFERENCES IEC JEDEC JEITA EUROPEAN PROJECTION ISSUE DATE 99-04-09 03-02-18 SOT505-1 Fig 12. Package outline SOT505-1 (TSSOP8) PCA9306_2 Product data sheet © NXP B.V. 2007. All rights reserved. Rev. 02 — 21 February 2007 13 of 21 PCA9306 NXP Semiconductors Dual bidirectional I2C-bus and SMBus voltage-level translator TSSOP8: plastic thin shrink small outline package; 8 leads; body width 3 mm; lead length 0.5 mm D E A SOT505-2 X c HE y v M A Z 5 8 A A2 (A3) A1 pin 1 index θ Lp L 1 4 e detail X w M bp 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max. A1 A2 A3 bp c D(1) E(1) e HE L Lp v w y Z(1) θ mm 1.1 0.15 0.00 0.95 0.75 0.25 0.38 0.22 0.18 0.08 3.1 2.9 3.1 2.9 0.65 4.1 3.9 0.5 0.47 0.33 0.2 0.13 0.1 0.70 0.35 8° 0° Note 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. OUTLINE VERSION SOT505-2 REFERENCES IEC JEDEC JEITA EUROPEAN PROJECTION ISSUE DATE 02-01-16 --- Fig 13. Package outline SOT505-2 (TSSOP8) PCA9306_2 Product data sheet © NXP B.V. 2007. All rights reserved. Rev. 02 — 21 February 2007 14 of 21 PCA9306 NXP Semiconductors Dual bidirectional I2C-bus and SMBus voltage-level translator VSSOP8: plastic very thin shrink small outline package; 8 leads; body width 2.3 mm D E SOT765-1 A X c y HE v M A Z 5 8 Q A A2 A1 pin 1 index (A3) θ Lp 1 4 e L detail X w M bp 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max. A1 A2 A3 bp c D(1) E(2) e HE L Lp Q v w y Z(1) θ mm 1 0.15 0.00 0.85 0.60 0.12 0.27 0.17 0.23 0.08 2.1 1.9 2.4 2.2 0.5 3.2 3.0 0.4 0.40 0.15 0.21 0.19 0.2 0.13 0.1 0.4 0.1 8° 0° Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT765-1 REFERENCES IEC JEDEC JEITA EUROPEAN PROJECTION ISSUE DATE 02-06-07 MO-187 Fig 14. Package outline SOT765-1 (VSSOP8) PCA9306_2 Product data sheet © NXP B.V. 2007. All rights reserved. Rev. 02 — 21 February 2007 15 of 21 PCA9306 NXP Semiconductors Dual bidirectional I2C-bus and SMBus voltage-level translator XQFN8: plastic extremely thin quad flat package; no leads; 8 terminals; body 1.6 x 1.6 x 0.5 mm B D SOT902-1 A terminal 1 index area E A A1 detail X L1 e e C ∅v M C A B ∅w M C L 4 y1 C y 5 3 metal area not for soldering e1 b 2 6 e1 7 1 terminal 1 index area 8 X 0 1 2 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max A1 b D E e e1 L L1 v w y y1 mm 0.5 0.05 0.00 0.25 0.15 1.65 1.55 1.65 1.55 0.55 0.5 0.35 0.25 0.15 0.05 0.1 0.05 0.05 0.05 REFERENCES OUTLINE VERSION IEC JEDEC JEITA SOT902-1 --- MO-255 --- EUROPEAN PROJECTION ISSUE DATE 05-11-16 05-11-25 Fig 15. Package outline SOT902-1 (XQFN8) PCA9306_2 Product data sheet © NXP B.V. 2007. All rights reserved. Rev. 02 — 21 February 2007 16 of 21 PCA9306 NXP Semiconductors Dual bidirectional I2C-bus and SMBus voltage-level translator 13. Soldering This text provides a very brief insight into a complex technology. A more in-depth account of soldering ICs can be found in Application Note AN10365 “Surface mount reflow soldering description”. 13.1 Introduction to soldering Soldering is one of the most common methods through which packages are attached to Printed Circuit Boards (PCBs), to form electrical circuits. The soldered joint provides both the mechanical and the electrical connection. There is no single soldering method that is ideal for all IC packages. Wave soldering is often preferred when through-hole and Surface Mount Devices (SMDs) are mixed on one printed wiring board; however, it is not suitable for fine pitch SMDs. Reflow soldering is ideal for the small pitches and high densities that come with increased miniaturization. 13.2 Wave and reflow soldering Wave soldering is a joining technology in which the joints are made by solder coming from a standing wave of liquid solder. The wave soldering process is suitable for the following: • Through-hole components • Leaded or leadless SMDs, which are glued to the surface of the printed circuit board Not all SMDs can be wave soldered. Packages with solder balls, and some leadless packages which have solder lands underneath the body, cannot be wave soldered. Also, leaded SMDs with leads having a pitch smaller than ~0.6 mm cannot be wave soldered, due to an increased probability of bridging. The reflow soldering process involves applying solder paste to a board, followed by component placement and exposure to a temperature profile. Leaded packages, packages with solder balls, and leadless packages are all reflow solderable. Key characteristics in both wave and reflow soldering are: • • • • • • Board specifications, including the board finish, solder masks and vias Package footprints, including solder thieves and orientation The moisture sensitivity level of the packages Package placement Inspection and repair Lead-free soldering versus PbSn soldering 13.3 Wave soldering Key characteristics in wave soldering are: • Process issues, such as application of adhesive and flux, clinching of leads, board transport, the solder wave parameters, and the time during which components are exposed to the wave • Solder bath specifications, including temperature and impurities PCA9306_2 Product data sheet © NXP B.V. 2007. All rights reserved. Rev. 02 — 21 February 2007 17 of 21 PCA9306 NXP Semiconductors Dual bidirectional I2C-bus and SMBus voltage-level translator 13.4 Reflow soldering Key characteristics in reflow soldering are: • Lead-free versus SnPb soldering; note that a lead-free reflow process usually leads to higher minimum peak temperatures (see Figure 16) than a PbSn process, thus reducing the process window • Solder paste printing issues including smearing, release, and adjusting the process window for a mix of large and small components on one board • Reflow temperature profile; this profile includes preheat, reflow (in which the board is heated to the peak temperature) and cooling down. It is imperative that the peak temperature is high enough for the solder to make reliable solder joints (a solder paste characteristic). In addition, the peak temperature must be low enough that the packages and/or boards are not damaged. The peak temperature of the package depends on package thickness and volume and is classified in accordance with Table 11 and 12 Table 11. SnPb eutectic process (from J-STD-020C) Package thickness (mm) Package reflow temperature (°C) Volume (mm3) < 350 ≥ 350 < 2.5 235 220 ≥ 2.5 220 220 Table 12. Lead-free process (from J-STD-020C) Package thickness (mm) Package reflow temperature (°C) Volume (mm3) < 350 350 to 2000 > 2000 < 1.6 260 260 260 1.6 to 2.5 260 250 245 > 2.5 250 245 245 Moisture sensitivity precautions, as indicated on the packing, must be respected at all times. Studies have shown that small packages reach higher temperatures during reflow soldering, see Figure 16. PCA9306_2 Product data sheet © NXP B.V. 2007. All rights reserved. Rev. 02 — 21 February 2007 18 of 21 PCA9306 NXP Semiconductors Dual bidirectional I2C-bus and SMBus voltage-level translator maximum peak temperature = MSL limit, damage level temperature minimum peak temperature = minimum soldering temperature peak temperature time 001aac844 MSL: Moisture Sensitivity Level Fig 16. Temperature profiles for large and small components For further information on temperature profiles, refer to Application Note AN10365 “Surface mount reflow soldering description”. 14. Abbreviations Table 13. Abbreviations Acronym Description CDM Charged Device Model ESD ElectroStatic Discharge HBM Human Body Model I2C-bus Inter-Integrated Circuit bus I/O Input/Output MM Machine Model PRR Pulse Repetition Rate SMBus System Management Bus 15. Revision history Table 14. Revision history Document ID Release date Data sheet status Change notice Supersedes PCA9306_2 20070221 Product data sheet - PCA9306_1 Modifications: • Table 1 “Ordering information”: – changed topside mark for type number PCA9306GM from “P06” to “P6X” – added Table note 4 PCA9306_1 20061020 Product data sheet - PCA9306_2 Product data sheet - © NXP B.V. 2007. All rights reserved. Rev. 02 — 21 February 2007 19 of 21 PCA9306 NXP Semiconductors Dual bidirectional I2C-bus and SMBus voltage-level translator 16. Legal information 16.1 Data sheet status Document status[1][2] Product status[3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification. [1] Please consult the most recently issued document before initiating or completing a design. [2] The term ‘short data sheet’ is explained in section “Definitions”. [3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com. 16.2 Definitions Draft — The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet — A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. 16.3 Disclaimers General — Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use — NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or malfunction of a NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk. Applications — Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Limiting values — Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) may cause permanent damage to the device. Limiting values are stress ratings only and operation of the device at these or any other conditions above those given in the Characteristics sections of this document is not implied. Exposure to limiting values for extended periods may affect device reliability. Terms and conditions of sale — NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, including those pertaining to warranty, intellectual property rights infringement and limitation of liability, unless explicitly otherwise agreed to in writing by NXP Semiconductors. In case of any inconsistency or conflict between information in this document and such terms and conditions, the latter will prevail. No offer to sell or license — Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. 16.4 Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. I2C-bus — logo is a trademark of NXP B.V. 17. Contact information For additional information, please visit: http://www.nxp.com For sales office addresses, send an email to: [email protected] PCA9306_2 Product data sheet © NXP B.V. 2007. All rights reserved. Rev. 02 — 21 February 2007 20 of 21 PCA9306 NXP Semiconductors Dual bidirectional I2C-bus and SMBus voltage-level translator 18. Contents 1 2 3 4 5 5.1 5.2 6 6.1 7 8 9 10 11 11.1 11.2 12 13 13.1 13.2 13.3 13.4 14 15 16 16.1 16.2 16.3 16.4 17 18 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Ordering information . . . . . . . . . . . . . . . . . . . . . 3 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 3 Pinning information . . . . . . . . . . . . . . . . . . . . . . 4 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 5 Functional description . . . . . . . . . . . . . . . . . . . 5 Function table . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 6 Recommended operating conditions. . . . . . . . 6 Static characteristics. . . . . . . . . . . . . . . . . . . . . 7 Dynamic characteristics . . . . . . . . . . . . . . . . . . 8 Application information. . . . . . . . . . . . . . . . . . . 9 Bidirectional translation. . . . . . . . . . . . . . . . . . 10 Sizing pull-up resistor . . . . . . . . . . . . . . . . . . . 10 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 12 Soldering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Introduction to soldering . . . . . . . . . . . . . . . . . 17 Wave and reflow soldering . . . . . . . . . . . . . . . 17 Wave soldering . . . . . . . . . . . . . . . . . . . . . . . . 17 Reflow soldering . . . . . . . . . . . . . . . . . . . . . . . 18 Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Revision history . . . . . . . . . . . . . . . . . . . . . . . . 19 Legal information. . . . . . . . . . . . . . . . . . . . . . . 20 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 20 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Contact information. . . . . . . . . . . . . . . . . . . . . 20 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. © NXP B.V. 2007. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: [email protected] Date of release: 21 February 2007 Document identifier: PCA9306_2