INTEGRATED CIRCUITS DATA SHEET 74HCT7273 Octal D-type flip-flop with reset; positive edge-trigger; open drain outputs Product specification File under Integrated Circuits, IC06 1999 Oct 01 Philips Semiconductors Product specification Octal D-type flip-flop with reset; positive edge-trigger; open drain outputs 74HCT7273 FEATURES DESCRIPTION • ESD protection: HBM EIA/JESD22-A114-A Exceeds 2000 V MM EIA/JESD22-A115-A Exceeds 200 V The 74HCT7273 is a high-speed SI-gate CMOS device and is pin compatible with Low power Schottky TTL (LSTTL). It is specified in compliance with JEDEC standard no 7A. • Ideal buffer for MOS microprocessor or memory The 74HCT7273 has eight edge-triggered D-type flip-flops with individual D inputs and Q outputs. The common Clock (CP) and Master Reset (MR) inputs load and reset (clear) all flip-flops simultaneously. • Eight positive edge-triggered D-type flip-flops The state of each D input, one set-up time before the LOW-to-HIGH clock transition, is transferred to the corresponding output (Qn) of the flip-flop. • Common clock and master reset A LOW level on the MR input forces all outputs LOW, independently of the clock or data inputs. • Output capability: standard (open drain) • ICC category: MSI. The device is useful for applications requiring true outputs only and clock and master reset inputs that are common to all storage elements. The 74HCT7273 has open-drain N-outputs, which are clamped by a diode connected to VCC. When a HIGH is clocked in the flip-flop, the output comes in the high-impedance OFF-state. The output may now be pulled to any voltage between GND and VOmax. This allows the device to be used as a LOW-to-HIGH or HIGH-to-LOW level shifter. For digital operation and OR-tied output applications, the device must have a pull-up resistor to establish a logic HIGH level. QUICK REFERENCE DATA Ground = 0 V; Tamb = 25 °C; tr = tf = 6.0 ns. SYMBOL tPZL/tPLZ PARAMETER propagation delay CONDITIONS TYPICAL UNIT CL = 50 pF; VCC = 4.5 V CP to Qn 16 ns MR to Qn 23 ns fmax maximum clock frequency 56 MHz CI input capacitance 3.5 pF CPD power dissipation capacitance 37 pF CL = 50 pF; f = 1 MHz; notes 1 and 2 Notes 1. CPD is used to determine the dynamic power dissipation (PD in µW). PD = CPD × VCC2 × fi + ∑ (CL × VCC2 × fo) + ∑(V02/RL) × duty factor LOW where: fi = input frequency in MHz; fo = output frequency in MHz; ∑ (CL × VCC2 × fo) = sum of outputs; CL = output load capacitance in pF; RL = pull-up resistor in MΩ; VCC = supply voltage in Volts. 2. The condition is VI = GND to VCC − 1.5 V. 1999 Oct 01 2 Philips Semiconductors Product specification Octal D-type flip-flop with reset; positive edge-trigger; open drain outputs 74HCT7273 FUNCTION TABLE See note 1. INPUTS OUTPUTS OPERATING MODES MR CP Dn Qn Reset (clear) L X X L Load ‘1’ H ↑ h Z Load ‘0’ H ↑ l L Note 1. H = HIGH voltage level; h = HIGH voltage level one set-up time prior to the LOW-to-HIGH CP transition; L = LOW voltage level. l = LOW voltage level one set-up time prior to the LOW-to-HIGH CP transition; Z = high-impedance OFF-state; X = don’t care; ↑ = LOW-to-HIGH CP transition. ORDERING INFORMATION PACKAGE OUTSIDE NORTH AMERICA NORTH AMERICA 74HCT7273D 74HCT7273D 74HCT7273N 74HCT7273N 1999 Oct 01 TEMPERATURE RANGE PINS PACKAGE MATERIAL CODE −40 to +125 °C 20 SO plastic SOT163-1 20 DIP plastic SOT146-1 3 Philips Semiconductors Product specification Octal D-type flip-flop with reset; positive edge-trigger; open drain outputs 74HCT7273 PINNING PIN SYMBOL DESCRIPTION 1 MR asynchronous master reset (active LOW) 2, 5, 6, 9, 12, 15, 16, 19 Q0 to Q7 flip-flop outputs 3, 4, 7, 8, 13, 14, 17, 18 D0 to D7 data inputs 10 GND ground (0 V) 11 CP clock input (LOW-to-HIGH, edge triggered) 20 VCC DC supply voltage handbook, halfpage MR 1 20 VCC Q0 2 19 Q7 D0 3 18 D7 D1 4 17 D6 Q1 5 16 Q6 11 Q2 6 15 Q5 1 D2 7 14 D5 D3 8 13 D4 Q3 9 12 Q4 GND 10 11 CP 7273 3 4 7 8 13 14 17 18 D0 D1 D2 D3 D4 D5 D6 D7 MR Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 5 6 9 12 15 16 19 handbook, halfpage CP 2 MNA381 MNA380 Fig.1 Pin configuration. 1999 Oct 01 Fig.2 Logic symbol. 4 Philips Semiconductors Product specification Octal D-type flip-flop with reset; positive edge-trigger; open drain outputs handbook, halfpage 11 74HCT7273 C1 1 R 3 2 1D 4 5 7 6 8 9 13 12 14 15 17 16 18 19 MNA382 Fig.3 IEC logic symbol. 3 handbook, full pagewidth 4 D0 D1 D 11 1 7 Q 8 D2 D Q 13 D3 D Q 14 D4 D Q 17 D5 D Q 18 D7 D6 D Q D Q D Q FF1 FF2 FF3 FF4 FF5 FF6 FF7 FF8 CP RD CP RD CP RD CP RD CP RD CP RD CP RD CP RD CP MR Q0 2 Q1 5 Q2 6 Q3 9 Q4 12 Q5 15 Q6 16 Q7 19 MNA383 Fig.4 Functional diagram. 1999 Oct 01 5 This text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here in _white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here inThis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader. white to force landscape pages to be ... D Q D2 D Q D3 D Q D4 D Q D5 D Q D7 D6 D Q D Q D Q FF1 FF2 FF3 FF4 FF5 FF6 FF7 FF8 CP RD CP RD CP RD CP RD CP RD CP RD CP RD CP RD 6 CP Philips Semiconductors D1 Octal D-type flip-flop with reset; positive edge-trigger; open drain outputs handbook, full pagewidth 1999 Oct 01 D0 MR VCC VCC Q0 VCC Q1 VCC Q2 VCC Q3 VCC Q4 VCC Q5 VCC Q6 Q7 MNA384 Product specification 74HCT7273 Fig.5 Logic diagram. Philips Semiconductors Product specification Octal D-type flip-flop with reset; positive edge-trigger; open drain outputs 74HCT7273 RECOMMENDED OPERATING CONDITIONS TYPE SYMBOL PARAMETER CONDITIONS UNIT MIN. TYP. MAX. VCC DC supply voltage 4.5 5.0 5.5 V VI input voltage 0 − VCC V VO output voltage 0 − VCC V Tamb operating ambient temperature see DC and AC characteristics per device −40 − +85 °C −40 − +125 °C input rise and fall times except for Schmitt-trigger inputs VCC = 2.0 V − 6.0 500 ns/V VCC = 4.5 V − 6.0 500 VCC = 6.0 V − 6.0 500 tr,tf (∆t/∆f) LIMITING VALUES In accordance with the Absolute Maximum Rating System (IEC 134); voltages are referenced to GND (ground = 0 V). SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT −0.5 +7.0 V −0.5 +7.0 V − 20 mA VO < −0.5 V or VO > VCC + 0.5 V − ±20 mA −0.5V < VO < VCC + 0.5 V − 25 mA VCC DC supply voltage VO output voltage IIK DC input diode current VI < −0.5 V or VI > VCC + 0.5 V IOK DC output diode current IO DC output source or sink current ICC DC VCC or GND current − ±50 mA Tstg storage temperature −65 +150 °C PD power dissipation per package for temperature range: −40 to +125 °C plastic DIP note 1 − 750 mW plastic mini-pack (SO) note 2 − 500 mW Note 1. For DIP package: above 70 °C the value of PD derates linearly with 12 mW/K. 2. For SO package: above 70 °C the value of PD derates linearly with 8 mW/K. 1999 Oct 01 7 Philips Semiconductors Product specification Octal D-type flip-flop with reset; positive edge-trigger; open drain outputs 74HCT7273 DC CHARACTERISTICS Over recommended operating conditions; voltages are referenced to GND (ground = 0 V). Tamb (°C) TEST CONDITIONS SYMBOL −40 to +85 25 PARAMETER OTHER VCC (V) −40 to +125 UNIT MIN. TYP. MAX. MIN. MAX. MIN. MAX. VIH HIGH-level input voltage 4.5 to 5.5 2.0 1.6 − 2.0 − 2.0 − V VIL LOW-level input voltage 4.5 to 5.5 − 1.2 0.8 − 0.8 − 0.8 V VOL LOW-level output voltage VI = VIH or VIL; IO = 20 µA 4.5 − 0 0.1 − 0.1 − 0.1 V VI = VIH or VIL; IO = 4.0 mA 4.5 − 0.15 0.26 − 0.33 − 0.4 V µA II input leakage current VI = VIH or VIL 5.5 − − 0.1 − 1.0 − 1.0 IOZ HIGH level output leakage current VI = VIL; VO = VCC or GND 4.5 to 5.5 − − ±0.5 − ±5.0 − ±10.0 µA ICC quiescent supply VI = VCC or GND; current IO = 0 5.5 − − 8.0 − 80 − 160 µA ∆ICC additional quiescent supply current per input pin 4.5 to 5.5 − 100 360 − 450 − 490 µA VI = VCC − 2.1 V other inputs at VCC or GND; IO = 0; note 1 Note 1. The value off additional quiescent supply current (∆ICC) for a unit load of 1 is given in the specifications. To determine ∆ICC per input, multiply this value by the unit load coefficient shown in Table 1. Table 1 1999 Oct 01 INPUT UNIT LOAD COEFFICIENT MR 1.50 CP 1.50 Dn 0.40 8 Philips Semiconductors Product specification Octal D-type flip-flop with reset; positive edge-trigger; open drain outputs 74HCT7273 AC CHARACTERISTICS Ground = 0 V; tr = tf ≤ 6.0 ns; CL = 50 pF. TEST CONDITIONS SYMBOL Tamb (°C) 25 −40 to +85 MIN. TYP. MAX. MIN. MAX. MIN. MAX. PARAMETER WAVEFORMS VCC (V) −40 to +125 UNIT tPZL/tPLZ propagation delay see Figs 6 and 9 4.5 CP to Qn − 16 30 − 38 − 45 ns tPZL propagation delay see Figs 6 and 9 4.5 MR to Qn − 23 34 − 43 − 51 ns tTHL output transition time see Figs 6 and 9 4.5 − 7 15 − 19 − 22 ns tTLH output transition time see Figs 7 and 9 4.5 − − 110 − 110 − 110 ns tW clock pulse width HIGH or LOW see Figs 6 and 9 4.5 16 9 − 20 − 24 − ns tW master reset see Figs 7 and 9 4.5 pulse width; LOW 16 8 − 20 − 24 − ns trem removal time MR to CP see Figs 7 and 9 4.5 10 −2 − 13 − 15 − ns tsu set-up time Dn to CP see Figs 8 and 9 4.5 12 5 − 15 − 18 − ns th hold time Dn to CP see Figs 8 and 9 4.5 3 −4 − 3 − 3 − ns fmax maximum clock pulse frequency see Figs 6 and 9 4.5 30 56 − 24 − 20 − MHz 1999 Oct 01 9 Philips Semiconductors Product specification Octal D-type flip-flop with reset; positive edge-trigger; open drain outputs 74HCT7273 AC WAVEFORMS 1/fmax handbook, full pagewidth VI CP input VM GND tW t PZL VOH t PLZ 90% VM Qn output 10% VOL 10% MNA385 t THL VM = 1.3 V; VI = GND to 3 V. Fig.6 The clock (CP) to output (Qn) propagation delays, the clock pulse width, the output transition times and maximum clock pulse frequency. VCC handbook, full pagewidth VM MR input GND tW t rem VCC CP input VM GND t PHL t TLH VOH 90% VM Qn output 10% VOL MNA386 VM = 1.3 V; VI = GND to 3 V. Fig.7 Master reset (MR) pulse width, the master reset to output (Qn) propagation delays and the master reset to clock (CP). 1999 Oct 01 10 Philips Semiconductors Product specification Octal D-type flip-flop with reset; positive edge-trigger; open drain outputs 74HCT7273 VI handbook, full pagewidth VM CP input GND t su t su th th VI Dn input VM GND VOH Q n output VOL MNA387 VM = 1.3 V; VI = GND to 3 V. The shaded areas indicate when the input is permitted to change for predicable output performance. Fig.8 Data set-up and hold times for the data input (Dn). S1 handbook, full pagewidth VCC PULSE GENERATOR VI 1000 Ω VO VCC open GND D.U.T. CL RT MNA219 TEST S1 tPLH/tPHL open tPLZ/tPZL VCC tPHZ/tPZH GND Definitions for test circuit. CL = load capacitance including jig and probe capacitance (See Chapter “AC characteristics”). RT = termination resistance should be equal to the output impedance Zo of the pulse generator. Fig.9 Load circuit for switching times. 1999 Oct 01 11 Philips Semiconductors Product specification Octal D-type flip-flop with reset; positive edge-trigger; open drain outputs 74HCT7273 PACKAGE OUTLINES SO20: plastic small outline package; 20 leads; body width 7.5 mm SOT163-1 D E A X c HE y v M A Z 11 20 Q A2 A (A 3) A1 pin 1 index θ Lp L 1 10 e bp detail X w M 0 5 10 mm scale DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (1) e HE L Lp Q v w y mm 2.65 0.30 0.10 2.45 2.25 0.25 0.49 0.36 0.32 0.23 13.0 12.6 7.6 7.4 1.27 10.65 10.00 1.4 1.1 0.4 1.1 1.0 0.25 0.25 0.1 0.9 0.4 inches 0.10 0.012 0.096 0.004 0.089 0.01 0.019 0.013 0.014 0.009 0.51 0.49 0.30 0.29 0.050 0.419 0.043 0.055 0.394 0.016 0.043 0.039 0.01 0.01 0.004 0.035 0.016 Z (1) θ 8o 0o Note 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. REFERENCES OUTLINE VERSION IEC JEDEC SOT163-1 075E04 MS-013AC 1999 Oct 01 EIAJ EUROPEAN PROJECTION ISSUE DATE 95-01-24 97-05-22 12 Philips Semiconductors Product specification Octal D-type flip-flop with reset; positive edge-trigger; open drain outputs 74HCT7273 DIP20: plastic dual in-line package; 20 leads (300 mil) SOT146-1 ME seating plane D A2 A A1 L c e Z b1 w M (e 1) b MH 11 20 pin 1 index E 1 10 0 5 10 mm scale DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT A max. A1 min. A2 max. b b1 c mm 4.2 0.51 3.2 1.73 1.30 0.53 0.38 0.36 0.23 26.92 26.54 inches 0.17 0.020 0.13 0.068 0.051 0.021 0.015 0.014 0.009 1.060 1.045 D e e1 L ME MH w Z (1) max. 6.40 6.22 2.54 7.62 3.60 3.05 8.25 7.80 10.0 8.3 0.254 2.0 0.25 0.24 0.10 0.30 0.14 0.12 0.32 0.31 0.39 0.33 0.01 0.078 (1) E (1) Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT146-1 1999 Oct 01 REFERENCES IEC JEDEC EIAJ SC603 13 EUROPEAN PROJECTION ISSUE DATE 92-11-17 95-05-24 Philips Semiconductors Product specification Octal D-type flip-flop with reset; positive edge-trigger; open drain outputs SOLDERING 74HCT7273 If wave soldering is used the following conditions must be observed for optimal results: Introduction to soldering surface mount packages • Use a double-wave soldering method comprising a turbulent wave with high upward pressure followed by a smooth laminar wave. This text gives a very brief insight to a complex technology. A more in-depth account of soldering ICs can be found in our “Data Handbook IC26; Integrated Circuit Packages” (document order number 9398 652 90011). • For packages with leads on two sides and a pitch (e): – larger than or equal to 1.27 mm, the footprint longitudinal axis is preferred to be parallel to the transport direction of the printed-circuit board; There is no soldering method that is ideal for all surface mount IC packages. Wave soldering is not always suitable for surface mount ICs, or for printed-circuit boards with high population densities. In these situations reflow soldering is often used. – smaller than 1.27 mm, the footprint longitudinal axis must be parallel to the transport direction of the printed-circuit board. Reflow soldering The footprint must incorporate solder thieves at the downstream end. Reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. • For packages with leads on four sides, the footprint must be placed at a 45° angle to the transport direction of the printed-circuit board. The footprint must incorporate solder thieves downstream and at the side corners. Several methods exist for reflowing; for example, infrared/convection heating in a conveyor type oven. Throughput times (preheating, soldering and cooling) vary between 100 and 200 seconds depending on heating method. During placement and before soldering, the package must be fixed with a droplet of adhesive. The adhesive can be applied by screen printing, pin transfer or syringe dispensing. The package can be soldered after the adhesive is cured. Typical reflow peak temperatures range from 215 to 250 °C. The top-surface temperature of the packages should preferable be kept below 230 °C. Typical dwell time is 4 seconds at 250 °C. A mildly-activated flux will eliminate the need for removal of corrosive residues in most applications. Wave soldering Manual soldering Conventional single wave soldering is not recommended for surface mount devices (SMDs) or printed-circuit boards with a high component density, as solder bridging and non-wetting can present major problems. Fix the component by first soldering two diagonally-opposite end leads. Use a low voltage (24 V or less) soldering iron applied to the flat part of the lead. Contact time must be limited to 10 seconds at up to 300 °C. To overcome these problems the double-wave soldering method was specifically developed. When using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 °C. 1999 Oct 01 14 Philips Semiconductors Product specification Octal D-type flip-flop with reset; positive edge-trigger; open drain outputs 74HCT7273 Suitability of surface mount IC packages for wave and reflow soldering methods SOLDERING METHOD PACKAGE REFLOW(1) WAVE BGA, SQFP not suitable HLQFP, HSQFP, HSOP, SMS not PLCC(3), SO, SOJ suitable LQFP, QFP, TQFP SSOP, TSSOP, VSO suitable suitable(2) suitable suitable not recommended(3)(4) suitable not recommended(5) suitable Notes 1. All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the maximum temperature (with respect to time) and body size of the package, there is a risk that internal or external package cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). For details, refer to the Drypack information in the “Data Handbook IC26; Integrated Circuit Packages; Section: Packing Methods”. 2. These packages are not suitable for wave soldering as a solder joint between the printed-circuit board and heatsink (at bottom version) can not be achieved, and as solder may stick to the heatsink (on top version). 3. If wave soldering is considered, then the package must be placed at a 45° angle to the solder wave direction. The package footprint must incorporate solder thieves downstream and at the side corners. 4. Wave soldering is only suitable for LQFP, TQFP and QFP packages with a pitch (e) equal to or larger than 0.8 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm. 5. Wave soldering is only suitable for SSOP and TSSOP packages with a pitch (e) equal to or larger than 0.65 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm. Introduction to soldering through-hole mount packages This text gives a brief insight to wave, dip and manual soldering. A more in-depth account of soldering ICs can be found in our “Data Handbook IC26; Integrated Circuit Packages” (document order number 9398 652 90011). Wave soldering is the preferred method for mounting of through-hole mount IC packages on a printed-circuit board. Soldering by dipping or by solder wave The maximum permissible temperature of the solder is 260 °C; solder at this temperature must not be in contact with the joints for more than 5 seconds. The total contact time of successive solder waves must not exceed 5 seconds. The device may be mounted up to the seating plane, but the temperature of the plastic body must not exceed the specified maximum storage temperature (Tstg(max)). If the printed-circuit board has been pre-heated, forced cooling may be necessary immediately after soldering to keep the temperature within the permissible limit. Manual soldering Apply the soldering iron (24 V or less) to the lead(s) of the package, either below the seating plane or not more than 2 mm above it. If the temperature of the soldering iron bit is less than 300 °C it may remain in contact for up to 10 seconds. If the bit temperature is between 300 and 400 °C, contact may be up to 5 seconds. 1999 Oct 01 15 Philips Semiconductors Product specification Octal D-type flip-flop with reset; positive edge-trigger; open drain outputs 74HCT7273 Suitability of through-hole mount IC packages for dipping and wave soldering methods SOLDERING METHOD PACKAGE DIPPING DBS, DIP, HDIP, SDIP, SIL WAVE suitable(1) suitable Note 1. For SDIP packages, the longitudinal axis must be parallel to the transport direction of the printed-circuit board. DEFINITIONS Data sheet status Objective specification This data sheet contains target or goal specifications for product development. Preliminary specification This data sheet contains preliminary data; supplementary data may be published later. Product specification This data sheet contains final product specifications. Limiting values Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Where application information is given, it is advisory and does not form part of the specification. LIFE SUPPORT APPLICATIONS These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such improper use or sale. 1999 Oct 01 16 Philips Semiconductors Product specification Octal D-type flip-flop with reset; positive edge-trigger; open drain outputs NOTES 1999 Oct 01 17 74HCT7273 Philips Semiconductors Product specification Octal D-type flip-flop with reset; positive edge-trigger; open drain outputs NOTES 1999 Oct 01 18 74HCT7273 Philips Semiconductors Product specification Octal D-type flip-flop with reset; positive edge-trigger; open drain outputs NOTES 1999 Oct 01 19 74HCT7273 Philips Semiconductors – a worldwide company Argentina: see South America Australia: 3 Figtree Drive, HOMEBUSH, NSW 2140, Tel. +61 2 9704 8141, Fax. +61 2 9704 8139 Austria: Computerstr. 6, A-1101 WIEN, P.O. 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Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights. Printed in The Netherlands 245002/01/pp20 Date of release: 1999 Oct 01 Document order number: 9397 750 05733