INTEGRATED CIRCUITS 74AVC16835 18-bit registered driver (3-State) Preliminary specification Replaces datasheet 74AVC16835/74AVCH16835 dated 1998 Dec 07 1999 Jul 23 Philips Semiconductors Preliminary specification 18-bit Registered Driver (3-State) 74AVC16835 FEATURES PIN CONFIGURATION • Wide supply voltage range of 1.2 V to 3.6 V • Complies with JEDEC standard no. 8-1A/5/7. • CMOS low power consumption • Input/output tolerant up to 3.6 V • DCO (Dynamic Controlled Output) circuit dynamically changes output impedance, resulting in noise reduction without speed degradation • Low inductance multiple VCC and GND pins for minimum noise and ground bounce • Power off disables 74AVC16835 outputs, permitting Live Insertion DESCRIPTION The 74AVC16835 is a 18-bit universal bus driver. Data flow is controlled by output enable (OE), latch enable (LE) and clock inputs (CP). This product is designed to have an extremely fast propagation delay and a minimum amount of power consumption. To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup resistor (Live Insertion). A Dynamic Controlled Output (DCO) circuitry is implemented to support termination line drive during transient. See the graphs on page 8 for typical curves. NC 1 56 GND NC 2 55 NC Y0 3 54 A0 GND 4 53 GND Y1 5 52 A1 Y2 6 51 A2 VCC 7 50 VCC Y3 8 49 A3 Y4 9 48 A4 Y5 10 47 A5 GND 11 46 GND Y6 12 45 A6 Y7 13 44 A7 Y8 14 43 A8 Y9 15 42 A9 Y10 16 41 A10 Y11 17 40 A11 GND 18 39 GND Y12 19 38 A12 Y13 20 37 A13 Y14 21 36 A14 VCC 22 35 VCC Y15 23 34 A15 Y16 24 33 A16 GND 25 32 GND Y17 26 31 A17 OE 27 30 CP LE 28 29 GND SH00130 QUICK REFERENCE DATA GND = 0 V; Tamb = 25°C; tr = tf ≤ 2.0 ns; CL = 30 pF. PARAMETER SYMBOL CONDITIONS tPHL/tPLH Propagation delay An to Yn VCC = 1.8 V VCC = 2.5 V VCC = 3.3 V tPHL/tPLH Propagation delay LE to Yn; CP to Yn VCC = 1.8 V VCC = 2.5 V VCC = 3.3 V CI Input capacitance CPD Power dissipation dissi ation capacitance ca acitance per er buffer VI = GND to VCC1 TYPICAL 2.6 2.0 1.7 2.8 2.2 1.8 Outputs enabled Output disabled 5.0 25 6 UNIT ns ns pF pF F NOTES: 1. CPD is used to determine the dynamic power dissipation (PD in µW): PD = CPD × VCC2 × fi + S (CL × VCC2 × fo) where: fi = input frequency in MHz; CL = output load capacitance in pF; fo = output frequency in MHz; VCC = supply voltage in V; S (CL × VCC2 × fo) = sum of outputs. ORDERING INFORMATION PACKAGES 56-Pin Plastic Thin Shrink Small Outline (TSSOP) Type II 1999 Jul 23 2 TEMPERATURE RANGE ORDER CODE DRAWING NUMBER –40°C to +85°C 74AVC16835 DGG SOT364-1 Philips Semiconductors Preliminary specification 18-bit Registered Driver (3-State) 74AVC16835 PIN DESCRIPTION LOGIC SYMBOL (IEEE/IEC) PIN NUMBER SYMBOL 1, 2, 55 NC NAME AND FUNCTION No connection 3, 5, 6, 8, 9, 10, 12, 13, 14, 15, 16, 17, 19, 20, 21, 23, 24, 26 Y0 to Y17 4, 11, 18, 25, 32, 39, 46, 53, 56 GND 7, 22, 35, 50 VCC Positive supply voltage OE 27 28 CP 54, 52, 51, 49, 48, 47, 45, 44, 43, 42, 41, 40, 38, 37, 36, 34, 33, 31 27 CP 30 LE 28 EN1 2C3 C3 G2 LE 30 Data outputs OE A0 to A17 Y0 3 54 A0 Y1 5 52 A1 Y2 6 51 A2 Output enable input (active LOW) Y3 8 49 A3 Y4 9 48 A4 Latch enable input (active HIGH) Y5 10 47 A5 Y6 12 45 A6 Clock input Y7 13 44 A7 Y8 14 43 A8 Y9 15 42 Y10 16 41 A10 Y11 17 40 A11 Y12 19 38 A12 Y13 20 37 A13 Y14 21 36 A14 Y15 23 34 A15 Y16 24 33 A16 Y17 26 31 A17 Ground (0V) Data inputs LOGIC SYMBOL OE CP 1∇ 1 3D A9 SH00154 LE A0 FUNCTION TABLE D INPUTS LE Y0 CP TO THE 17 OTHER CHANNELS SH00138 H L X Z ↑ OUTPUTS OE LE CP A H X X X L H X L L L H X H H L L ↑ L L L L ↑ H H L L H X Y01 L L L X Y02 = = = = = Z HIGH voltage level LOW voltage level Don’t care High impedance “off” state LOW-to-HIGH level transition NOTES: 1. Output level before the indicated steady-state input conditions were established, provided that CP is high before LE goes low. 2. Output level before the indicated steady-state input conditions were established. 1999 Jul 23 3 Philips Semiconductors Preliminary specification 18-bit Registered Driver (3-State) 74AVC16835 SDRAM SDRAM SDRAM SDRAM SDRAM SDRAM SDRAM SDRAM SDRAM SDRAM SDRAM SDRAM SDRAM SDRAM SDRAM SDRAM 168-pin SDR SDRAM DIMM SDRAM SDRAM BACK SIDE FRONT SIDE AVC16835 AVC16835 AVC16835 PCK2509S or PCK2510S The PLL clock distribution device and AVC registered drivers reduce signal loads on the memory controller and prevent timing delays and waveform distortions that would cause unreliable operation SW00408 RECOMMENDED OPERATING CONDITIONS SYMBOL PARAMETER CONDITIONS MIN MAX UNIT 1.65 2.3 3.0 1.95 2.7 3.6 V 1.2 3.6 DC Input voltage range 0 3.6 DC output voltage range; output 3-State 0 3.6 DC output voltage range; output HIGH or LOW state 0 VCC –40 +85 °C 0 0 0 30 20 10 ns/V DC supply voltage (according to JEDEC Low Voltage Standards) VCC DC supply voltage (for low voltage applications) VI VO Tamb Operating free-air temperature range tr, tf Input rise and fall times 1999 Jul 23 V V VCC = 1.65 to 2.3 V VCC = 2.3 to 3.0 V VCC = 3.0 to 3.6 V 4 Philips Semiconductors Preliminary specification 18-bit Registered Driver (3-State) 74AVC16835 ABSOLUTE MAXIMUM RATINGS In accordance with the Absolute Maximum Rating System (IEC 134) Voltages are referenced to GND (ground = 0V) SYMBOL PARAMETER VCC CONDITIONS RATING DC supply voltage UNIT –0.5 to +4.6 V –50 mA –0.5 to 4.6 V IIK DC input diode current VI t0 VI DC input voltage For all inputs1 IOK DC output diode current VO uVCC or VO t 0 "50 mA VO DC output voltage; output 3-State Note 1 –0.5 to 4.6 V VO DC output voltage; output HIGH or LOW state Note 1 –0.5 to VCC +0.5 V IO DC output source or sink current VO = 0 to VCC IGND, ICC Tstg PTOT DC VCC or GND current Storage temperature range Power dissipation per package –plastic thin-medium-shrink (TSSOP) For temperature range: –40 to +125 °C above +55°C derate linearly with 8 mW/K "50 mA "100 mA –65 to +150 °C mW 600 NOTE: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed. DC ELECTRICAL CHARACTERISTICS Over recommended operating conditions. Voltage are referenced to GND (ground = 0 V). LIMITS SYMBOL PARAMETER TEST CONDITIONS VCC = 1.2 V VIH HIGH level Input In ut voltage VCC = 1.65 to 1.95 V Temp = -40°C to +85°C UNIT MIN TYP1 MAX VCC – – 0.65VCC 0.9 – VCC = 2.3 to 2.7 V 1.7 1.2 – VCC = 3.0 to 3.6 V V 2.0 1.5 – VCC = 1.2 V – – GND VCC = 1.65 to 1.95 V – 0.9 0.35VCC VCC = 2.3 to 2.7 V – 1.2 0.7 VCC = 3.0 to 3.6 V – 1.5 0.8 VCC = 1.65 to 3.6 V; VI = VIH or VIL; IO = –100 µA VCC*0.20 *0 20 VCC – VCC = 1.65 V; VI = VIH or VIL; IO = –4 mA VCC*0.45 VCC*0.10 – VCC = 2.3 V; VI = VIH or VIL; IO = –8 mA VCC*0.55 VCC*0.28 – VCC = 3.0 V; VI = VIH or VIL; IO = –12 mA VCC*0.70 VCC*0.32 – VCC = 1.65 to 3.6 V; VI = VIH or VIL; IO = 100 µA – GND 0 20 0.20 VCC = 1.65 V; VI = VIH or VIL; IO = 4 mA – 0.10 0.45 VCC = 2.3 V; VI = VIH or VIL; IO = 8 mA – 0.26 0.55 VCC = 3.0 V; VI = VIH or VIL; IO = 12 mA – 0.36 0.70 Input leakage g current VCC = 1.65 1 65 to 3.6 36V V; VI = VCC or GND – 0.1 2.5 µA µ IOFF 3-State output OFF-state current VCC = 0 V; VI or VO = 3.6 V – 0.1 "10 µA IIHZ/IILZ 3-State output OFF-state current VCC = 1.65 to 3.6 V; VI = VCC or GND – 0.1 12.5 µA VCC = 1.65 to 2.7 V; VI = VIH or VIL; VO = VCC or GND – 0.1 5 VCC = 3.0 to 3.6 V; VI = VIH or VIL; VO = VCC or GND – 0.1 10 VCC = 1.65 to 2.7 V; VI = VCC or GND; IO = 0 – 0.1 20 VCC = 3.0 to 3.6 V; VI = VCC or GND; IO = 0 – 0.2 40 VIL VOH VOL II IOZ ICC LOW level In Input ut voltage HIGH level output voltage LOW level output voltage 3-State out ut OFF-state current output Quiescent su supply ly current NOTES: 1. All typical values are at Tamb = 25°C. 1999 Jul 23 5 V V V µA µA Philips Semiconductors Preliminary specification 18-bit Registered Driver (3-State) 74AVC16835 AC CHARACTERISTICS GND = 0V; tr = tf ≤ 2.0ns; CL = 30pF LIMITS SYMBOL PARAMETER WAVEFORM VCC = 3.3 ± 0.3V VCC = 2.5 ± 0.2V VCC = 1.8 ± 0.15V VCC = 1.2V MIN TYP1 MAX MIN TYP1 MAX MIN TYP1 MAX TYP UNIT Propagation delay An to Yn 1, 7 0.7 1.7 2.5 0.8 2.0 3.0 1.0 2.6 4.5 5.2 Propagation delay LE to Yn 2, 7 0.7 1.8 2.7 0.8 2.2 3.3 1.0 2.8 5.0 5.6 Propagation delay CP to Yn 3, 7 0.7 1.7 2.5 0.8 2.0 3.0 1.0 2.6 4.5 5.2 tPZH/tPZL 3-State output enable time OE to Yn 6, 7 1.0 2.3 4.0 1.0 2.5 4.5 1.5 3.0 6.5 5.5 ns tPHZ/tPLZ 3-State output disable time OE to Yn 6, 7 1.0 2.3 3.5 1.0 2.2 4.0 1.5 3.5 6.5 5.5 ns CP pulse width HIGH or LOW 3, 7 1.0 – – 1.2 – – 2.0 – – – LE pulse width HIGH 2, 7 1.0 – – 1.2 – – 2.0 – – – Set-up time An to CP 5, 7 0.3 – – 0.4 – – 0.5 – – – Set-up time An to LE 4, 7 0.3 – – 0.4 – – 0.5 – – – Hold time An to CP 5, 7 0.3 – – 0.4 – – 0.5 – – Hold time An to LE 4, 7 0.3 – – 0.4 – – 0.5 – – Maximum clock pulse frequency 3, 7 500 – – 400 – – 250 – – tPHL/tPLH tW tSU S ns ns ns th ns Fmax MHz NOTES: 1. All typical values are measured at Tamb = 25°C and at VCC = 1.8 V, 2.5 V, 3.3 V. AC WAVEFORMS FOR VCC = 3.0V TO 3.6V RANGE VM = 0.5 VCC VX = VOL + 0.300 V VY = VOH – 0.300 V VOL and VOH are the typical output voltage drop that occur with the output load. VI = VCC VI LE INPUT GND NOTE: VM = 0.5VCC at VCC = 2.3 to 2.7V SH00134 Waveform 2. Latch enable input (LE) pulse width, the latch enable input to output (Yn) propagation delays. VM GND tPLH VOH VM VOL NOTE: VM = 0.5VCC at VCC = 2.3 to 2.7 V SH00132 Waveform 1. Input (An) to output (Yn) propagation delay 1999 Jul 23 VM VOL VI Yn OUTPUT tPLH VOH Yn OUTPUT VM = 0.5 VCC VX = VOL + 0.15 V VY = VOH – 0.15 V VOL and VOH are the typical output voltage drop that occur with the output load. VI = VCC tPHL VM tW tPHL AC WAVEFORMS FOR VCC = 2.3 V TO 2.7 V AND VCC < 2.3 V RANGE An INPUT VM 6 Philips Semiconductors Preliminary specification 18-bit Registered Driver (3-State) 74AVC16835 AC WAVEFORMS FOR VCC = 3.0 V TO 3.6 V RANGE (Continued) VM = 0.5 VCC VX = VOL + 0.300 V VY = VOH – 0.300 V VOL and VOH are the typical output voltage drop that occur with the output load. VI = VCC VI GND VI An INPUT GND VOH VM Yn OUTPUT VOL NOTE: The shaded areas indicate when the input is permitted to change for predictable output performance. VM = 0.5VCC at VCC = 2.3 to 2.7 V SH00136 1/fMAX VI Waveform 5. Data set-up and hold times for the An input to the clock CP input VM tW GND tPHL tPLH VI VOH VM Yn OUTPUT nOE INPUT VOL NOTE: VM = 0.5VCC at VCC = 2.3 to 2.7 V VM GND SH00135 Waveform 3. The clock (CP) to Yn propagation delays, the clock pulse width and the maximum clock frequency. tPLZ tPZL VCC ÉÉÉ ÉÉÉÉÉÉÉ ÉÉÉ ÉÉÉ ÉÉÉÉÉÉÉ ÉÉÉ ÉÉÉ ÉÉÉÉÉÉÉ ÉÉÉ OUTPUT LOW-to-OFF OFF-to-LOW VI An INPUT ÉÉÉÉ ÉÉÉÉÉÉÉ ÉÉÉ ÉÉÉÉ ÉÉÉÉÉÉÉ ÉÉÉ ÉÉÉÉÉÉÉÉÉÉÉ ÉÉÉ th th VM = 0.5 VCC VX = VOL + 0.15 V VY = VOH – 0.15 V VOL and VOH are the typical output voltage drop that occur with the output load. VI = VCC VM tsu tsu AC WAVEFORMS FOR VCC = 2.3 V TO 2.7 V AND VCC < 2.3V RANGE (Continued) CP INPUT VM CP INPUT VM VX VM VOL GND th tSU tPHZ th tSU VI LE INPUT tPZH VOH OUTPUT HIGH-to-OFF OFF-to-HIGH VM GND VY VM GND outputs enabled NOTE: The shaded areas indicate when the input is permitted to change for predictable output performance. VM = 0.5VCC at VCC = 2.3 to 2.7V NOTE: VM = 0.5VCC at VCC = 2.3 to 2.7 V SH00133 outputs enabled SH00137 Waveform 6. 3-State enable and disable times Waveform 4. Data set-up and hold times for the An input to the LE input 1999 Jul 23 outputs disabled 7 Philips Semiconductors Preliminary specification 18-bit Registered Driver (3-State) 74AVC16835 TEST CIRCUIT GRAPHS S1 RL VO VI PULSE GENERATOR 0 2 * VCC Open GND I OH (mA) OUTPUT CURRENT VCC D.U.T. RT RL CL Test Circuit for switching times –50 1.8V –100 –150 2.5V –200 –250 3.3V PMOS –300 –350 0 DEFINITIONS 0.5 1.0 1.5 2.0 2.5 3.0 3.5 VOH (V) OUTPUT VOLTAGE RL = Load resistor CL = Load capacitance includes jig and probe capacitance SH00161 RT = Termination resistance should be equal to ZOUT of pulse generators. SWITCH POSITION tPLH/tPHL tPLZ/tPZL tPHZ/tPZH S1 Open 2 VCC GND VCC VI RL < 2.3 V VCC 1000 Ω 2.3–2.7 V VCC 500 Ω 3.0 V VCC 500 Ω –350 I OH (mA) OUTPUT CURRENT TEST SV01018 Waveform 7. Load circuitry for switching times –300 –250 3.3V –200 –150 2.5V –100 1.8V –50 NMOS 0 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 VOH (V) OUTPUT VOLTAGE SH00162 1999 Jul 23 8 Philips Semiconductors Preliminary specification 8-bit Registered Driver (3-State) 74AVC16835 TSSOP56: plastic thin shrink small outline package; 56 leads; body width 6.1mm 1999 Jul 23 9 SOT364-1 Philips Semiconductors Preliminary specification 8-bit Registered Driver (3-State) 74AVC16835 Data sheet status Data sheet status Product status Definition [1] Objective specification Development This data sheet contains the design target or goal specifications for product development. Specification may change in any manner without notice. Preliminary specification Qualification This data sheet contains preliminary data, and supplementary data will be published at a later date. Philips Semiconductors reserves the right to make changes at any time without notice in order to improve design and supply the best possible product. Product specification Production This data sheet contains final specifications. Philips Semiconductors reserves the right to make changes at any time without notice in order to improve design and supply the best possible product. [1] Please consult the most recently issued datasheet before initiating or completing a design. Definitions Short-form specification — The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook. Limiting values definition — Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information — Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Disclaimers Life support — These products are not designed for use in life support appliances, devices or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application. Right to make changes — Philips Semiconductors reserves the right to make changes, without notice, in the products, including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified. Copyright Philips Electronics North America Corporation 1998 All rights reserved. Printed in U.S.A. Philips Semiconductors 811 East Arques Avenue P.O. Box 3409 Sunnyvale, California 94088–3409 Telephone 800-234-7381 print code Document order number: 1999 Jul 23 10 Date of release: 07-99 9397-750-06251