INTEGRATED CIRCUITS 74LVC2373A 74LVCH2373A Octal D-type transparent latch with 5-volt tolerant inputs/outputs; damping resistor (3-State) Product specification IC24 Data Handbook 1997 Mar 12 Philips Semiconductors Product specification Octal D-type transparent latch with 5-volt tolerant inputs/outputs; damping resistor (3-State) FEATURES 74LVC2373A 74LVCH2373A DESCRIPTION • 5-volt tolerant inputs/outputs, for interfacing with 5-volt logic • Supply voltage range of 2.7V to 3.6V • Complies with JEDEC standard no. 8-1A • CMOS low power consumption • Direct interface with TTL levels • High impedance when VCC = 0V • Bushold on all data inputs (74LVCH2373A only) • Integrated 30 damping resistor The 74LVC2373A/74LVCH2373A is a high performance, low-power, low-voltage Si-gate CMOS device and superior to most advanced CMOS compatible TTL families. Inputs can be driven from either 3.3V or 5V devices. This feature allows the use of these devices as translators in a mixed 3.3V/5V environment. The 74LVC2373A/74LVCH2373A is an octal D-type transparent latch featuring separate D-type inputs for each latch and 3-State outputs for bus oriented applications. A latch enable (LE) input and an output enable (OE) input are common to all internal latches. The ‘2373’ consists of eight D-type transparent latches with 3-State true outputs. When LE is HIGH, data at the Dn inputs enters the latches. In this condition the latches are transparent, i.e., a latch output will change each time its corresponding D-input changes. When LE is LOW the latches store the information that was present at the D-inputs a set-up time preceding the HIGH-to-LOW transition of LE. When OE is LOW, the contents of the eight latches are available at the outputs. When OE is HIGH, the outputs go to the high impedance OFF-state. Operation of the OE input does not affect the state of the latches. QUICK REFERENCE DATA GND = 0V; Tamb = 25°C; tr = tf 2.5 ns PARAMETER SYMBOL CONDITIONS tPHL/tPLH Propagation delay Dn to Qn LE to Qn CI Input capacitance CPD Power dissipation capacitance per latch TYPICAL UNIT 4.4 5.0 ns 5.0 pF 20 pF CL = 50pF VCC = 3.3V Notes 1, 2 NOTES: 1. CPD is used to determine the dynamic power dissipation (PD in µW) PD = CPD × VCC2 × fi Σ (CL × VCC2 × fo) where: fi = input frequency in MHz; CL = output load capacity in pF; fo = output frequency in MHz; VCC = supply voltage in V; Σ (CL × VCC2 × fo) = sum of the outputs. 2. The condition is VI = GND to VCC. ORDERING AND PACKAGE INFORMATION TEMPERATURE RANGE OUTSIDE NORTH AMERICA NORTH AMERICA PKG. DWG. # 20-Pin Plastic SO –40°C to +85°C 74LVC2373A D 74LVC2373A D SOT163-1 20-Pin Plastic SSOP Type II –40°C to +85°C 74LVC2373A DB 74LVC2373A DB SOT339-1 20-Pin Plastic TSSOP Type I –40°C to +85°C 74LVC2373A PW LVC2373APW DH SOT360-1 20-Pin Plastic SO –40°C to +85°C 74LVCH2373A D 74LVCH2373A D SOT163-1 20-Pin Plastic SSOP Type II –40°C to +85°C 74LVCH2373A DB 7LVCH2373A DB SOT339-1 20-Pin Plastic TSSOP Type I –40°C to +85°C 74LVCH2373A PW VCH2373APW DH SOT360-1 PACKAGES 1997 Mar 12 2 853–1940 17843 Philips Semiconductors Product specification 74LVC2373A 74LVCH2373A Octal D-type transparent latch with 5-volt tolerant inputs/outputs; damping resistor (3-State) PIN CONFIGURATION LOGIC SYMBOL 11 OE 1 20 VCC Q0 2 19 Q7 D0 3 18 D7 D1 4 17 D6 Q1 5 16 Q2 6 D2 D3 Q3 LE 3 D0 Q0 2 4 D1 Q1 5 7 D2 Q2 6 Q6 8 D3 Q3 9 15 Q5 13 D4 Q4 12 7 14 D5 14 D5 Q5 15 8 13 D4 17 D6 Q6 16 Q4 18 D7 Q7 19 9 12 OE GND 10 11 LE 1 SV00657 PIN DESCRIPTION FUNCTIONAL DIAGRAM PIN NUMBER SYMBOL 1 OE 2, 5, 6, 9, 12, 15, 16, 19 Q0–Q7 3, 4, 7, 8, 13, 14, 17, 18 D0–D7 10 GND 11 LE 20 VCC FUNCTION Output enable input (active LOW) 1 3 D0 Q0 2 4 D1 Q1 5 7 D2 Q2 6 8 D3 Q3 9 Q4 12 3-State latch outputs Data inputs LATCH 1 to 8 3–STATE OUTPUTS Ground (0V) 13 Latch enable input (active HIGH) 14 D5 Q5 15 Positive supply voltage 17 D6 Q6 16 Q7 19 LOGIC SYMBOL (IEEE/IEC) 11 SV00658 D4 18 D7 11 LE 1 OE C1 EN1 SV00660 3 1D 2 4 5 7 6 8 9 13 12 14 15 17 16 18 19 FUNCTION TABLE LE Dn INTERNAL LATCHES OUTPUTS OE Enable and read register (transparent mode) L L H H L H L H L H Latch and read register L L L L I h L H L H Latch register and disable outputs H H L L I h L H Z Z OPERATING MODES SV00659 INPUTS Q0 to Q7 H = HIGH voltage level h = HIGH voltage level one set-up time prior to the HIGH-to-LOW LE transition L = LOW voltage level I = LOW voltage level one set-up time prior to the HIGH-to-LOW LE transition X = Don’t care Z = High impedance OFF-state 1997 Mar 12 3 Philips Semiconductors Product specification 74LVC2373A 74LVCH2373A Octal D-type transparent latch with 5-volt tolerant inputs/outputs; damping resistor (3-State) LOGIC DIAGRAM D0 D1 D2 D3 D4 D5 D6 D7 Q D LATCH 1 Q D LATCH 2 Q D LATCH 3 Q D LATCH 4 Q D LATCH 5 Q D LATCH 6 Q D LATCH 7 Q D LATCH 8 LE LE LE LE LE LE LE LE LE LE LE LE LE LE LE LE LE OE Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 SV00661 RECOMMENDED OPERATING CONDITIONS SYMBOL PARAMETER CONDITIONS LIMITS MIN MAX UNIT VCC DC supply voltage (for max. speed performance) 2.7 3.6 V VCC DC supply voltage (for low-voltage applications) 1.2 3.6 V DC input voltage range 0 5.5 V VI/O DC input voltage range for I/Os 0 VCC V VO DC output voltage range 0 VCC V –40 +85 °C 0 0 20 10 ns/V VI Tamb Operating free-air temperature range tr, tf Input rise and fall times VCC = 1.2 to 2.7V VCC = 2.7 to 3.6V ABSOLUTE MAXIMUM RATINGS1 In accordance with the Absolute Maximum Rating System (IEC 134). Voltages are referenced to GND (ground = 0V). PARAMETER SYMBOL VCC CONDITIONS DC supply voltage RATING UNIT –0.5 to +6.5 V IIK DC input diode current VI t0 –50 mA VI DC input voltage Note 2 –0.5 to +5.5 V VI/O DC input voltage range for I/Os IOK DC output diode current VO uVCC or VO t 0 VOUT DC output voltage; output HIGH or LOW VOUT IOUT IGND, ICC Tstg PTOT –0.5 to VCC +0.5 V ±50 mA Note 2 –0.5 to VCC +0.5 V DC output voltage; output 3-State Note 2 –0.5 to +6.5 V DC output source or sink current VO = 0 to VCC ±50 mA DC VCC or GND current Storage temperature range Power dissipation per package – plastic mini-pack (SO) – plastic shrink mini-pack (SSOP and TSSOP) above +70°C derate linearly with 8 mW/K above +60°C derate linearly with 5.5 mW/K ±100 mA –60 to +150 °C 500 500 mW NOTES: 1. Stresses beyond those listed may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. 2. The input and output voltage ratings may be exceeded if the input and output current ratings are observed. 1997 Mar 12 4 Philips Semiconductors Product specification 74LVC2373A 74LVCH2373A Octal D-type transparent latch with 5-volt tolerant inputs/outputs; damping resistor (3-State) DC ELECTRICAL CHARACTERISTICS Over recommended operating conditions. Voltages are referenced to GND (ground = 0V). LIMITS SYMBOL PARAMETER TEST CONDITIONS Temp = -40°C to +85°C MIN VIH HIGH level Input voltage VIL LOW level Input voltage VOH VOH VCC = 1.2V VCC VCC = 2.7 to 3.6V 2.0 GND VCC = 2.7 to 3.6V HIGH level output voltage VCC0.2 VCC = 3.0V; VI = VIH or VIL; IO = –12mA VCC0.6 VCC = 3.0V; VI = VIH or VIL; IO = –24mA VCC1.0 VCC = 2.7V; VI = VIH or VIL; IO = –6mA7 VCC0.5 VCC = 3.0V; VI = VIH or VIL; IO = HIGH level output voltage 0.8 VCC = 3.0V; VI = VIH or VIL; IO = –100µA –100µA7 VCC0.2 VCC V VCC GND VCC = 3.0V; VI = VIH or VIL; IO = 24mA VCC = 3.0V; VI = VIH or VIL; IO = 12mA7 Input leakage current VCC = 3.6V; VI = 5.5V or GND Not for I/O pins IIHZ/IILZ Input current for common I/O pins IOZ 3-State output OFF-state current ICC 0.20 V 0.40 VCC = 3.0V; VI = VIH or VIL; IO = 100µA7 LOW level output voltage V 0.55 VCC = 2.7V; VI = VIH or VIL; IO = 6mA7 VOL V VCC0.8 VCC = 3.0V; VI = VIH or VIL; IO = 100µA LOW level output voltage UNIT MAX V VCC = 1.2V VCC = 3.0V; VI = VIH or VIL; IO = –12mA7 VOL O TYP1 GND 0.20 V 0.55 ±0.1 ±5 µA VCC = 3.6V; VI = VCC or GND ±0.1 ±15 µA VCC = 3.6V; VI = VIH or VIL; VO = VCC or GND 0.1 ±10 µA Quiescent supply current VCC = 3.6V; VI = VCC or GND; IO = 0 0.1 20 µA ∆ICC Additional quiescent supply current per input pin VCC = 2.7V to 3.6V; VI = VCC –0.6V; IO = 0 5 500 µA IBHL Bushold LOW sustaining current2, 3, 4 VCC = 3.0V; VI =0.8V 75 – – µA current2, 3, 4 II IBHH Bushold HIGH sustaining VCC = 3.0V; VI =2.0V –75 – – µA IBHLO Bushold LOW overdrive current2, 3, 5 VCC = 3.6V 500 – – µA IBHHO Bushold HIGH overdrive current2, 3, 5 VCC = 3.6V –500 – – µA NOTES: 1. All typical values are at VCC = 3.3V and Tamb = 25°C. 2. Valid for data inputs of bushold parts (LVCH-A) only. 3. For data inputs only, control inputs do not have a bushold circuit. 4. The specified sustaining current at the data inputs do not have a bushold circuit. 5. The specified overdrive current at the data input forces the data input to the opposite logic input state. 6. For bushold parts, the bushold circuit is switched off when VI exceeds VCC allowing 5.5V on the input terminal. 7. For data outputs of damping resistor parts only. 1997 Mar 12 5 Philips Semiconductors Product specification 74LVC2373A 74LVCH2373A Octal D-type transparent latch with 5-volt tolerant inputs/outputs; damping resistor (3-State) AC CHARACTERISTICS GND = 0 V; tr = tf v 2.5 ns; CL = 50 pF LIMITS SYMBOL PARAMETER VCC = 3.3V ±0.3V WAVEFORM VCC = 2.7V VCC = 1.2V MIN TYP1 MAX MIN MAX TYP UNIT tPHL/tPLH Propagation delay Dn to Qn Figures 1, 5 1.5 – 8.5 1.5 9.5 – ns tPHL/tPLH Propagation delay LE to Qn Figures 2, 5 1.5 – 9.5 1.5 11 – ns tPZH/tPZL 3-State output enable time OE to Qn Figures 3, 5 1.5 – 9.0 1.5 11 – ns tPHZ/tPLZ 3-State output disble time OE to Qn Figures 3, 5 1.5 – 6.0 1.5 6.5 – ns tW LE pulse width HIGH Figure 2 4.0 – – 4.0 – – ns tsu Set-up time Dn to LE Figure 4 2.0 – – 3.0 – – ns th Hold time Dn to LE Figure 4 2.0 – – 3.0 – – ns NOTE: 1. These typical values are at VCC = 3.3V and Tamb = 25°C. AC WAVEFORMS VM = 1.5 V at VCC w 2.7 V VM = 0.5 VCC at VCC < 2.7 V VOL and VOH are the typical output voltage drop that occur with the output load. VX = VOL + 0.3 V at VCC ≥ 2.7 V VX – VOL + 0.1 ⋅ VCC at VCC < 2.7 V VY = VOH – 0.3 V at VCC ≥ 2.7 V VY = VOH – 0.1 ⋅ VCC at VCC < 2.7 V VI VI INPUTS LE INPUT VM GND tW tPHL tPLH VOH Qn OUTPUT VM VM VOL VOL SV00690 SV00691 Figure 1. nput (Dn) to output (Qn) propagation delays 1997 Mar 12 tPLH tPHL VOH OUTPUTS VM GND Figure 2. Latch enable input (LE) pulse width, the latch enable input to output (Qn) propagation delays 6 Philips Semiconductors Product specification 74LVC2373A 74LVCH2373A Octal D-type transparent latch with 5-volt tolerant inputs/outputs; damping resistor (3-State) TEST CIRCUIT VI OE INPUT VM S1 VCC GND tPLZ tPZL PULSE GENERATOR VCC OUTPUT LOW–to–OFF OFF–to–LOW VOL VI 500Ω VO D.U.T. VM RT VX 50pF CL 500Ω tPZH tPHZ Test VOH OUTPUT HIGH–to–OFF OFF–to–HIGH GND VY VM outputs disabled outputs enabled S1 VCC VI tPLH/tPHL Open t 2.7V VCC tPLZ/tPZL 2 < VCC 2.7V – 3.6V 2.7V tPHZ/tPZH GND outputs enabled SY00003 Figure 5. Load circuitry for switching times SV00692 Figure 3. 3-State enable and disable times ÉÉÉÉÉÉÉÉÉÉÉÉ ÉÉÉÉÉÉÉÉÉÉÉÉ ÉÉÉÉÉÉÉÉÉÉÉÉ VI Dn INPUT VM GND th tsu th tsu VI LE INPUT VM GND NOTE: The shaded areas indicate when the input is permitted to change for predictable output performance. SV00693 Figure 4. Data set-up and hold times for the Dn input to the LE input 1997 Mar 12 2 < VCC Open GND 7 Philips Semiconductors Product specification Octal D-type transparent latch with 5-volt tolerant inputs/outputs; damping resistor (3-State) SO20: plastic small outline package; 20 leads; body width 7.5 mm 1997 Mar 12 8 74LVC2373A 74LVCH2373A SOT163-1 Philips Semiconductors Product specification Octal D-type transparent latch with 5-volt tolerant inputs/outputs; damping resistor (3-State) SSOP20: plastic shrink small outline package; 20 leads; body width 5.3 mm 1997 Mar 12 9 74LVC2373A 74LVCH2373A SOT339-1 Philips Semiconductors Product specification Octal D-type transparent latch with 5-volt tolerant inputs/outputs; damping resistor (3-State) TSSOP20: plastic thin shrink small outline package; 20 leads; body width 4.4 mm 1997 Mar 12 10 74LVC2373A 74LVCH2373A SOT360-1 Philips Semiconductors Product specification Octal D-type transparent latch with 5-volt tolerant inputs/outputs; damping resistor (3-State) NOTES 1997 Mar 12 11 74LVC2373A 74LVCH2373A Philips Semiconductors Product specification 74LVC2373A 74LVCH2373A Octal D-type transparent latch with 5-volt tolerant inputs/outputs; damping resistor (3-State) DEFINITIONS Data Sheet Identification Product Status Definition Objective Specification Formative or in Design This data sheet contains the design target or goal specifications for product development. Specifications may change in any manner without notice. Preliminary Specification Preproduction Product This data sheet contains preliminary data, and supplementary data will be published at a later date. Philips Semiconductors reserves the right to make changes at any time without notice in order to improve design and supply the best possible product. Product Specification Full Production This data sheet contains Final Specifications. Philips Semiconductors reserves the right to make changes at any time without notice, in order to improve design and supply the best possible product. Philips Semiconductors and Philips Electronics North America Corporation reserve the right to make changes, without notice, in the products, including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified. Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. LIFE SUPPORT APPLICATIONS Philips Semiconductors and Philips Electronics North America Corporation Products are not designed for use in life support appliances, devices, or systems where malfunction of a Philips Semiconductors and Philips Electronics North America Corporation Product can reasonably be expected to result in a personal injury. Philips Semiconductors and Philips Electronics North America Corporation customers using or selling Philips Semiconductors and Philips Electronics North America Corporation Products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors and Philips Electronics North America Corporation for any damages resulting from such improper use or sale. Copyright Philips Electronics North America Corporation 1997 All rights reserved. Printed in U.S.A. Philips Semiconductors 811 East Arques Avenue P.O. Box 3409 Sunnyvale, California 94088–3409 Telephone 800-234-7381 1997 Mar 12 12