PHILIPS PCF8558U/12

INTEGRATED CIRCUITS
DATA SHEET
PCF8558
Universal LCD driver for small
graphic panels
Objective specification
Supersedes data of 1997 Feb 27
File under Integrated Circuits, IC12
1998 Apr 07
Philips Semiconductors
Objective specification
Universal LCD driver for small graphic
panels
PCF8558
FEATURES
• Single-chip LCD controller/driver
• 40 row and 101 column outputs
• Display data RAM
40 × 101 bits = 505 bytes = 4040 bits
• On-chip:
GENERAL DESCRIPTION
– Generation of intermediate LCD bias voltages
The PCF8558 is a low power CMOS LCD controller driver,
designed to drive a graphic display of 40 rows and
101 columns. All necessary functions for the display are
provided in a single chip, including on-chip generation of
LCD bias voltages, resulting in a minimum of external
components and lower power consumption.
– Oscillator requires no external components
(external clock also possible)
• 400 kHz fast I2C-bus interface
• CMOS compatible
• MUX rate 1 : 40
The PCF8558 interfaces to most microcontrollers via a
I2C-bus interface.
• Logic supply voltage range VDD − VSS = 2.5 to 6 V
• Display supply voltage range VDD − VLCD = 3.5 to 9 V
• Low power consumption, suitable for battery operated
systems.
APPLICATIONS
• Telecom equipment
• Portable instruments
• Point of sale terminals
• Alarm systems.
ORDERING INFORMATION
PACKAGE(1)
TYPE
NUMBER
NAME
PCF8558U/10
−
chip on FFC
−
PCF8558U/12
−
chip with bumps on FFC
−
DESCRIPTION
Note
1. For further details see Chapter “Bonding pad locations”.
1998 Apr 07
2
VERSION
Philips Semiconductors
Objective specification
Universal LCD driver for small graphic
panels
PCF8558
BLOCK DIAGRAM
C1 to C101
R1 to R40
COLUMN DRIVERS
ROW DRIVERS
DATA LATCHES
SHIFT REGISTER
handbook, full pagewidth
BIAS
VOLTAGE
GENERATOR
VLCD
CURSOR AND
DATA CONTROL
OSCILLATOR
VDD
VSS
DISPLAY DATA RAM
505 BYTES
T1
T3
TIMING
GENERATOR
DISPLAY
ADDRESS
COUNTER
ADDRESS
COUNTER
T2
POWER-ON
RESET
DATA
REGISTER
PCF8558
I/O BUFFER
MGG558
SDA SCL
SA0
Fig.1 Block diagram.
1998 Apr 07
3
OSC
Philips Semiconductors
Objective specification
Universal LCD driver for small graphic
panels
PCF8558
PINNING
SYMBOL
SCL
PAD
1
R20 to R1
2 to 21
C101 to C1
22 to 122
R21 to R40
123 to 142
DESCRIPTION
I2C-bus
serial clock input
LCD row driver data outputs
LCD column driver data outputs
LCD row driver data outputs
T2
143
test pad output, must be left unconnected (not user accessible)
SDA
144
I2C-bus serial data input/output
VSS
145
ground
T1
146
test pad input, must be connected to VSS (not user accessible)
VLCD
147
negative supply voltage input
SA0
148
the LSB bit of the I2C-bus slave address input is set by connecting this pin to either
0 (VSS) or 1 (VDD)
T3
149
test pad input, must be connected to VDD (not user accessible)
OSC
150
when the on-chip oscillator is used this pin must be connected to VDD; an external clock
signal, if used, is input at this pin
VDD
151
positive supply voltage
1998 Apr 07
4
Philips Semiconductors
Objective specification
Universal LCD driver for small graphic
panels
PCF8558
Display Data RAM (DDRAM). Both registers can be written
to but not read from by the system controller.
FUNCTIONAL DESCRIPTION
LCD bias voltage generator
Address Counter (AC)
The intermediate bias voltages for the LCD display are
generated and buffered on-chip. This removes the need
for an external resistor bias chain and significantly reduces
the system power consumption.
The address counter assigns addresses to the DDRAM for
writing and is set by Y2 to Y0 in the command and
X6 to X0 in the address. After a write operation the
address counter is automatically incremented by 1 in
accordance with the V flag.
Oscillator
The on-chip oscillator provides the clock signal for the
display system. No external components are required and
the OSC pin must be connected to VDD.
Display Data RAM (DDRAM)
The PCF8558 contains a 40 × 101-bit static RAM which
stores the display data. The RAM is divided into 5 banks of
101 bytes (5 × 8 × 101 bits). During RAM access, data is
transferred to the RAM via the I2C-bus. There is a direct
correspondence between the X address and the column
output number.
External clock
If an external clock is to be used it is input at the OSC pin.
The resulting display frame frequency is given by
f OSC
f frame = ------------.
3072
Only in the power-down state is the clock allowed to be
stopped (OSC connected to VSS), otherwise the LCD will
be frozen in a state where a DC voltage is applied to it.
Timing generator
The timing generator produces the various signals
required to drive the internal circuitry. Internal chip
operation is not disturbed by operations on the data buses.
Power-on reset
Display control
The on-chip power-on reset block initializes the chip after
power-on or power failure. This is a synchronous reset and
requires 2 oscillator cycles to execute. These oscillator
cycles must be provided from the external clock source if
the internal oscillator is not used. If this is not done, the
device may not respond to command sequences
transmitted via the I2C-bus interface.
The display is generated by continuously shifting rows of
RAM data to the dot matrix LCD via the column outputs.
The display status (all dots on/off and normal/inverse
video) is set by bits E and D in the command word.
LCD row and column drivers
The PCF8558 contains 40 row and 101 column drivers,
which connect the appropriate LCD bias voltages in
sequence to the display in accordance with the data to be
displayed. Figure 3 illustrates typical waveforms. Unused
outputs should be left unconnected.
Power-down
The chip can be put into power-down mode where all static
currents are switched off (no internal oscillator, no internal
power-on reset, no bias level generation and all LCD
outputs are internally connected to VDD) when
PD = logic 1.
The bias voltage levels, V2 to V5, are chosen to give
optimum display contrast for a multiplex rate of 1 : 40.
During power-down the information in the RAMs and the
internal chip states are preserved. Instruction execution
during power-down is possible if an externally clock signal
is applied to pad OSC.
Table 1
Registers
The PCF8558 has one 8-bit register, time shared as a
Command Register (CR) and a Data Register (DR).
The command register stores the command code such as
display on or display off and address information for the
1998 Apr 07
5
Voltage bias levels
LEVEL
VOLTAGE
V2
0.8635 × (VDD − VLCD)
V3
0.7270 × (VDD − VLCD)
V4
0.2730 × (VDD − VLCD)
V5
0.1365 × (VDD − VLCD)
Philips Semiconductors
Objective specification
Universal LCD driver for small graphic
panels
PCF8558
RAM
bank 0
top of LCD
bank 1
bank 2
LCD
bank 3
bank 4
MGG559
Fig.2 DDRAM to display mapping.
1998 Apr 07
6
Philips Semiconductors
Objective specification
Universal LCD driver for small graphic
panels
frame n + 1
frame n
ROW 1
R1 (t)
VDD
V2
V3
V4
V5
VLCD
ROW 2
R2 (t)
VDD
V2
V3
V4
V5
VLCD
COL 1
C1 (t)
VDD
V2
V3
V4
V5
VLCD
COL 2
C2 (t)
VDD
V2
V3
V4
V5
VLCD
PCF8558
Vstate 1(t)
Vstate 2(t)
VOP
0.7269VOP
Vstate 1(t)
0.2731VOP
0V
0.2731VOP
0.7269VOP
VOP
VOP
0.7269VOP
Vstate 2(t)
0.2731VOP
0V
0.2731VOP
0.7269VOP
VOP
12 3 4 56 7 8 9
... 40 1 2 3 4 5 6 7 8 9
... 40
Vstate1(t) = C2(t) − R1(t); Vstate2(t) = C2(t) − R2(t).
Fig.3 Typical LCD driver waveforms (MUX rate 1 : 40).
1998 Apr 07
7
MGG560
Philips Semiconductors
Objective specification
Universal LCD driver for small graphic
panels
PCF8558
ADDRESSING
The data is downloaded into the matrix of the PCF8558 as indicated in Figs 4 and 5.
The display RAM has a matrix of 40 by 101 bits (5 by 101 bytes). The columns are addressed by the address pointer.
After writing one byte the pointer is set to the next byte. Control of address increment, horizontal or vertical, is by bit V in
the command byte.
handbook,LSB
full pagewidth
MSB
display line 0 to 7
000
display line 8 to 15
001
display line 16 to 23
010
display line 24 to 31
011
display line 32 to 39
100
X
address 2
address 1
address 0
address 98
address 99
address 100
MGG561
Fig.4 RAM format, addressing.
DATA STRUCTURE
handbook, full pagewidth 0 5
0
1
2
...
16
101 102 103 . . .
27
202 203 204 . . .
38
303 304 305 . . .
49
404 405 406 . . .
MGG562
a.
b.
Order of writing data bytes into RAM (V = 1).
Order of writing data bytes into RAM (V = 0).
Fig.5 Order of writing data bytes into RAM.
1998 Apr 07
8
Y address
Philips Semiconductors
Objective specification
Universal LCD driver for small graphic
panels
PCF8558
automatically incremented, enabling a stream of data to be
transferred to the DDRAM.
I2C-BUS PROTOCOL
Two 7-bit slave addresses (0111100 and 0111101) are
reserved for both the PCF8558. The least-significant bit of
the slave address is set by connecting input SA0 to
either 0 (VSS) or 1 (VDD). Therefore, two PCF8558 can be
used on the same I2C-bus allowing displays of up to
80 × 101 or 40 × 202 dots to be driven.
The instruction format is composed of I2C-bus slave
address followed by one command byte, one X address
pointer, followed by any number of data bytes.
Command execution/storing of data takes place during the
acknowledge cycle.
The I2C-bus protocol is shown in Fig.6.
All communications are initiated with a START condition
(S) from the I2C-bus master, which is followed by the
desired slave address and write bit. All devices with this
slave address acknowledge in parallel. All other devices
ignore the bus transfer.
Definitions
• Transmitter: the device which sends the data to the bus
• Receiver: the device which receives the data from the
bus
• Master: the device which initiates a transfer, generates
clock signals and terminates a transfer
In write mode (indicated by setting the read/write bit LOW)
one or more commands follow the slave address
acknowledgement. The commands are also
acknowledged by all addressed devices on the bus.
The last command must clear the continuation bit C. After
the last command a series of data bytes may follow.
The acknowledgement after each byte is made only by the
addressed device. After the last data byte has been
acknowledged, the I2C-bus master issues a STOP
condition (P).
• Slave: the device addressed by a master
• Multi-master: more than one master can attempt to
control the bus at the same time. The I2C-bus can
accommodate this without data los/contention.
• Arbitration: procedure to ensure that, if more than one
master simultaneously tries to control the bus, only one
is allowed to do so and the message is not corrupted
• Synchronization: procedure to synchronize the clock
signals of two or more devices.
For PCF8558, no read mode is provided.
Display bytes are written into the RAM at the address
specified by the data pointer and subaddress counter.
Both the data pointer and subaddress counter are
R/W
handbook, full pagewidth
S
S 0 1 1 1 1 0 A
O
A
C
K
COMMAND
A
C
K
X ADDRESS
slave address
A
C
K
DISPLAY DATA
A
C P
K
N ≥ 0 bytes
MGG563
Fig.6 I2C-bus protocol.
1998 Apr 07
9
Philips Semiconductors
Objective specification
Universal LCD driver for small graphic
panels
PCF8558
COMMANDS
Set X address
Display Control
The X address points to the columns. The range of X is
0 to 100 (64H).
BIT
LOGIC 0
LOGIC 1
PD
normal
power-down
Reset function
V
horizontal addressing
vertical addressing
After power-on the chip has the following state:
Table 2
• Power-down mode (PD = 1)
Display status
• RAM undefined
BITS
• RAM X and Y address undefined
DISPLAY STATUS
E
D
• Display control bits (except PD) undefined
Blank
0
0
• I2C-bus interface reset.
Normal
1
1
Note
All segments on
1
0
Inverse video
0
1
If the chip is used with an external clock source, after
power-on, the chip requires at least 2 clock pulses to
ensure that an internal synchronous reset is carried out.
After the internal reset, the chip goes into power-down
mode (PD = 1). If the clock pulses are not supplied, and
the reset is not cleared, the chip cannot respond to
commands in the I2C bus.
PD: POWER-DOWN
• All LCD outputs at VDD (display off)
• Bias generator off
• Power-on reset on, oscillator off (external clock still
possible)
In applications where the internal oscillator is used
(pin OSC = VDD), the oscillator starts after power-on.
As soon as the synchronous reset is cleared, the chip goes
into power-down mode, and the oscillator is stopped.
• VLCD can be disconnected
• I2C-bus, RAM, commands, etc. still function in
power-down mode.
Set Address
Table 3
Y0, Y1 and Y2 define the Y address vector
address of the display RAM
Y2
Y1
Y0
LINE
0
0
0
0
0
0
1
1
0
1
0
2
0
1
1
3
1
0
0
4
Table 4
Instructions: control byte, address
INSTRUCTION
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
Display control
0
E
D
PD
V
Y2
Y1
Y0
X address
0
1998 Apr 07
X address
10
DESCRIPTION
Y address vector, display control
set column address
Philips Semiconductors
Objective specification
Universal LCD driver for small graphic
panels
PCF8558
CHARACTERISTICS OF THE I2C-BUS
Acknowledge
The I2C-bus is for bidirectional, two-line communication
between different ICs or modules. The two lines are a
serial data line (SDA) and a serial clock line (SCL) which
must be connected to a positive supply via a pull-up
resistor. Data transfer may be initiated only when the bus
is not busy.
The number of data bytes transferred between the START
and STOP conditions from transmitter to receiver is
unlimited. Each data byte of eight bits is followed by one
acknowledge bit. The acknowledge bit is a HIGH level put
on the bus by the transmitter, whereas the master
generates an extra acknowledge related clock pulse.
A slave receiver which is addressed must generate an
acknowledge after the reception of each byte. Also a
master must generate an acknowledge after the reception
of each byte that has been clocked out of the slave
transmitter. The device that acknowledges must pull down
the SDA line during the acknowledge clock pulse, so that
the SDA line is stable LOW during the HIGH period of the
acknowledge related clock pulse (set-up and hold times
must be taken into consideration). A master receiver must
signal the end of a data transmission to the transmitter by
not generating an acknowledge on the last byte that has
been clocked out of the slave. In this event the transmitter
must leave the data line HIGH to enable the master to
generate a stop condition.
Bit transfer
One data bit is transferred during each clock pulse.
The data on the SDA line must remain stable during the
HIGH period of the clock pulse as changes in the data line
at this moment will be interpreted as control signals.
START and STOP conditions
Both data and clock lines remain HIGH when the bus is not
busy. A HIGH-to-LOW transition of the data line, while the
clock is HIGH, is defined as the START condition (S).
A LOW-to-HIGH transition of the data line while the clock
is HIGH, is defined as the STOP condition (P).
System configuration
A device transmitting a message is a 'transmitter', a device
receiving a message is the 'receiver'. The device that
controls the message flow is the 'master' and the devices
which are controlled by the master are the 'slaves'.
handbook, full pagewidth
SDA
SCL
data line
stable;
data valid
change
of data
allowed
Fig.7 Bit transfer.
1998 Apr 07
11
MBC621
Philips Semiconductors
Objective specification
Universal LCD driver for small graphic
panels
PCF8558
handbook, full pagewidth
SDA
SDA
SCL
SCL
S
P
START condition
STOP condition
MBC622
Fig.8 Definition of START and STOP condition.
MASTER
TRANSMITTER/
RECEIVER
SLAVE
RECEIVER
SLAVE
TRANSMITTER/
RECEIVER
MASTER
TRANSMITTER
MASTER
TRANSMITTER/
RECEIVER
SDA
SCL
MGA807
Fig.9 System configuration.
1998 Apr 07
12
Philips Semiconductors
Objective specification
Universal LCD driver for small graphic
panels
PCF8558
handbook, full pagewidth
DATA OUTPUT
BY TRANSMITTER
not acknowledge
DATA OUTPUT
BY RECEIVER
acknowledge
SCL FROM
MASTER
1
2
8
9
S
clock pulse for
acknowledgement
START
condition
MBC602
The general characteristics and detailed specification of the I2C-bus are available on request (order number 9398 393 40011).
Fig.10 Acknowledgment on the I2C-bus.
LIMITING VALUES
In accordance with the Absolute Maximum Rating System (IEC 134).
SYMBOL
PARAMETER
MIN.
MAX.
UNIT
VDD
supply voltage
−0.5
+8.0
V
VLCD
LCD supply voltage
VDD − 11
VDD
V
Vi1
input voltage T1, T3, SA0 and OSC
VSS − 0.5
VDD + 0.5
V
Vi2
input voltage SDA and SCL
VSS − 0.5
8.0
V
Vo1
output voltage T2 and SDA
VSS − 0.5
VDD + 0.5
V
Vo2
output voltage R1 to R40 and C1 to C101
VLCD − 0.5 VDD + 0.5
V
II
DC input current
−10
+10
mA
IO
DC output current
−10
+10
mA
IDD, ISS, ILCD
VDD, VSS or VLCD current
−50
+50
mA
Ptot
power dissipation per package
−
400
mW
Po
power dissipation per output
−
100
mW
Tstg
storage temperature
−65
+150
°C
HANDLING
Inputs and outputs are protected against electrostatic discharge in normal handling. However, to be totally safe it is
desirable to take normal precautions appropriate to handling MOS devices.
1998 Apr 07
13
Philips Semiconductors
Objective specification
Universal LCD driver for small graphic
panels
PCF8558
DC CHARACTERISTICS
VDD = 2.5 to 6 V; VSS = 0 V; VLCD = VDD − 3.5 V to VDD − 9 V; Tamb = −40 to +85 °C; unless otherwise specified, note 1.
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
Supplies
VDD
supply voltage
2.5
−
6.0
VLCD
LCD supply voltage
VDD − 9
−
VDD − 3.5 V
IDD(PD)
supply current in power-down mode
−
5
10
µA
IDD1
supply current external clock
−
120
180
µA
IDD2
supply current internal clock
−
130
200
µA
ILCD
LCD input current
−
50
100
µA
VPOR
power-on reset level
0.6
1.3
1.8
V
note 2
V
Logic
VIL1
LOW level input voltage (all inputs
except OSC)
VSS
−
0.3VDD
V
VIH1
HIGH level input voltage (all inputs
except OSC)
0.7VDD
−
VDD
V
VIL2
LOW level input voltage (pin OSC)
VSS
−
VDD − 1.5 V
VIH2
HIGH level input voltage (pin OSC)
VDD − 0.1 −
VDD
V
IL1
leakage current at T1, T3 OSC and SA0
VI = VDD or VSS
−1
−
+1
mA
CI1
input capacitance at T1, T3 OSC and
SA0
note 3
−
−
5
pF
−
±20
−
mV
LCD outputs
VDC
DC component of LCD drivers R1 to R40
and C1 to C101
RROW
output resistance R1 to R40
note 4
−
1.5
6
kΩ
RCOL
output resistance C1 to C101
note 4
−
3
10
kΩ
I2C-bus;
SDA and SCL
VIL3
LOW level input voltage
note 5
VSS
−
0.3VDD
V
VIH3
HIGH level input voltage
note 5
0.7VDD
−
6
V
IL2
leakage current
VI = VDD or VSS
−1
−
+1
mA
CI2
input capacitance
note 3
−
−
7
pF
IOL
LOW level output current at SDA
VOL = 0.4 V;
VDD = 5 V
3.0
−
−
mA
Notes
1. Outputs are open-circuit; inputs at VDD or VSS; I2C-bus inactive; external clock with 50% duty factor.
2. Resets all logic when VDD < VPOR.
3. Periodically sampled, not 100% tested.
4. Resistance of output terminals (R1 to R40 and C1 to C101) with IL = 20 µA; VOP = VDD − VLCD = 9 V; outputs
measured one at a time.
5. When the voltages are above or below the supply voltages VDD or VSS, an input current may flow. This current must
not exceed ±0.5 mA.
1998 Apr 07
14
Philips Semiconductors
Objective specification
Universal LCD driver for small graphic
panels
PCF8558
AC CHARACTERISTICS
All timing values are referenced to VIH and VIL levels with an input voltage swing of VSS to VDD. VDD = 2.5 to 6 V;
VSS = 0 V; VLCD = VDD − 3.5 V to VDD − 9 V; Tamb = −40 to +85 °C; unless otherwise specified.
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
fFR)
LCD frame frequency
(internal oscillator)
37
62.5
94
Hz
fOSC(ext)
external clock frequency
90
150
225
kHz
tPLCD
driver delays
−
−
100
µs
VDD − VLCD = 9 V;
with test loads
I2C-bus (see Fig.12)
fSCL
SCL clock frequency
−
−
400
kHz
tCLKL
SCL LOW time
1.3
−
−
µs
tCLKH
SCL HIGH time
0.6
−
−
µs
tBUF
bus free time
between successive STOP
and START conditions
1.3
−
−
µs
tr
SCL and SDA rise time
note 1
−
−
300
ns
tf
SCL and SDA fall time
note 1
20 + 0.1Cb
−
300
ns
tSU;STA
START condition set-up time
repeated start codes only
0.6
−
−
µs
tHD;STA
START condition hold time
0.6
−
−
µs
tSU;DAT
data set-up time
100
−
−
ns
tHD;DAT
data hold time
0
−
−
ns
tSU;STO
STOP condition set-up time
0.6
−
−
µs
tSW
tolerable spike width on bus
−
−
50
ns
Cb
capacitive load per bus line
−
−
400
pF
note 2
Notes
1. The rise and fall times specified here refer to the driver device (i.e. not PCF8558) and are part of the general fast
I2C-bus specification. However, when PCF8558 asserts an acknowledge on SDA, the fall time is given by parameter
tf. Cb = capacitive load per bus line.
2. The device inputs SDA and SCL are filtered and will reject spikes on the bus lines of width <tSW(max).
handbook, full pagewidth
R1 to R40,
C1 to C101
1 nF
1.5 kΩ
SDA
VDD
MGG564
Fig.11 AC test loads.
1998 Apr 07
15
Philips Semiconductors
Objective specification
Universal LCD driver for small graphic
panels
PCF8558
ndbook, full pagewidth
SDA
t BUF
tf
t LOW
SCL
t HD;STA
t HD;DAT
tr
t HIGH
t SU;DAT
SDA
MGA728
t SU;STA
Fig.12 I2C-bus timing waveforms.
1998 Apr 07
16
t SU;STO
Philips Semiconductors
Objective specification
Universal LCD driver for small graphic
panels
PCF8558
APPLICATION INFORMATION
The pinning of the PCF8558 is optimized for single plane wiring e.g. for Chip-on-glass display modules.
handbook, full pagewidth
VDD
VDD VDD
SA0
OSC
R1 to R40
VDD
VDD
100
nF
40
PCF8558
C1 to C101
VLCD
VLCD
100 nF
VSS
40 × 101 dots
full graphic display
101
VSS SCL SDA
VSS
SA0
OSC
R1 to R40
VDD
VDD
100
nF
40
PCF8558
C1 to C101
VLCD
VLCD
100 nF
VSS
101
VSS SCL SDA
SCL SDA
MASTER TRANSMITTER
PCF84C81A; P80CL410
MGG565
Fig.13 Application using I2C-bus interface.
1998 Apr 07
17
40 × 101 dots
full graphic display
Philips Semiconductors
Objective specification
Universal LCD driver for small graphic
panels
handbook, halfpage
handbook, halfpage
DISPLAY 40 × 101
20
PCF8558
101
4 mm
20
9 mm
PCF8558
Y
X
PCF8558
pitch
8
supply, I/O
MGG567
MGG566
Fig.14 Application, display size 40 × 101 pixels.
Fig.15 Bonding pads.
CHIP INFORMATION
The PCF8558 is manufactured in p-well CMOS
technology. VDD − VLCD is positive. The chip substrate is
connected to VDD.
Bonding pads
Pad pitch
Pad size, aluminium
Bump dimensions
Wafer thickness
1998 Apr 07
100
µm
80 × 120
µm
59 × 99 × 15
µm
381
µm
18
Philips Semiconductors
Objective specification
Universal LCD driver for small graphic
panels
PCF8558
C17
C1
handbook, full pagewidth
R21
R32
BONDING PAD LOCATIONS
R33
C18
R40
dummy 1
~8.95
mm
y
0
0
dummy 6
x
PCF8558
T2
VSS
VLCD
SDA
T1
SA0
T3
OSC
VDD
C96
R1
C101
R7
R8
R20
SCL
Y
X
C95
~3.99 mm
MGG568
Fig.16 Bonding pad locations.
1998 Apr 07
19
Philips Semiconductors
Objective specification
Universal LCD driver for small graphic
panels
Table 5
PCF8558
Bonding pad locations (dimensions in µm).
All x/y coordinates are referenced to the centre
of the chip, see Fig.16.
SYMBOL
SCL
R20
R19
R18
R17
R16
R15
R14
R13
R12
R11
R10
R9
R8
R7
R6
R5
R4
R3
R2
R1
C101
C100
C99
C98
C97
C96
C95
C94
C93
C92
C91
C90
C89
C88
C87
C86
C85
C84
C83
C82
1998 Apr 07
PAD
x
y
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
−4303.6
−4303.6
−4303.6
−4303.6
−4303.6
−4303.6
−4303.6
−4303.6
−4303.6
−4303.6
−4303.6
−4303.6
−4303.6
−4303.6
−4303.6
−4303.6
−4303.6
−4303.6
−4303.6
−4303.6
−4303.6
−4303.6
−4303.6
−4303.6
−4303.6
−4303.6
−4303.6
−3903.6
−3803.6
−3703.6
−3603.6
−3503.6
−3403.6
−3303.6
−3203.6
−3103.6
−3003.6
−2903.6
−2803.6
−2703.6
−2603.6
1280.0
1005.8
905.8
805.8
705.8
605.8
505.8
405.8
305.8
205.8
105.8
5.8
−94.3
−194.3
−383.3
−483.3
−583.3
−683.3
−783.3
−883.3
−983.3
−1083.3
−1183.3
−1283.3
−1383.3
−1483.3
−1583.3
−1823.5
−1823.5
−1823.5
−1823.5
−1823.5
−1823.5
−1823.5
−1823.5
−1823.5
−1823.5
−1823.5
−1823.5
−1823.5
−1823.5
SYMBOL
C81
C80
C79
C78
C77
C76
C75
C74
C73
C72
C71
C70
C69
C68
C67
C66
C65
C64
C63
C62
C61
C60
C59
C58
C57
C56
C55
C54
C53
C52
C51
C50
C49
C48
C47
C46
C45
C44
C43
C42
C41
20
PAD
x
y
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
−2503.6
−2403.6
−2303.6
−2203.6
−2103.6
−2003.6
−1814.6
−1714.6
−1614.6
−1514.6
−1414.6
−1314.6
−1214.6
−1114.6
−1014.6
−914.6
−814.6
−714.6
−614.6
−514.6
−414.6
−314.6
−214.6
−114.6
−14.6
85.4
274.4
374.4
474.4
574.4
674.4
774.4
874.4
974.4
1074.4
1174.4
1274.4
1374.4
1474.4
1574.4
1674.4
−1823.5
−1823.5
−1823.5
−1823.5
−1823.5
−1823.5
−1823.5
−1823.5
−1823.5
−1823.5
−1823.5
−1823.5
−1823.5
−1823.5
−1823.5
−1823.5
−1823.5
−1823.5
−1823.5
−1823.5
−1823.5
−1823.5
−1823.5
−1823.5
−1823.5
−1823.5
−1823.5
−1823.5
−1823.5
−1823.5
−1823.5
−1823.5
−1823.5
−1823.5
−1823.5
−1823.5
−1823.5
−1823.5
−1823.5
−1823.5
−1823.5
Philips Semiconductors
Objective specification
Universal LCD driver for small graphic
panels
SYMBOL
C40
C39
C38
C37
C36
C35
C34
C33
C32
C31
C30
C29
C28
C27
C26
C25
C24
C23
C22
C21
C20
C19
C18
C17
C16
C15
C14
C13
C12
C11
C10
C9
C8
C7
C6
C5
C4
C3
C2
C1
R21
R22
R23
R24
1998 Apr 07
PAD
x
y
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
1774.4
1874.4
1974.4
2074.4
2174.4
2363.4
2463.4
2563.4
2663.4
2763.4
2863.4
2963.4
3063.4
3163.4
3263.4
3363.4
3463.4
3563.4
3663.4
3763.4
3863.4
3963.4
4063.4
4303.6
4303.6
4303.6
4303.6
4303.6
4303.6
4303.6
4303.6
4303.6
4303.6
4303.6
4303.6
4303.6
4303.6
4303.6
4303.6
4303.6
4303.6
4303.6
4303.6
4303.6
−1823.5
−1823.5
−1823.5
−1823.5
−1823.5
−1823.5
−1823.5
−1823.5
−1823.5
−1823.5
−1823.5
−1823.5
−1823.5
−1823.5
−1823.5
−1823.5
−1823.5
−1823.5
−1823.5
−1823.5
−1823.5
−1823.5
−1823.5
−1583
−1483
−1383
−1283
−1183
−1083
−983
−883
−783
−683
−583
−483
−383
−283
−183
5.8
105.8
483
583
683
783
PCF8558
SYMBOL
R25
R26
R27
R28
R29
R30
R31
R32
R33
R34
R35
R36
R37
R38
R39
R40
T2
SDA
VSS
T1
VLCD
SA0
T3
OSC
VDD
PAD
x
y
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
4303.6
4303.6
4303.6
4303.6
4303.6
4303.6
4303.6
4303.6
4017.1
3917.1
3817.1
3717.1
3617.1
3517.1
3417.1
3317.1
−2695.6
−3044.1
−3190.6
−3362.1
−3463.6
−3635.1
−3735.1
−3839.1
−3939.6
883
983
1083
1183
1283
1383
1483
1583
1823.5
1823.5
1823.5
1823.5
1823.5
1823.5
1823.5
1823.5
1823.5
1823.5
1823.5
1823.5
1823.5
1823.5
1823.5
1823.5
1823.5
−
−
−
−
−
−
−
−
−
−
−257.1
−155.6
−54.1
47.4
148.9
250.4
−4223.6
4303.5
−4303.6
4323.6
1790.4
1790.4
1790.4
1790.4
1790.4
1790.4
1823.4
1843.5
−1843.5
−1843.5
−
−
−
−4082.6
4147.4
−4262.6
−1782.5
1807.5
1417.5
Dummy pads
dummy 1
dummy 2
dummy 3
dummy 4
dummy 5
dummy 6
dummy 7
dummy 8
dummy 9
dummy 10
Alignment marks
Sign C
Sign C
Sign F
21
Philips Semiconductors
Objective specification
Universal LCD driver for small graphic
panels
PCF8558
DEFINITIONS
Data sheet status
Objective specification
This data sheet contains target or goal specifications for product development.
Preliminary specification
This data sheet contains preliminary data; supplementary data may be published later.
Product specification
This data sheet contains final product specifications.
Limiting values
Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or
more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation
of the device at these or at any other conditions above those given in the Characteristics sections of the specification
is not implied. Exposure to limiting values for extended periods may affect device reliability.
Application information
Where application information is given, it is advisory and does not form part of the specification.
LIFE SUPPORT APPLICATIONS
These products are not designed for use in life support appliances, devices, or systems where malfunction of these
products can reasonably be expected to result in personal injury. Philips customers using or selling these products for
use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such
improper use or sale.
PURCHASE OF PHILIPS I2C COMPONENTS
Purchase of Philips I2C components conveys a license under the Philips’ I2C patent to use the
components in the I2C system provided the system conforms to the I2C specification defined by
Philips. This specification can be ordered using the code 9398 393 40011.
1998 Apr 07
22
Philips Semiconductors
Objective specification
Universal LCD driver for small graphic
panels
NOTES
1998 Apr 07
23
PCF8558
Philips Semiconductors – a worldwide company
Argentina: see South America
Australia: 34 Waterloo Road, NORTH RYDE, NSW 2113,
Tel. +61 2 9805 4455, Fax. +61 2 9805 4466
Austria: Computerstr. 6, A-1101 WIEN, P.O. Box 213, Tel. +43 160 1010,
Fax. +43 160 101 1210
Belarus: Hotel Minsk Business Center, Bld. 3, r. 1211, Volodarski Str. 6,
220050 MINSK, Tel. +375 172 200 733, Fax. +375 172 200 773
Belgium: see The Netherlands
Brazil: see South America
Bulgaria: Philips Bulgaria Ltd., Energoproject, 15th floor,
51 James Bourchier Blvd., 1407 SOFIA,
Tel. +359 2 689 211, Fax. +359 2 689 102
Canada: PHILIPS SEMICONDUCTORS/COMPONENTS,
Tel. +1 800 234 7381
China/Hong Kong: 501 Hong Kong Industrial Technology Centre,
72 Tat Chee Avenue, Kowloon Tong, HONG KONG,
Tel. +852 2319 7888, Fax. +852 2319 7700
Colombia: see South America
Czech Republic: see Austria
Denmark: Prags Boulevard 80, PB 1919, DK-2300 COPENHAGEN S,
Tel. +45 32 88 2636, Fax. +45 31 57 0044
Finland: Sinikalliontie 3, FIN-02630 ESPOO,
Tel. +358 9 615800, Fax. +358 9 61580920
France: 51 Rue Carnot, BP317, 92156 SURESNES Cedex,
Tel. +33 1 40 99 6161, Fax. +33 1 40 99 6427
Germany: Hammerbrookstraße 69, D-20097 HAMBURG,
Tel. +49 40 23 53 60, Fax. +49 40 23 536 300
Greece: No. 15, 25th March Street, GR 17778 TAVROS/ATHENS,
Tel. +30 1 4894 339/239, Fax. +30 1 4814 240
Hungary: see Austria
India: Philips INDIA Ltd, Band Box Building, 2nd floor,
254-D, Dr. Annie Besant Road, Worli, MUMBAI 400 025,
Tel. +91 22 493 8541, Fax. +91 22 493 0966
Indonesia: PT Philips Development Corporation, Semiconductors Division,
Gedung Philips, Jl. Buncit Raya Kav.99-100, JAKARTA 12510,
Tel. +62 21 794 0040 ext. 2501, Fax. +62 21 794 0080
Ireland: Newstead, Clonskeagh, DUBLIN 14,
Tel. +353 1 7640 000, Fax. +353 1 7640 200
Israel: RAPAC Electronics, 7 Kehilat Saloniki St, PO Box 18053,
TEL AVIV 61180, Tel. +972 3 645 0444, Fax. +972 3 649 1007
Italy: PHILIPS SEMICONDUCTORS, Piazza IV Novembre 3,
20124 MILANO, Tel. +39 2 6752 2531, Fax. +39 2 6752 2557
Japan: Philips Bldg 13-37, Kohnan 2-chome, Minato-ku, TOKYO 108,
Tel. +81 3 3740 5130, Fax. +81 3 3740 5077
Korea: Philips House, 260-199 Itaewon-dong, Yongsan-ku, SEOUL,
Tel. +82 2 709 1412, Fax. +82 2 709 1415
Malaysia: No. 76 Jalan Universiti, 46200 PETALING JAYA, SELANGOR,
Tel. +60 3 750 5214, Fax. +60 3 757 4880
Mexico: 5900 Gateway East, Suite 200, EL PASO, TEXAS 79905,
Tel. +9-5 800 234 7381
Middle East: see Italy
Netherlands: Postbus 90050, 5600 PB EINDHOVEN, Bldg. VB,
Tel. +31 40 27 82785, Fax. +31 40 27 88399
New Zealand: 2 Wagener Place, C.P.O. Box 1041, AUCKLAND,
Tel. +64 9 849 4160, Fax. +64 9 849 7811
Norway: Box 1, Manglerud 0612, OSLO,
Tel. +47 22 74 8000, Fax. +47 22 74 8341
Pakistan: see Singapore
Philippines: Philips Semiconductors Philippines Inc.,
106 Valero St. Salcedo Village, P.O. Box 2108 MCC, MAKATI,
Metro MANILA, Tel. +63 2 816 6380, Fax. +63 2 817 3474
Poland: Ul. Lukiska 10, PL 04-123 WARSZAWA,
Tel. +48 22 612 2831, Fax. +48 22 612 2327
Portugal: see Spain
Romania: see Italy
Russia: Philips Russia, Ul. Usatcheva 35A, 119048 MOSCOW,
Tel. +7 095 755 6918, Fax. +7 095 755 6919
Singapore: Lorong 1, Toa Payoh, SINGAPORE 319762,
Tel. +65 350 2538, Fax. +65 251 6500
Slovakia: see Austria
Slovenia: see Italy
South Africa: S.A. PHILIPS Pty Ltd., 195-215 Main Road Martindale,
2092 JOHANNESBURG, P.O. Box 7430 Johannesburg 2000,
Tel. +27 11 470 5911, Fax. +27 11 470 5494
South America: Al. Vicente Pinzon, 173, 6th floor,
04547-130 SÃO PAULO, SP, Brazil,
Tel. +55 11 821 2333, Fax. +55 11 821 2382
Spain: Balmes 22, 08007 BARCELONA,
Tel. +34 3 301 6312, Fax. +34 3 301 4107
Sweden: Kottbygatan 7, Akalla, S-16485 STOCKHOLM,
Tel. +46 8 5985 2000, Fax. +46 8 5985 2745
Switzerland: Allmendstrasse 140, CH-8027 ZÜRICH,
Tel. +41 1 488 2741 Fax. +41 1 488 3263
Taiwan: Philips Semiconductors, 6F, No. 96, Chien Kuo N. Rd., Sec. 1,
TAIPEI, Taiwan Tel. +886 2 2134 2865, Fax. +886 2 2134 2874
Thailand: PHILIPS ELECTRONICS (THAILAND) Ltd.,
209/2 Sanpavuth-Bangna Road Prakanong, BANGKOK 10260,
Tel. +66 2 745 4090, Fax. +66 2 398 0793
Turkey: Talatpasa Cad. No. 5, 80640 GÜLTEPE/ISTANBUL,
Tel. +90 212 279 2770, Fax. +90 212 282 6707
Ukraine: PHILIPS UKRAINE, 4 Patrice Lumumba str., Building B, Floor 7,
252042 KIEV, Tel. +380 44 264 2776, Fax. +380 44 268 0461
United Kingdom: Philips Semiconductors Ltd., 276 Bath Road, Hayes,
MIDDLESEX UB3 5BX, Tel. +44 181 730 5000, Fax. +44 181 754 8421
United States: 811 East Arques Avenue, SUNNYVALE, CA 94088-3409,
Tel. +1 800 234 7381
Uruguay: see South America
Vietnam: see Singapore
Yugoslavia: PHILIPS, Trg N. Pasica 5/v, 11000 BEOGRAD,
Tel. +381 11 625 344, Fax.+381 11 635 777
For all other countries apply to: Philips Semiconductors,
International Marketing & Sales Communications, Building BE-p, P.O. Box 218,
5600 MD EINDHOVEN, The Netherlands, Fax. +31 40 27 24825
Internet: http://www.semiconductors.philips.com
© Philips Electronics N.V. 1998
SCA59
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner.
The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed
without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license
under patent- or other industrial or intellectual property rights.
Printed in The Netherlands
415106/1200/02/pp24
Date of release: 1998 Apr 07
Document order number:
9397 750 03284