PHILIPS P83C834CFP

INTEGRATED CIRCUITS
DATA SHEET
P83C434; P83C834
8-bit microcontrollers with
LCD-driver
Product specification
Supersedes data of 1996 Oct 16
File under Integrated Circuits, IC20
1997 Jul 03
Philips Semiconductors
Product specification
8-bit microcontrollers with LCD-driver
CONTENTS
P83C434; P83C834
7
LIMITING VALUES
8
HANDLING
9
DC CHARACTERISTICS
10
LCD DRIVER CHARACTERISTICS
1
FEATURES
1.1
1.2
Differences from the 80C51 core
Memory
2
GENERAL DESCRIPTION
11
AC CHARACTERISTICS
3
ORDERING INFORMATION
11.1
Characteristic curves
4
BLOCK DIAGRAM
12
APPLICATION INFORMATION
5
PINNING INFORMATION
13
PACKAGE OUTLINE
5.1
5.2
Pinning
Pin description
14
SOLDERING
6
FUNCTIONAL DESCRIPTION
6.1
6.2
6.3
6.4
6.5
6.6
6.7
Input/Output (I/O)
Oscillator
Interrupts
Reduced power modes
Reset
Special Function Registers (SFRs)
LCD driver unit
14.1
14.2
14.3
Introduction
SDIP
QFP
15
DEFINITIONS
16
LIFE SUPPORT APPLICATIONS
1997 Jul 03
2
Philips Semiconductors
Product specification
8-bit microcontrollers with LCD-driver
1
P83C434; P83C834
• Timer 0 external input replaced by a direct connection to
the 32 kHz oscillator output.
FEATURES
• 80C51 type core
• Timer 1 external input is connected to pin P0.0 (Port 0);
alternate function of P0.0.
• System clock derived from an internal free running
Current Controlled Oscillator (CCO); no external
components required. Clock frequency can be adjusted
by software.
• Standard serial interface and its control register is not
present.
• Adjustable on-chip oscillator without external
components.
• Optimized for EMC (Electromagnetic Compatibility)
• Clock frequency fclk = 1 to 12 MHz
• Wake-up from Power-down mode is also possible by
means of an interrupt.
• 12 I/O lines, quasi-bidirectional
• Gated interrupt on 8 I/O lines:
• Extended external interrupts.
– P0.0 to P0.3 when LOW
1.2
– P0.4 to P0.7 when LOW or HIGH
• LCD driver clock, 32 kHz, which also provides the time
base for a Real Time Clock
Memory
Table 1
ROM/RAM sizes
MEMORY
• 1-second interrupt by internal 15-bit counter
DEVICE
ROM
• On-chip Liquid Crystal Display (LCD) drivers with
26 outputs, comprising:
– 22, 23 or 24 segment drivers
RAM
P83C434
4 kbytes
128 bytes
P83C834
8 kbytes
256 bytes
– 1 to 4 backplanes
• LCD multiplexing rates: 1 : 1 (static), 1 : 2, 1 : 3 or 1 : 4
2
• Operating temperature: −40 to +85 °C
The P83C434 and P83C834 are low-cost microcontrollers
of the 80C51 family, with LCD drivers.
Main application is in the user-interface (keypad, display)
of consumer products, e.g. portable radios, CD-players,
etc.
• Single power supply:
– Operating voltage: 3.5 to 5.5 V
– Power-down mode: 1.8 V.
1.1
GENERAL DESCRIPTION
This data sheet details the specific properties of the
P83C434 and P83C834. The shared characteristics of the
80C51 family of microcontrollers are described in “Data
Handbook IC20”, which should be read in conjunction with
this data sheet.
Differences from the 80C51 core
• Port 0 quasi-bidirectional instead of open-drain.
• No external memory connection.
Signals EA, ALE and PSEN are not present.
• Port 1, Port 2 (pins P2.4 to P2.7) and Port 3 are not
present.
3
ORDERING INFORMATION
PACKAGE
VERSION
TEMP.
RANGE (°C)
SOT270-1
−40 to +85
TYPE NUMBER
NAME
P83C434CFP;
P83C834CFP
1997 Jul 03
DESCRIPTION
SDIP42 plastic shrink dual in-line package; 42 leads (600 mil)
QFP44 plastic quad flat package; 44 leads (lead length 1.3 mm); SOT307-2
body 10 × 10 × 1.75 mm
3
1997 Jul 03
4
MCON.3
MCON.2
MCON.1
MCON.0
RESET
VSS
8
8
INTERRUPT GATES
REGISTER (IG).
8
INTERRUPT
GATES
8
0
1
P2.0 to P2.3
2
T0
3
T1
EI1
0
80C51 CORE
1
2
3
P0.0 to P0.7
4
5
6
CLOCK
7
EI0
internal bus
VDD(C)
Fig.1 Block diagram.
MCON
CCO
MCON.4
D/A
LCD
UNIT
internal
CLOCK
OSCON
S00 S22/ S23/ BP1 BP0
to BP3 BP2
MGG012
S21
(1)
8
OSC
1-SECOND COUNTER
MCON.5
XTAL2
32
kHz
XTAL1
8-bit microcontrollers with LCD-driver
(1) Drive lines S00 and S21 are not available with the SDIP42 (SOT270-1) package.
P0.0
P0.1
P0.2
P0.3
P0.4
P0.5
P0.6
P0.7
VDD(P)
4
P2.0
P2.1
P2.2
P2.3
handbook, full pagewidth
Philips Semiconductors
Product specification
P83C434; P83C834
BLOCK DIAGRAM
Philips Semiconductors
Product specification
8-bit microcontrollers with LCD-driver
5
5.1
P83C434; P83C834
PINNING INFORMATION
Pinning
handbook, halfpage
S23/BP2
1
42 S22/BP3
BP1
2
41 S20
BP0
3
40 S19
P2.0
4
39 S18
P2.1
5
38 S17
P2.2
6
37 S16
P2.3
7
36 S15
RESET
8
35 S14
VDD(P)
9
34 S13
VSS 10
VDD(C) 11
P83C434
P83C834
33 S12
32 S11
XTAL1 12
31 S10
XTAL2 13
30 S09
P0.0 14
29 S08
P0.1 15
28 S07
P0.2 16
27 S06
P0.3 17
26 S05
P0.4 18
25 S04
P0.5 19
24 S03
P0.6 20
23 S02
P0.7 21
22 S01
MGG011
Fig.2 Pinning diagram for SDIP42 (SOT270-1).
1997 Jul 03
5
Philips Semiconductors
Product specification
34 S17
35 S18
36 S19
37 S20
38 S21
P83C434; P83C834
39 S22/BP3
41 BP1
42 BP0
44 P2.1
43 P2.0
handbook, full pagewidth
40 S23/BP2
8-bit microcontrollers with LCD-driver
P2.2
1
33 S16
P2.3
2
32 S15
RESET
3
31 S14
VDD(P)
4
30 S13
VSS
5
VDD(C)
6
XTAL1
7
27 S10
XTAL2
8
26 S09
P0.0
9
25 S08
P0.1 10
24 S07
P0.2 11
23 P06
29 S12
S05 22
S04 21
S03 20
28 S11
S02 19
S01 18
S00 17
P0.7 16
P0.6 15
P0.5 14
P0.4 13
P0.3 12
P83C434
P83C834
MGG010
Fig.3 Pinning diagram for QFP44 (SOT307-2).
1997 Jul 03
6
Philips Semiconductors
Product specification
8-bit microcontrollers with LCD-driver
5.2
P83C434; P83C834
Pin description
Table 2
Pin description for SDIP42 and QFP44
PIN
SYMBOL
DESCRIPTION
SDIP42
(SOT270-1)
QFP44
(SOT307-2)
S23/BP2
1
40
segment drive line 23/Backplane drive line 2
BP1
2
41
backplane drive line 1
BP0
3
42
backplane drive line 0
P2.0 to P2.3
4 to 7
43, 44, 1 and 2 quasi-bidirectional I/O line
RESET
8
3
reset input
VDD(P)
9
4
power supply (+) for periphery and LCD unit; see note 1
VSS
10
5
ground; double bonded
VDD(C)
11
6
power supply for the core; see note 1
XTAL1
12
7
oscillator, XTAL connections
XTAL2
P0.0 to P0.7
S00
S01 to S20
13
8
14 to 21
9 to 16
−
17
Port 0: quasi-bidirectional I/O lines
segment drive line 0; see note 2
22 to 41
18 to 37
S21
−
38
segment drive line 21; see note 2
segment drive line 1 to 20
S22/BP3
42
39
segment drive line 22/Backplane drive line 3
Notes
1. For proper VDD supply to VDD(P) and VDD(C) see Section 6.1.1.
2. In package SDIP42 (SOT270-1) segment drive lines S00 and S21 are not connected, so the total number of drive
lines is 22.
1997 Jul 03
7
Philips Semiconductors
Product specification
8-bit microcontrollers with LCD-driver
6
P83C434; P83C834
• The power supply and ground pins are placed next to
each other.
FUNCTIONAL DESCRIPTION
The block diagram is shown in Fig.1. The P83C434 and
P83C834 provide all functions that are required for a user
interface. This is illustrated in the radio application detailed
in Chapter 12. In the following sections the functions of the
device are described.
6.1
• Double bonding VSS pins, i.e. 2 bondpads for each pin.
• Limiting the drive capability of:
– clock drivers and prechargers.
– segment drivers and backplane drivers for the LCD.
• External decoupling of the of the CPU supply VDD(C);
to avoid interference on the VDD line, the VDD(C) and
VDD(P) pins should be connected as illustrated in Fig.4.
Input/Output (I/O)
A total of 12 I/O lines are available.
Port 0 P0.0 to P0.7 (8 lines).
Port configuration: Quasi-bidirectional (push-pull in
emulation mode). For the Interrupt generation see
Fig.10. If one of the port lines P0.0 to P0.3 is a
logic 0 or one of the port lines P0.4 to P0.7 is equal
to the corresponding bit in the Miscellaneous
Control Register (MCON) and the corresponding bit
in the Interrupt Gate Register (IG) is a logic 1, then
an INT0 interrupt is generated.
VDD
handbook, halfpage
2.2 µH
Port 2 P2.0 to P2.3 (4 lines).
Port configuration: Quasi-bidirectional (push-pull in
emulation mode). When writing to Port 2, bits
P2.4 to P2.7 have to be fixed at HIGH. Data to be
written should be ‘1111XXXXB’.
6.1.1
VDD(C)
VDD(P)
P83C434
P83C834
EMC (ELECTROMAGNETIC COMPATIBILITY)
MGG019
In order to reduce EMI (Electromagnetic Interference) the
following design measures have been taken:
• Slope control is implemented on all the I/O lines.
Rise and fall time (10% to 90%) are:
20 ns < rise/fall time < 50 ns.
Fig.4 Avoiding interference on VDD.
strong pull-up
handbook, full pagewidth
VDD
2 oscillator
periods
p2
p3
p1
I/O PIN
Q
from port latch
n
I1
input data
read port pin
INPUT
BUFFER
MLC926 - 1
Fig.5 Standard output with switched pull-up current source.
1997 Jul 03
8
Philips Semiconductors
Product specification
8-bit microcontrollers with LCD-driver
6.2
6.2.1
P83C434; P83C834
Table 3
Oscillator
CPU CLOCK
The internal timing circuits of the CPU are clocked by a
Current Controlled Oscillator (CCO). The oscillator is free
running and is adjusted by means of the Oscillator Control
Register (OSCON; see Section 6.6.4) and a
digital-to-analog converter; it does not require external
components. The frequency of the CPU clock can be
measured by means of Timer T0 which is clocked by the
32 kHz oscillator (see Section 6.2.2).
6.2.3
Oscillator status during Power-down mode
RUN32
32 kHz OSCILLATOR
HIGH
running
LOW
stopped
15-BIT COUNTER (1-SECOND TIMER)
An interrupt is generated every second by the 15-bit
counter. This 1-second timer is a 15-bit counter, clocked
by the 32 kHz oscillator output. When this counter
overflows it generates an INT1 interrupt by setting SECINT
in the Miscellaneous Control Register (MCON). Reset of
this interrupt is carried out via software by clearing bit
SECINT.
Adjustments can be made by changing the contents of the
OSCON register (see Fig.9). Over the range 0 to 31 the
frequency step size is constant (deviation ≤10%).
The frequency variation per step of the register is:
0.5 MHz < step size < 2 MHz.
At Power-on-reset the oscillator frequency will be:
1 MHz < fOSC < 4 MHz. Stability of the oscillator:
frequency change with time ≤1.5%. The maximum
operating frequency is: ≤12 MHz at VDD ≥4.5 V.
The minimum operating frequency is 1 MHz.
handbook, halfpage
In Power-down mode the oscillator is stopped.
6.2.2
XTAL1
LCD DRIVER CLOCK: 32 KHZ OSCILLATOR
XTAL2
MLC928
A 32 kHz oscillator provides the clocking of the LCD timing
generator and may also be used as the time base for a
Real Time Clock. The output of the 32 kHz oscillator is also
used as an input of Timer/Counter 0.
a. Crystal oscillator.
The frequency of the 32 kHz oscillator need not be exactly
32 kHz, and is determined by the component(s) connected
between pins XTAL1 and XTAL2. See Chapter 11.
handbook, halfpage
The oscillator is suitable for use with either:
XTAL1
• A crystal; connected as shown in Fig.6a
XTAL2
n.c.
• External drive; connected as shown in Fig.6b.
external clock
(not TTL compatible)
During Power-down mode, the control bit RUN32 in the
Miscellaneous Control Register (MCON) determines
whether the oscillator is stopped or running continuously;
see Table 3.
b. External clock drive.
The output of the oscillator (XTAL2) is used as an input to
the Timer/Counter 0. This can be useful for accurate time
measurements and generation of time-slots. For example
it may be used to determine (and possibly adjust) the
frequency of the CCO that is used for the CPU clock.
1997 Jul 03
MBE312
Fig.6 Oscillator configurations P83C434/P83C834.
9
Philips Semiconductors
Product specification
8-bit microcontrollers with LCD-driver
P83C434; P83C834
MBE313
16
handbook, halfpage
MBE314
16
f osc
handbook, halfpage
f osc
(MHz)
(MHz)
12
OSCON =
FH
OSCON =
FH
12
8
8
7H
7H
4
4
1H
1H
0
50
Fig.7
0
50
T ( oC)
100
0
2
fosc as function of temperature;
at VDD = 5 V.
handbook, halfpage
f osc
(MHz)
(1)
24
(2)
(3)
12
0
0
10
20
30
40
contents of OSCON (decimal) 31(max)
(1) Fast case; VDD = 5.5 V, Tamb = −40 °C.
(2) Typical case; VDD = 4.0 V, Tamb = 25 °C.
(3) Slow case; VDD = 2.0 V, Tamb = 85 °C.
Fig.9 fosc as function of OSCON.
1997 Jul 03
4
VDD (V)
Fig.8 fosc as function of VDD.
MBE315
36
3
10
5
Philips Semiconductors
Product specification
8-bit microcontrollers with LCD-driver
6.3
P83C434; P83C834
In the interrupt routine SECINT should be reset by
software so that with the next 1-second overflow another
interrupt may be generated.
Interrupts
The P83C434 and P83C834 have 4 interrupt sources;
these are shown Fig.10.
Timer 0 and Timer 1 interrupts are generated by TF0 and
TF1 which are set by an overflow of their respective
Timer/Counter registers (except for Timer 0 in mode 3;
see “Data Handbook IC20, 80C51 Family, Chapter
Timer/Counters” ). When a timer interrupt is generated, the
flag that generated it is cleared by the internal hardware
when the LCALL is executed for the vector address.
Interrupt INT0 is generated when one of the I/O lines
(P0.0 to P0.3) becomes LOW; or one of I/O lines
(P0.4 to P0.7) equals the corresponding bit in the MCON
register (ILVL0 to ILVL3). By means of bit IT0 in the TCON
register this interrupt can be chosen to be:
• Level sensitive, when IT0 = LOW; INT0 must be inactive
before a return from interrupt is given, otherwise the
same interrupt will occur again.
All of the bits that generate interrupts can be set or cleared
by software, with the same result as though it had been set
or cleared by hardware. That is, interrupts can be
generated or pending interrupts can be cancelled in
software.
• Edge sensitive, when IT0 = HIGH; the internal hardware
will reset the latch when the LCALL is executed for the
vector address (see Table 7).
Interrupt INT1 is generated by the overflow of the 1-second
counter. The overflow signal is latched. The output of the
latch will set the SECINT bit in the MCON register.
When SECINT is set the overflow latch will be reset.
Interrupt INT1 is selected as edge or level sensitive by the
state of the IT1 bit in the TCON register. However, it is
recommended to always set IT1 to HIGH (edge sensitive)
so that IE1 will be reset by the internal hardware when the
LCALL is executed for the vector address.
Each of these interrupts sources can be individually
enabled or disabled by setting or clearing the bit in Special
Function Register IE (see Table 5). IE also contains a
global disable bit EA, which disables all interrupts at once.
INTERRUPT ENABLE REGISTER (IE)
6.3.1
Table 4
Interrupt Enable Register (address A8H)
7
6
5
4
3
2
1
0
EA
−
−
−
ET1
EX1
ET0
EX0
Table 5
Description of IE bits
BIT
7
SYMBOL
EA
DESCRIPTION
Disable all interrupts. If EA is:
LOW, then no interrupt will be acknowledged.
HIGH, then each interrupt source is individually enabled or disabled by setting or
clearing its enable bit.
−
Reserved.
3
ET1
Enables or disables the Timer 1 Overflow Interrupt. If ET1 is LOW then the Timer 1
interrupt is disabled.
2
EX1
Enables or disables the External Interrupt 1. If EX1 is LOW then the External 1
interrupt is disabled.
1
ET0
Enables or disables the Timer 0 Overflow Interrupt. If ET0 is LOW then the Timer 0
interrupt is disabled.
0
EX0
Enables or disables the External Interrupt 0. If EX0 is LOW then the External 0
interrupt is disabled.
6 to 4
1997 Jul 03
11
1997 Jul 03
1
2
12
3
1
2
LATCH
1
2
3
3
handbook, full pagewidth
1
2
3
9
INT1
INT0
Fig.10 Interrupt sources.
SECINT
interrupt
gates
1
2
3
4
5
6
7
8
'1'
'0'
'1'
'0'
IT1
IT0
TF1
IE1
TF0
IE0
1
2
1
2
MLC919 - 1
3
3
TF1
IE1´
TF0
IE0´
interupt
sources
8-bit microcontrollers with LCD-driver
Timer 1 overflow
1-sec counter
overflow
1
2
3
MCON: ILVL0 to ILVL3
Timer 0 overflow
P0.7
P0.6
P0.5
P0.4
P0.3
P0.2
P0.1
P0.0
Philips Semiconductors
Product specification
P83C434; P83C834
Philips Semiconductors
Product specification
8-bit microcontrollers with LCD-driver
6.3.2
Condition 2 ensures that the instruction in progress will be
completed before vectoring to any service routine.
PRIORITY LEVEL STRUCTURE
The priority level of each interrupt source can be
individually programmed by setting or clearing a bit in the
Interrupt Priority Register (IP; see Section 6.3.4). A low
priority interrupt can itself be interrupted by a high priority
interrupt, but not by another low priority interrupt. A high
priority interrupt can not be interrupted by another interrupt
source.
Condition 3 ensures that if the instruction in progress is
RETI or any access to IE or IP, then at least one more
instruction will be executed before the interrupt is vectored
to.
The polling cycle is repeated with each machine cycle, and
the values polled are the values that were present at S5P2
of the previous machine cycle. Note that if an interrupt flag
is active but not being responded to for one of the above
mentioned conditions, if the flag is still inactive when the
blocking condition is removed, the denied interrupt will not
be serviced. In other words, the fact that the interrupt flag
was once active but not serviced is not remembered.
Every polling cycle is new.
If two requests of different priority levels are received
simultaneously, the request of higher priority level is
serviced. If request of the same priority level is received
simultaneously, an internal polling sequence determines
which request is serviced. Thus, within each priority level
there is a second priority structure determined as shown in
Table 6.
The polling cycle/LCALL sequence is illustrated in
“Data Handbook IC20, 80C51 Family, Fig.20”.
The IP register contains a number of not implemented bits.
IP.7, IP.6 and IP.5 are reserved in the 80C51.
User software should not write logic 1’s to these positions,
since they may be used in other 8051-Family products.
Table 6
Note that if an interrupt of higher priority level becomes
active prior to S5P2 of the machine cycle labelled C3
(“Data Handbook IC20, 80C51 Family, Fig.20”), then in
accordance with the above rules it will be vectored to
during C5 and C6, without any instruction of the lower
priority routine having been executed. Thus the processor
acknowledges an interrupt request by executing a
hardware generated LCALL to the appropriate servicing
routine. The hardware generated LCALL pushes the
contents of the Program Counter on to the stack (but it
does not save the PSW) and reloads the PC with an
address that depends on the source of the interrupt being
vectored to as shown in Table 7.
Priority within levels
SOURCE
PRIORITY WITHIN LEVEL(1)
IE0′
1 (highest)
TF0
2
IE1′
3
TF1
4 (lowest)
Note
1. The ‘Priority within level’ structure is only used to
resolve simultaneous requests of the same priority
level.
6.3.3
P83C434; P83C834
Execution proceeds from that location until the RETI
instruction is encountered. The RETI instruction informs
the processor that the interrupt routine is no longer in
progress, then pops the top two bytes from the stack and
reloads the Program Counter. Execution of the interrupted
program continues from where it left off.
HOW INTERRUPTS ARE HANDLED
The interrupt flags are sampled at S5P2 of every machine
cycle. The samples are polled during the following
machine cycle. If one of the flags was in a set condition at
S5P2 of the preceding cycle, the polling cycle will find it
and the interrupt system will generate an LCALL to the
appropriate service routine, provided this hardware
generated LCALL is not blocked by any of the following
conditions:
Note that a simple RET instruction would also return
execution to the interrupted program, but it would have left
the interrupt control system thinking an interrupt was still in
progress, making future interrupts impossible.
Table 7
1. An interrupt of equal priority or higher priority level is
already in progress.
Vector addresses
SOURCE
VECTOR ADDRESS
2. The current (polling) cycle is not the final cycle in the
execution of the instruction in progress.
IE0′
0003H
TF0
000BH
3. The instruction in progress is RETI or any write to the
IE or IP registers.
IE1′
0013H
TF1
001BH
1997 Jul 03
13
Philips Semiconductors
Product specification
8-bit microcontrollers with LCD-driver
6.3.4
INTERRUPT PRIORITY REGISTER (IP)
Table 8
Interrupt Priority Register (address B8H)
7
6
5
4
3
2
1
0
−
−
−
−
PT1
PX1
PT0
PX0
Table 9
Description of IP bits
BIT
6.4.1
SYMBOL
DESCRIPTION
−
Reserved.
3
PT1
Defines the Timer 1 Overflow Interrupt priority level. When PT1 is HIGH, Timer 1
Overflow Interrupt is assigned a high priority level.
2
PX1
Defines the External Interrupt 1 priority level. When PX1 is HIGH, External
Interrupt 1 is assigned a high priority level.
1
PT0
Defines the Timer 0 Overflow Interrupt priority level. When PT0 is HIGH, Timer 0
Overflow Interrupt is assigned a high priority level.
0
PX0
Defines the External Interrupt 0 priority level. When PX0 is HIGH, External
Interrupt 0 is assigned a high priority level.
7 to 4
6.4
To terminate the Power-down mode with an external
interrupt, INT0 or INT1 must be switched to level-sensitive
and must be enabled. The external interrupt input signal
INT0 and INT1 must be kept LOW until the oscillator has
restarted and stabilized. An instruction following the
instruction that puts the device in the Power-down mode
will be executed. The control bits for the reduced power
modes are in the Special Function Register PCON.
Reduced power modes
IDLE MODE
In the Idle mode, the CPU puts itself to sleep while all of
the on-chip peripherals remain active. The instruction to
invoke the Idle mode is the last instruction executed in the
normal operating mode before the Idle mode is activated.
The CPU contents, the on-chip RAM, and all of the special
function registers remain intact during this mode. The Idle
mode can be terminated either by any enabled interrupt (at
which time the process is picked up at the interrupt service
routine and continued), or by a hardware reset which starts
the processor in the same manner as a power-on reset.
6.4.2
P83C434; P83C834
To wake-up the microcontroller by a reset, the RESET pin
must be kept HIGH for a minimum of 36 µs.
6.5
Reset is accomplished either at power-on when the supply
voltage rises above Power-on-reset threshold or by a
logic 1 signal at the RESET pin.
The Power-on-reset threshold is minimum 1.8 V and
maximum 3.0 V. The RESET signal should be active
(HIGH) for at least 2 machine cycles (24 oscillator
periods).
POWER-DOWN MODE
In the Power-down mode, the CCO oscillator (processor
clock) is stopped; as the instruction to invoke Power-down
mode is the last instruction executed. Whether the 32 kHz
oscillator is stopped depends on bit RUN32 in the MCON
register (MCON5). The Power-down mode can be
terminated by a RESET in same way as in the 80C51 or in
addition by one of two external interrupts, INT0 or INT1.
The reset algorithm puts registers and flip-flops in a
defined state (see 80C51 Family specification in “Data
Handbook IC20” and Section 6.6.1). The I/O ports are set
to a logic 1 at reset.
A termination with an external interrupt does not affect the
internal data memory and does not affect the Special
Function Registers. This makes it possible to exit
Power-down without changing the port output levels.
1997 Jul 03
Reset
To wake-up from power-down the RESET signal must be
kept HIGH for a minimum of 36 µs.
14
Philips Semiconductors
Product specification
8-bit microcontrollers with LCD-driver
6.6
P83C434; P83C834
Special Function Registers (SFRs)
6.6.1
CHANGES W.R.T. 80C51 KERNEL
• Removed SFRs: P3, P1, SCON and SBUF
• Added SFRs: IG, MCON, OSCON, LCDCON and LCD0 to LCD11.
Table 10 Overview of the additional SFRs
All SFRs are Read/Write registers.
REGISTER
DESCRIPTION
ADDRESS
RESET VALUE
IG
Interrupt Gate Register
97H
00H
MCON
Miscellaneous Control Register
98H
00H
OSCON
Oscillator Control Register
B7H
01H
LCDCON
LCD Control Register
LCD0 to LCD5
LCD segment display registers
LCD6 to LCD11
6.6.2
B9H
0CH
9AH to 9FH
00H
BAH to BFH
00H
INTERRUPT GATE REGISTER (IG)
Table 11 Interrupt Gate Register (address 97H)
7
6
5
4
3
2
1
0
IG.7
IG.6
IG.5
IG.4
IG.3
IG.2
IG.1
IG.0
Table 12 Description of IG bits
BIT
7 to 0
SYMBOL
IG.7 to IG.0
DESCRIPTION
gate signals for interrupt from I/O lines P0.7 to P0.0. If signal IG.n is:
LOW, then no interrupt is possible
HIGH, then interrupt is possible
1997 Jul 03
15
Philips Semiconductors
Product specification
8-bit microcontrollers with LCD-driver
6.6.3
P83C434; P83C834
MISCELLANEOUS CONTROL REGISTER (MCON)
This register is bit-addressable.
Table 13 Miscellaneous Control Register (address 98H)
7
6
5
4
3
2
1
0
−
−
RUN32
SECINT
ILVL3
ILVL2
ILVL1
ILVL0
Table 14 Description of MCON bits
BIT
7 and 6
5
SYMBOL
DESCRIPTION
−
Reserved.
RUN32
Prevent stop of 32 kHz oscillator in Power-down mode. If RUN32 is:
HIGH, then the 32 kHz oscillator is not stopped in Power-down mode.
LOW, then the 32 kHz oscillator is stopped in Power-down mode.
4
SECINT
1-second interrupt flag. Is set by hardware on overflow of the 1-second counter.
Can be Set/Reset via software. If SECINT is:
HIGH, then there is an interrupt on overflow.
LOW, then there is no interrupt on overflow.
3 to 0
ILVL3
to
ILVL0
The state of these bits determine the signal level of the inputs P0.m (m = 4 to 7) which
will generate the interrupt EI0 (dependent on bits IG.4 to IG.7 respectively).
If ILVLn (n = 0 to 3) is:
LOW, then P0.m = LOW, will cause an interrupt.
HIGH, then P0.m = HIGH, will cause an interrupt.
OSCILLATOR CONTROL REGISTER (OSCON)
6.6.4
Table 15 Oscillator Control Register (address B7H)
7
6
5
4
3
2
1
0
−
−
−
OSCON.4
OSCON.3
OSCON.2
OSCON.1
OSCON.0
Table 16 Description of OSCON bits
BIT
SYMBOL
DESCRIPTION
7 to 5
−
Reserved.
4 to 0
OSCON.4
to
OSCON.0
These 5 bits can hold a decimal value in the range of 0 to 31, that will be converted to a
current that controls the frequency of the CCO of the CPU clock; can be set by software.
The register value is converted to an analog current that controls the oscillator
(see Section 6.2.1).
1997 Jul 03
16
Philips Semiconductors
Product specification
8-bit microcontrollers with LCD-driver
6.6.5
P83C434; P83C834
LCD CONTROL REGISTER (LCDCON)
After an external or Power-on-reset the LCD Control Register holds the value 0CH (see Table 10) resulting in:
• The LCD is disabled. All segment and backplane drivers are set to the VSS level.
• BIAS is set to generate 1⁄3VDD(P).
• Bits MD0 and MD1 reset the multiplex ratio to the 1 : 4 mode.
Table 17 LCD Control Register (address B9H)
7
6
5
4
3
2
1
0
−
−
−
−
MD1
MD0
BIAS
ENLCD
Table 18 Description of LCDCON bits
BIT
SYMBOL
DESCRIPTION
−
Reserved.
3
MD1
Mode bits. MD0 and MD1 determine the multiplex rate; see Table 19.
2
MD0
1
BIAS
7 to 4
The BIAS bit sets the LCD voltage bias generator. If BIAS is:
HIGH, then the LCD voltage bias generator is set to 1⁄2VDD(P).
LOW, then the LCD voltage bias generator is set to 1⁄3VDD(P).
0
ENLCD
Enable LCD. If ENLCD is:
LOW, then the LCD is disabled.
All segment and backplane drivers are set to the VSS level.
HIGH, then the LCD is enabled and character display is possible.
Table 19 Multiplex ratio mode selection
6.6.6
MD1
MD0
MULTIPLEX RATIO MODE
0
0
static
0
1
1:2
1
0
1:3
1
1
1:4
LCD SEGMENT DISPLAY REGISTERS (LCD0 TO LCD11)
The 12 display registers, LCD0 to LCD11, are 8-bit derivative (Read/Write) registers which store LCD segment data.
For detailed information, regarding the LCD0 to LCD11, see Table 23 in Section 6.7.7.
1997 Jul 03
17
Philips Semiconductors
Product specification
8-bit microcontrollers with LCD-driver
6.7
P83C434; P83C834
The display configurations possible with the P83C434 and
P83C834 depend on the number of active backplane
outputs required.
LCD driver unit
The LCD driver unit has 24 segment drivers, two of which
can also serve as backplane drivers. Selection will be done
automatically, depending on the multiplex ratio as shown
in Table 20.
6.7.1
A selection of display configurations is given in Table 21.
The appropriate biasing voltages for the multiplexed LCD
wave forms are generated internally.
FUNCTIONAL DESCRIPTION OF THE LCD DRIVER
At power-on all the LCD driver control register bits are
cleared. The LCD driver is not affected by executing Idle or
Power-down modes.
The P83C434 and P83C834 have a display driver which
interfaces to almost any LCD which has a low multiplex
rate. The interface delivers drive signals for any static or
multiplexed LCD panel that contains up to 4 backplanes
and up to 24 segments. Figure 11 shows the block
diagram of the LCD driver. The following features are
incorporated:
6.7.2
The LCD operating voltage: Vop = VDD(P) − VSS.
Vop should be chosen so that the off voltage (Voff(rms)) is
just below the threshold voltage (Vth), typically when the
LCD exhibits 10% contrast. Fractional LCD biasing
voltages are obtained from an internal voltage divider of
three resistors connected between VSS and VDD(P). The
centre resistor may be switched out of circuit to provide a
1⁄ bias voltage level for a 1 : 2 multiplex configuration.
2
• Selection of backplane drive configuration:
– static
– 2, 3 or 4 backplane multiplexing
• Selection of display bias configuration:
–
1⁄
2
internal LCD bias generation
–
1⁄
3
internal LCD bias generation
LCD BIAS GENERATION
6.7.3
• 24 individual segment drivers can be used to provide:
LCD VOLTAGE SELECTOR
The LCD voltage selector coordinates the multiplexing of
the LCD according to the selected drive configuration.
The operation of the voltage selector is controlled by the
MODE bits in the LCD control byte.
– up to twelve 7-segment numeric characters
– up to six 14-segment alphanumeric characters
– graphic using up to 88 elements
The biasing configurations that apply to the preferred
mode of operation, together with the biasing
characteristics as functions of Vop = VDD(P) − VSS and the
resulting discrimination ratios (D), are given in Table 22.
– twelve 8-bit derivative registers for display data bits.
handbook, full pagewidth
CLOCK
LCD VOLTAGE SELECTOR
SEGMENT
REGISTERS
VDD(P)
24
4
LCD DRIVERS
8
SEGMENT
BACKPLANE
LCD BIAS
GENERATION
internal
bus
LCD CONTROL
REGISTER
22
MUX.
MGG013
S0 to S21 S22/BP3 S23/BP2 BP1 BP0
Fig.11 Block diagram of the LCD driver.
1997 Jul 03
18
VSS
Philips Semiconductors
Product specification
8-bit microcontrollers with LCD-driver
P83C434; P83C834
Table 20 Mode selection Segments/Backplanes
MULTIPLEX RATIO
SEGMENTS
BACKPLANES
1 : 1 (static)
S00 to S21, S22/BP3, S23/BP2
BP0
1:2
S00 to S21, S22/BP3, S23/BP2
BP0, BP1
1:3
S00 to S21, S22/BP3
BP0, BP1, S23BP2
1:4
S00 to S21
BP0, BP1, S23/BP2, S22/BP3
Table 21 Selection of display configurations
NUMBER OF
14-SEGMENTS
ALPHANUMERIC
7-SEGMENTS NUMERIC
DOT MATRIX
BACKPLANES SEGMENTS
4
88
DIGITS
INDICATOR
SYMBOLS
CHARACTERS
INDICATOR
SYMBOLS
12
4
6
4
88 dots (4 × 22)
3
69
9
6
4
13
69 dots (3 × 23)
2
48
6
6
3
6
48 dots (2 × 24)
1
24
3
3
1
10
24 dots (1 × 24)
Table 22 LCD drive modes and characteristics
NUMBER OF
V off(rms)
--------------------V op
V on(rms)
--------------------V op
V on(rms)
D = --------------------V off(rms)
BACKPLANES
LEVELS
LCD BIAS
CONFIGURATION
static
1
2
static
0
1
∞
1:2
2
3
1⁄
2
0.354
0.791
2.236
1:2
2
4
1⁄
3
0.333
0.745
2.236
3
0.333
0.638
1.915
3
0.333
0.577
1.7321
LCD DRIVE MODE
3(1)
3
4
1⁄
1 : 4(1)
4
4
1⁄
1:
Note
1. Multiplex drive ratios of 1 : 3 and 1 : 4 with 1⁄2 bias are possible, but the discrimination contrast ratios are reduced;
for 1 : 3, D = 1.732 and for 1 : 4, D = 1.528. However, there is an advantage that leads to reduction of Vop as follows:
a) for 1 : 3 multiplex (1⁄2 bias), Vop = 2.449 × Voff(rms).
b) For 1 : 4 multiplex (1⁄2 bias), Vop = 2.309 × Voff(rms).
This compared to Vop = 3 × Voff(rms) when 1⁄3 bias is used.
1997 Jul 03
19
Philips Semiconductors
Product specification
8-bit microcontrollers with LCD-driver
6.7.4
6.7.4.1
P83C434; P83C834
LCD DRIVE MODE WAVEFORMS
Static drive mode
The static LCD drive mode is used when a single backplane is provided in the LCD. Backplane and segment drive
waveforms are shown in Fig.12.
Tframe
handbook, full pagewidth
LCD elements
VDD(P)
BP0
VSS
state 1
(on)
VDD(P)
state 2
(off)
Sn
VSS
VDD(P)
Sn+1
VSS
(a) waveforms at driver
Vop
state 1
0
−Vop
V state1(t) = V S (t) – V BP0(t)
n
Vop
V on(rms) = V op
state 2
V state2(t) = V S
0
n+1
V off(rms) = 0 V
−Vop
(b) resultant waveforms
at LCD element
MGG014
Fig.12 Static drive mode waveforms (Vop = VDD(P) − VSS).
1997 Jul 03
20
(t) – V BP0(t)
Philips Semiconductors
Product specification
8-bit microcontrollers with LCD-driver
6.7.4.2
P83C434; P83C834
1 : 2 multiplex drive mode
When two backplanes are provided in the LCD, the 1 : 2 multiplex mode applies. The P83C434; P83C834 allows use of
1⁄ or 1⁄ bias in this mode as shown in Figs 13 and 14.
2
3
Tframe
full pagewidth
VDD(P)
BP0
LCD elements
(VDD(P)+VSS)/2
VSS
state 1
VDD(P)
BP1
state 2
(VDD(P)+VSS)/2
VSS
VDD(P)
Sn
VSS
VDD(P)
Sn+1
VSS
(a) waveforms at driver
Vop
Vop/2
state 1
0
−Vop/2
V state1(t) = V S (t) – V BP0(t)
−Vop
V on(rms) = 0.791V op
n
Vop
V state2(t) = V S (t) – V BP0(t)
n
Vop/2
state 2
V off(rms) = 0.354V op
0
−Vop/2
−Vop
(b) resultant waveforms
at LCD element
MGG015
Fig.13 Waveforms for the 1 : 2 multiplex mode with 1⁄2 bias (Vop = VDD(P) − VSS).
1997 Jul 03
21
Philips Semiconductors
Product specification
8-bit microcontrollers with LCD-driver
P83C434; P83C834
Tframe
agewidth
BP0
VDD(P)
VSS+2Vop/3
BP1
VDD(P)
VSS+2Vop/3
LCD elements
VSS+Vop/3
VSS
state 1
state 2
VSS+Vop/3
VSS
Sn
VDD(P)
VSS+2Vop/3
VSS+Vop/3
VSS
Sn+1
VDD(P)
VSS+2Vop/3
VSS+Vop/3
VSS
(a) waveforms at driver
state 1
state 2
Vop
2Vop/3
Vop/3
0
−Vop/3
−2Vop/3
−Vop
Vop
2Vop/3
Vop/3
0
−Vop/3
−2Vop/3
−Vop
V state1(t) = V S (t) – V BP0(t)
n
V on(rms) = 0.745V op
V state2(t) = V S (t) – V BP0(t)
n
V off(rms) = 0.333V op
(b) resultant waveforms
at LCD element
MGG016
Fig.14 Waveforms for the 1 : 2 multiplex mode with 1⁄3 bias (Vop = VDD(P) − VSS).
1997 Jul 03
22
Philips Semiconductors
Product specification
8-bit microcontrollers with LCD-driver
6.7.4.3
P83C434; P83C834
1 : 3 multiplex drive mode
When three backplanes are provided in the LCD, the 1 : 3 multiplex mode applies, as shown in Fig.15.
Tframe
book, full pagewidth
VDD(P)
LCD elements
VSS+2Vop/3
VSS+Vop/3
VSS
BP0
state 1
VDD(P)
BP2/S23
VDD(P)
VSS+2Vop/3
VSS+Vop/3
VSS
Sn
VDD(P)
VSS+2Vop/3
VSS+Vop/3
VSS
Sn+1
Sn+2
state 2
VSS+2Vop/3
VSS+Vop/3
VSS
BP1
VDD(P)
VSS+2Vop/3
VSS+Vop/3
VSS
VDD(P)
VSS+2Vop/3
VSS+Vop/3
VSS
(a) waveforms at driver
Vop
2Vop/3
Vop/3
state 1
0
−Vop/3
−2Vop/3
−Vop
V state1(t) = V S (t) – V BP0(t)
n
Vop
2Vop/3
Vop/3
state 2
0
−Vop/3
−2Vop/3
−Vop
V on(rms) = 0.638V op
V state2(t) = V S (t) – V BP0(t)
n
V off(rms) = 0.333V op
(b) resultant waveforms
at LCD element
MGG017
Fig.15 Waveforms for the 1 : 3 multiplex drive mode (Vop = VDD(P) − VSS).
1997 Jul 03
23
Philips Semiconductors
Product specification
8-bit microcontrollers with LCD-driver
6.7.4.4
P83C434; P83C834
1 : 4 multiplex drive mode
When four backplanes are provided in the LCD, the 1 : 4 multiplex mode applies, as shown in Fig.16.
handbook, full pagewidth
VDD(P)
BP0
Tframe
LCD elements
VSS+2Vop/3
VSS+Vop/3
VSS
state 1
VDD(P)
BP1
BP2/S23
BP3/S22
Sn
Sn+1
Sn+2
Sn+3
state 2
VSS+2Vop/3
VSS+Vop/3
VSS
VDD(P)
VSS+2Vop/3
VSS+Vop/3
VSS
VDD(P)
VSS+2Vop/3
VSS+Vop/3
VSS
VDD(P)
VSS+2Vop/3
VSS+Vop/3
VSS
VDD(P)
VSS+2Vop/3
VSS+Vop/3
VSS
VDD(P)
VSS+2Vop/3
VSS+Vop/3
VSS
VDD(P)
VSS+2Vop/3
VSS+Vop/3
VSS
(a) waveforms at driver
Vop
2Vop/3
Vop/3
state 1
0
−Vop/3
−2Vop/3
−Vop
Vop
2Vop/3
Vop/3
state 2
0
−Vop/3
−2Vop/3
−Vop
V state1(t) = V S (t) – V BP0(t)
n
V on(rms) = 0.577V op
V state2(t) = V S (t) – V BP0(t)
n
V off(rms) = 0.333V op
(b) resultant waveforms
at LCD element
MGG018
Fig.16 Waveforms for the 1 : 4 multiplex drive mode (Vop = VDD(P) − VSS).
1997 Jul 03
24
Philips Semiconductors
Product specification
8-bit microcontrollers with LCD-driver
6.7.5
P83C434; P83C834
If less than 4 backplane outputs are required then the
unused backplane driver outputs should be left open.
LCD SEGMENT DRIVER OUTPUTS
The LCD drive section includes 24 segment outputs
(S00 to S23) which should be connected directly to the
LCD. The segment data bits are multiplexed to the outputs
in accordance with the backplane signals. If less than the
24 segment outputs are required then the unused driver
outputs should be left open.
There is a one-to-one relationship between the LCD
segment register bits and the segment outputs.
A segment register bit which is set to:
6.7.6
• Logic 1 indicates the ‘ON’ state of the corresponding
LCD segment.
6.7.7
BACKPLANE OUTPUTS
LCD SEGMENT DISPLAY REGISTERS
• Logic 0 indicates the ‘OFF’ state of the corresponding
LCD segment.
The LCD drive sections includes 4 backplane outputs
(BP0, BP1, S23/BP2 and S22/BP3) which should be
connected directly to the LCD. These backplane output
signals are generated in accordance with the selected
LCD drive mode.
Table 23 shows the display register bit map.
Table 23 Display register bit map
REGISTER
ADDRESS
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
S06
S05
S04
S03
S02
S01
S00
Segments corresponding to backplane BP0
LCD0
9AH
S07
LCD1
9BH
S15
S14
S13
S12
S11
S10
S09
S08
LCD2
9CH
S23
S22
S21
S20
S19
S18
S17
S16
Segments corresponding to backplane BP1
LCD3
9DH
S07
S06
S05
S04
S03
S02
S01
S00
LCD4
9EH
S15
S14
S13
S12
S11
S10
S09
S08
LCD5
9FH
S23
S22
S21
S20
S19
S18
S17
S16
Segments corresponding to backplane S23/BP2
LCD6
BAH
S07
S06
S05
S04
S03
S02
S01
S00
LCD7
BBH
S15
S14
S13
S12
S11
S10
S09
S08
BCH
−(1)
S22
S21
S20
S19
S18
S17
S16
S05
S04
S03
S02
S01
S00
LCD8
Segments corresponding to backplane S22/BP3
LCD9
BDH
S07
S06
LCD10
BEH
S15
S14
S13
S12
S11
S10
S09
S08
LCD11
BFH
−(1)
−(1)
S21
S20
S19
S18
S17
S16
Note
1. These bits are not connected to a segment and can be used for other purposes.
1997 Jul 03
25
Philips Semiconductors
Product specification
8-bit microcontrollers with LCD-driver
P83C434; P83C834
7 LIMITING VALUES
In accordance with the Absolute Maximum Rating System (IEC 134).
SYMBOL
PARAMETER
MIN.
MAX.
UNIT
VDD
supply voltage; note 1
3.3
5.5
V
VI
input voltage (all inputs)
−0.5
VDD + 0.5
V
Isource(max)
total maximum source current for all port lines
−
25
mA
Isink(max)
total maximum sink current for all port lines
−
25
mA
Ptot
total power dissipation
−
100
mW
Tstg
storage temperature
−60
+150
°C
Tamb
operating ambient temperature (for all devices)
−40
+85
°C
Note
1. VDD represents both VDD(P) and VDD(C).
8
HANDLING
Inputs and outputs are protected against electrostatic discharge in normal handling. However, to be totally safe, it is
desirable to take normal precautions appropriate to handling MOS devices (see “Handling MOS devices” ).
9 DC CHARACTERISTICS
VDD = 3.3 to 5.5 V; VSS = 0 V; Tamb = −45 to +85 °C; all voltages with respect to VSS unless otherwise specified.
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
Supply
VDD
normal operating supply voltage;
note 1
IDD
operating supply current
3.3
−
5.5
V
fosc = 12 MHz
−
15
22
mA
fosc = 5 MHz
−
7.5
10
mA
fosc = 1 MHz
−
1.6
2.5
mA
fosc = 12 MHz
−
2.1
3.0
mA
fosc = 5 MHz
−
0.9
1.4
mA
fosc = 1 MHz
−
205
300
µA
supply current in Power-down
mode
all functions down
−
18
50
µA
RINP
input resistance RESET
VDD = 3.3 to 5.5 V
20
60
220
kΩ
IL
leakage current; RESET pin
VDD = 5 V
−
−
10
µA
0.3VDD
V
IDD(ID)
IDD(PD)
supply current in Idle mode
Inputs
PORTS P0, P2 AND RESET
VIL
LOW level input voltage
VSS − 0.5 −
VIH
HIGH level input voltage
0.7VDD
1997 Jul 03
26
−
VDD + 0.5 V
Philips Semiconductors
Product specification
8-bit microcontrollers with LCD-driver
SYMBOL
PARAMETER
P83C434; P83C834
CONDITIONS
MIN.
TYP.
MAX.
UNIT
PORTS P0 AND P2
IIL
IIT
VI = 0.4 V; VDD = 5 V
−10
−40
−100
µA
VI = 0.4 V; VDD = 3.3 V
−
−12
−50
µA
VI = 0.5VDD; VDD = 5 V
−
−
−1000
µA
−
−
−500
µA
VO ≤ 0.4 V; VDD = 5 V
8
13
−
mA
VO ≤ 0.4 V; VDD = 3.3 V
5
10
−
mA
VO ≤ 1.0 V; VDD = 5 V
20
25
−
mA
strong pull-up during 2 clock
cycles
VO = VDD − 0.4 V; VDD = 5 V
6
9
−
mA
VO = VDD − 0.4 V; VDD = 3.3 V 4
6
−
mA
weak pull-up
VO = VDD − 0.4 V; VDD = 5 V
30
40
−
µA
VO = VDD − 0.4 V; VDD = 3.3 V 15
25
−
µA
input current Ports P0 and P2
input transition current Ports P0
and P2
Outputs: Ports P0, P2
IOL
IOH
LOW level output sink current
HIGH level pull-up output source
current
Note
1. VDD represents both VDD(P) and VDD(C).
10 LCD DRIVER CHARACTERISTICS
VDD = 3.3 to 5.5 V; VSS = 0 V; Tamb = −45 to +85 °C; all voltages with respect to VSS unless otherwise specified.
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
Supply
VDD(P)
operating supply voltage;
periphery and LCD part
VS
DC voltage component;
all backplane and segment drivers
note 1
3.3
−
VDD
V
−
−
100
mV
LCD driver outputs
RBP
output impedance
BP0, BP1, S23/BP2 and S22/BP3
VDD(P) = 5 V; IBP = 100 µA;
outputs measured one at a
time
50
−
200
kΩ
RS
output impedance
S0 to S21, S22/BP3 and S23/BP2
VDD(P) = 5 V; IS = 100 µA;
outputs measured one at a
time
50
−
200
kΩ
fLCD
LCD scan frequency
ratio: 1 : 1, 1 : 2, 1 : 4; note 2
−
64
−
Hz
ratio: 1 : 3; note 2
−
85
−
Hz
Notes
1. VDD(P) > 3 V for 1⁄3 bias.
2. Oscillator frequency = 32 kHz.
1997 Jul 03
27
Philips Semiconductors
Product specification
8-bit microcontrollers with LCD-driver
P83C434; P83C834
11 AC CHARACTERISTICS
VDD = 5 V; Tamb = −45 to +85 °C.
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
System (CPU) clock
system clock
fclk
1.0
−
12.0
MHz
16
−
40
kHz
32 kHz LCD oscillator
fxtal
crystal frequency
11.1
Characteristic curves
MBE321
MBE322
25
25
(1)
I OL
(mA)
I OH
(mA)
20
20
(2)
15
15
(1)
(3)
(2)
10
10
(3)
5
5
0
0
2
3
4
5
VDD (V)
2
6
3
4
5
VDD (V)
6
(3) Tamb = 85 °C.
Port 0 (P0.0 to P0.7) and Port 2 (P2.0 to P2.3); VO = VDD − 0.4 V.
(1) Tamb = −40 °C.
(2) Tamb = 25 °C.
(3) Tamb = 85 °C.
Fig.17 Typical LOW level output sink current as a
function of the supply voltage.
Fig.18 Typical HIGH level pull-up output source
current as a function of the supply voltage.
Port 0 (P0.0 to P0.7) and Port 2 (P2.0 to P2.3); VO = 0.4 V.
(1) Tamb = −40 °C.
(2) Tamb = 25 °C.
1997 Jul 03
28
Philips Semiconductors
Product specification
8-bit microcontrollers with LCD-driver
P83C434; P83C834
The advantage of the TEA5757 is that it works
independently from the microcontroller, e.g. once tuned to
a station, the microcontroller could be removed and the
tuner stays tuned.
12 APPLICATION INFORMATION
Figure 19 shows a typical portable/personal radio system
application which uses the device in conjunction with the
Self Tuned Radio (STR) TEA5757. This application
provides the following functions:
The system is designed such that the microcontroller is
switched to Power-down mode when no actions are
required; this increases the lifetime of the batteries.
• Scanning the keypad
• Transfer of commands and information to and from the
rest of the radio system
The microcontroller is activated by an interrupt, e.g. when
a key on the keyboard is pressed, or by the 1 second timer
(updating the real-time clock function). After the
appropriate actions are taken the microcontroller will enter
the Power-down mode again.
• Display of information on a LCD
• Storage of preset frequencies
• Real Time Clock (not always required).
Control between the TEA5757 and the microcontroller is
performed by a 4 line interface bus.
handbook, full pagewidth
TUNER
F/E
L
IF AMP/DET.
MPX
R
TEA5757H
SYNTH.
L
HEADPHONE
AMPLIFIER
TDA8542(T),
TDA7050(T)
or
TDA1308T
R
volume
MICROCONTROLLER
P83Cx34
LCD DISPLAY
KEYPAD
MSB622
Fig.19 Application diagram with the STR (TEA5757).
1997 Jul 03
29
Philips Semiconductors
Product specification
8-bit microcontrollers with LCD-driver
P83C434; P83C834
13 PACKAGE OUTLINES
seating plane
SDIP42: plastic shrink dual in-line package; 42 leads (600 mil)
SOT270-1
ME
D
A2
L
A
A1
c
e
Z
b1
(e 1)
w M
MH
b
22
42
pin 1 index
E
1
21
0
5
10 mm
scale
DIMENSIONS (mm are the original dimensions)
UNIT
A
max.
A1
min.
A2
max.
b
b1
c
D (1)
E (1)
e
e1
L
ME
MH
w
Z (1)
max.
mm
5.08
0.51
4.0
1.3
0.8
0.53
0.40
0.32
0.23
38.9
38.4
14.0
13.7
1.778
15.24
3.2
2.9
15.80
15.24
17.15
15.90
0.18
1.73
Note
1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.
OUTLINE
VERSION
REFERENCES
IEC
JEDEC
EIAJ
ISSUE DATE
90-02-13
95-02-04
SOT270-1
1997 Jul 03
EUROPEAN
PROJECTION
30
Philips Semiconductors
Product specification
8-bit microcontrollers with LCD-driver
P83C434; P83C834
QFP44: plastic quad flat package; 44 leads (lead length 1.3 mm); body 10 x 10 x 1.75 mm
SOT307-2
c
y
X
A
33
23
34
22
ZE
e
Q
E HE
A A2
wM
(A 3)
A1
θ
bp
Lp
pin 1 index
L
12
44
1
detail X
11
wM
bp
e
ZD
v M A
D
B
HD
v M B
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
UNIT
A
max.
A1
A2
A3
bp
c
D (1)
E (1)
e
HD
HE
L
Lp
Q
v
w
y
mm
2.10
0.25
0.05
1.85
1.65
0.25
0.40
0.20
0.25
0.14
10.1
9.9
10.1
9.9
0.8
12.9
12.3
12.9
12.3
1.3
0.95
0.55
0.85
0.75
0.15
0.15
0.1
Z D (1) Z E (1)
1.2
0.8
1.2
0.8
θ
Note
1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.
OUTLINE
VERSION
REFERENCES
IEC
JEDEC
EIAJ
ISSUE DATE
92-11-17
95-02-04
SOT307-2
1997 Jul 03
EUROPEAN
PROJECTION
31
o
10
0o
Philips Semiconductors
Product specification
8-bit microcontrollers with LCD-driver
Reflow soldering requires solder paste (a suspension of
fine solder particles, flux and binding agent) to be applied
to the printed-circuit board by screen printing, stencilling or
pressure-syringe dispensing before package placement.
14 SOLDERING
14.1
Introduction
There is no soldering method that is ideal for all IC
packages. Wave soldering is often preferred when
through-hole and surface mounted components are mixed
on one printed-circuit board. However, wave soldering is
not always suitable for surface mounted ICs, or for
printed-circuits with high population densities. In these
situations reflow soldering is often used.
Several techniques exist for reflowing; for example,
thermal conduction by heated belt. Dwell times vary from
50 to 300 seconds depending on heating method. Typical
reflow temperatures range from 215 to 250 °C.
Preheating is necessary to dry the paste and evaporate
the binding agent. Preheat for 45 minutes at 45 °C.
This text gives a very brief insight to a complex technology.
A more in-depth account of soldering ICs can be found in
our “IC Package Databook” (order code 9398 652 90011).
14.2
14.2.1
P83C434; P83C834
14.3.2
WAVE SOLDERING
Wave soldering is not recommended for QFP packages.
This is because of the likelihood of solder bridging due to
closely-spaced leads and the possibility of incomplete
solder penetration in multi-lead devices.
SDIP
SOLDERING BY DIPPING OR BY WAVE
The maximum permissible temperature of the solder is
260 °C; solder at this temperature must not be in contact
with the joint for more than 5 seconds. The total contact
time of successive solder waves must not exceed
5 seconds.
If wave soldering cannot be avoided, the following
conditions must be observed:
The device may be mounted up to the seating plane, but
the temperature of the plastic body must not exceed the
specified maximum storage temperature (Tstg max). If the
printed-circuit board has been pre-heated, forced cooling
may be necessary immediately after soldering to keep the
temperature within the permissible limit.
• The footprint must be at an angle of 45° to the board
direction and must incorporate solder thieves
downstream and at the side corners.
14.2.2
• A double-wave (a turbulent wave with high upward
pressure followed by a smooth laminar wave)
soldering technique should be used.
Even with these conditions, do not consider wave
soldering the following packages: QFP52 (SOT379-1),
QFP100 (SOT317-1), QFP100 (SOT317-2),
QFP100 (SOT382-1) or QFP160 (SOT322-1).
REPAIRING SOLDERED JOINTS
During placement and before soldering, the package must
be fixed with a droplet of adhesive. The adhesive can be
applied by screen printing, pin transfer or syringe
dispensing. The package can be soldered after the
adhesive is cured. Maximum permissible solder
temperature is 260 °C, and maximum duration of package
immersion in solder is 10 seconds, if cooled to less than
150 °C within 6 seconds. Typical dwell time is 4 seconds
at 250 °C.
Apply a low voltage soldering iron (less than 24 V) to the
lead(s) of the package, below the seating plane or not
more than 2 mm above it. If the temperature of the
soldering iron bit is less than 300 °C it may remain in
contact for up to 10 seconds. If the bit temperature is
between 300 and 400 °C, contact may be up to 5 seconds.
14.3
14.3.1
QFP
REFLOW SOLDERING
A mildly-activated flux will eliminate the need for removal
of corrosive residues in most applications.
Reflow soldering techniques are suitable for all QFP
packages.
14.3.3
The choice of heating method may be influenced by larger
plastic QFP packages (44 leads, or more). If infrared or
vapour phase heating is used and the large packages are
not absolutely dry (less than 0.1% moisture content by
weight), vaporization of the small amount of moisture in
them can cause cracking of the plastic body. For more
information, refer to the Drypack chapter in our “Quality
Reference Handbook” (order code 9397 750 00192).
1997 Jul 03
REPAIRING SOLDERED JOINTS
Fix the component by first soldering two diagonallyopposite end leads. Use only a low voltage soldering iron
(less than 24 V) applied to the flat part of the lead. Contact
time must be limited to 10 seconds at up to 300 °C. When
using a dedicated tool, all other leads can be soldered in
one operation within 2 to 5 seconds between
270 and 320 °C.
32
Philips Semiconductors
Product specification
8-bit microcontrollers with LCD-driver
P83C434; P83C834
15 DEFINITIONS
Data sheet status
Objective specification
This data sheet contains target or goal specifications for product development.
Preliminary specification
This data sheet contains preliminary data; supplementary data may be published later.
Product specification
This data sheet contains final product specifications.
Limiting values
Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or
more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation
of the device at these or at any other conditions above those given in the Characteristics sections of the specification
is not implied. Exposure to limiting values for extended periods may affect device reliability.
Application information
Where application information is given, it is advisory and does not form part of the specification.
16 LIFE SUPPORT APPLICATIONS
These products are not designed for use in life support appliances, devices, or systems where malfunction of these
products can reasonably be expected to result in personal injury. Philips customers using or selling these products for
use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such
improper use or sale.
1997 Jul 03
33
Philips Semiconductors
Product specification
8-bit microcontrollers with LCD-driver
NOTES
1997 Jul 03
34
P83C434; P83C834
Philips Semiconductors
Product specification
8-bit microcontrollers with LCD-driver
NOTES
1997 Jul 03
35
P83C434; P83C834
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Internet: http://www.semiconductors.philips.com
© Philips Electronics N.V. 1997
SCA54
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner.
The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed
without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license
under patent- or other industrial or intellectual property rights.
Printed in The Netherlands
457047/00/03/pp36
Date of release: 1997 Jul 03
Document order number:
9397 750 02549