INTEGRATED CIRCUITS DATA SHEET For a complete data sheet, please also download: • The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications • The IC06 74HC/HCT/HCU/HCMOS Logic Package Information • The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines 74HC/HCT7404 5-Bit x 64-word FIFO register; 3-state Product specification Supersedes data of October 1990 File under Integrated Circuits, IC06 September 1993 Philips Semiconductors Product specification 5-Bit x 64-word FIFO register; 3-state 74HC/HCT7404 FEATURES GENERAL DESCRIPTION • Synchronous or asynchronous operation The 74HC/HCT7404 are high-speed Si-gate CMOS devices specified in compliance with JEDEC standard no.7A. • 3-state outputs • 30 MHz (typical) shift-in and shift-out rates The “7404” is an expandable, First-In First-Out (FIFO) memory organized as 64 words by 5 bits. A guaranteed 15 MHz data-rate makes it ideal for high-speed applications. A higher data-rate can be obtained in applications where the status flags are not used (burst-mode). • Readily expandable in word and bit dimensions • Pinning arranged for easy board layout: input pins directly opposite output pins • Output capability: driver (8 mA) • ICC category: LSI. With separate controls for shift-in (SI) and shift-out (SO), reading and writing operations are completely independent, allowing synchronous and asynchronous data transfers. Additional controls include a master-reset input (MR), an output enable input (OE) and flags. The data-in-ready (DIR) and data-out-ready (DOR) flags indicate the status of the device. APPLICATIONS • High-speed disc or tape controller • Communications buffer. QUICK REFERENCE DATA GND = 0 V; Tamb = 25 °C; tr = tf = 6 ns. TYP. SYMBOL PARAMETER CONDITIONS UNIT HC CL = 15 pF; VCC = 5 V HCT tPHL/tPLH propagation delay SO, SI to DIR and DOR 15 17 ns fmax maximum clock frequency 30 30 MHz CI input capacitance 3.5 3.5 pF CPD power dissipation capacitance per package 475 490 pF note 1 Note 1. For HC the condition is VI = GND to VCC. For HCT the condition is VI = GND to VCC −1.5 V. ORDERING INFORMATION EXTENDED TYPE NUMBER PACKAGE PINS PIN POSITION MATERIAL CODE 74HC/HCT7404N 18 DIL plastic SOT102 74HC/HCT7404D 20 SO20 plastic SOT163A September 1993 2 Philips Semiconductors Product specification 5-Bit x 64-word FIFO register; 3-state 74HC/HCT7404 PINNING (SOT102) SYMBOL PINNING (SOT163A) PIN DESCRIPTION SYMBOL PIN DESCRIPTION OE 1 output enable input (active LOW) OE 1 output enable input (active LOW) DIR 2 data-in-ready output DIR 2 data-in-ready output 3 shift-in input (active HIGH) SI 3 shift-in input (active HIGH) n.c. 4 not connected SI DO to D4 4, 5, 6, 7, 8 parallel data inputs GND 9 ground D0 to D4 MR 10 asynchronous master-reset input (active LOW) GND 10 ground MR 11 asynchronous master-reset input (active LOW) Q4 to Q0 11, 12, 13, 14, 15 5, 6, 7, 8, 9 parallel data inputs data outputs Q4 to Q0 12, 13, 14, 15, 16 data outputs DOR 16 data-out-ready output SO 17 shift-out input (active LOW) n.c. 17 not connected VCC 18 positive supply voltage DOR 18 data-out ready output n.c. 19 not connected VCC 20 positive supply voltage handbook, halfpage handbook, halfpage OE 1 18 VCC DIR 2 17 SO SI 3 16 DOR D0 4 15 Q0 D1 5 D2 6 13 Q2 D3 7 12 Q3 D4 8 11 Q4 GND 9 10 MR 7404 14 Q1 OE 1 20 VCC DIR 2 19 SO SI 3 18 DOR n.c. 4 17 n.c. D0 5 D1 6 15 Q1 D2 7 14 Q2 D3 8 13 Q3 D4 9 12 Q4 GND 10 11 MR 16 Q0 7404 MGA670 MGA671 Fig.1 Pin configuration (SOT102). September 1993 Fig.2 Pin configuration (SOT163). 3 Philips Semiconductors Product specification 5-Bit x 64-word FIFO register; 3-state 74HC/HCT7404 1 (1) handbook, halfpage handbook, halfpage (1) 1 OE D0 D1 Q0 Q1 15 (16) (6) 5 (7) 6 D2 Q2 13 (14) (8) 7 D3 Q3 12 (13) (9) 8 D4 Q4 11 (12) (3) 3 SI DOR 16 (18) (5) 4 (19) 17 14 (15) (5) 4 MR CTR 1 ( /C2) CT < 64 CT = 0 CT > 0 5 2 (2) 16 (18) G1 G5 4 2D 15 (16) (6) 5 14 (15) (7) 6 13 (14) (8) 7 12 (13) 11 (12) (9) 8 MGA673 10 (11) [IR] 3 [OR] 6 5Z6 2 (2) DIR SO (3) 3 (11) 10 (19) 17 FIFO 64 x 5 EN4 1Z3 MGA675 Pin numbers between parentheses refer to the SO package. Pin numbers between parentheses refer to the SO package. Fig.3 Logic symbol. Fig.4 IEC logic symbol. handbook, full pagewidth (5) 4 D0 (6) 5 D1 Q 0 15 (16) (7) 6 D2 (8) 7 D3 Q 2 13 (14) (9) 8 D4 Q 1 14 (15) MAIN FIFO REGISTER 62 x 5 BITS INPUT STAGE 1 x 5 BITS (11) 10 MR OUTPUT STAGE 1 x 5 BITS Q 4 11 (12) CONTROL LOGIC DIR SI 2 (2) 3 (3) DOR SO 16 (18) 17 (19) Pin numbers between parentheses refer to the SO package. Fig.5 Functional diagram. September 1993 Q 3 12 (13) OE 4 OE 1 (1) MGA680 September 1993 5 FS Q CL position 1 5 LATCHES CL (2) S R FF1 R Q Q CL position 2 5 LATCHES CL (2) S R FF2 R Q Q CL position 3 to 63 5 LATCHES CL Fig.6 Logic diagram. Q FF3 R to FF63 S Q R 61 x CL position 64 5 LATCHES CL S FB (1) MSB117 3-STATE OUTPUT BUFFER R Q Q S (2) R FF64 R FP Q Q Q4 Q3 Q1 Q0 OE SO DOR 5-Bit x 64-word FIFO register; 3-state (See control flip-flops) LOW on S input of flip-flops FS, FB and FP will set Q output to HIGH independent of state on R input. LOW on R input of FF1 to FF64 will set Q output to LOW independent of state on S input. D4 D3 D1 S R (1) full pagewidth D0 DIR SI MR S R R (1) Philips Semiconductors Product specification 74HC/HCT7404 Philips Semiconductors Product specification 5-Bit x 64-word FIFO register; 3-state FUNCTIONAL DESCRIPTION The DIR flag indicates the input stage status, either empty and ready to receive data (DIR = HIGH) or full and busy (DIR = LOW). When DIR and SI are HIGH, data present at D0 to D4 is shifted into the input stage; once complete DIR goes LOW. When SI is set LOW, data is automatically shifted to the output stage or to the last empty location. A FIFO which can receive data is indicated by DIR set HIGH. A DOR flag indicates the output stage status, either data available (DOR = HIGH) or busy (DOR = LOW). When SO and DOR are HIGH, data is available at the 74HC/HCT7404 outputs (Q0 to Q4). When SO is LOW new data may be shifted into the output stage, once complete DOR is set LOW. Expanded Format (see Fig.18) The DOR and DIR signals are used to allow the ‘7404’ to be cascaded. Both parallel and serial expansion is possible. Serial expansion is only possible with typical devices. Serial Expansion Serial expansion is accomplished by: • tying the data outputs of the first device to the data inputs of the second device • connecting the DOR pin of the first device to the SI pin of the second device • connecting the SO pin of the first device to the DIR pin of the second device. Parallel Expansion Parallel expansion is accomplished by logically ANDing the DOR and DIR signals to form a composite signal. DC CHARACTERISTICS FOR 74HC For the DC characteristics see “74HC/HCT/HCU/HCMOS Logic Family Specifications”. Output capability: parallel outputs, bus driver; serial output, standard ICC category: MSI Output capability: driver 8 mA ICC category: LSI Voltages are referenced to GND (ground = 0 V). DC CHARACTERISTICS FOR 74HC Tamb °C SYMBOL TEST CONDITION −40 to +85 MIN TYP MAX MIN −40 to +125 UNIT V CC (V) MAX MIN MAX +25 PARAMETER VI OTHER VOH HIGH level output voltage 3.98 5.48 4.32 5.81 − − 3.84 5.34 − − 3.70 5.20 − − V V 4.5 6 VIH or VIL IO = −8 mA IO = −10 mA VOL LOW level output voltage − − 0.15 0.15 0.26 0.26 − − 0.33 0.33 − − 0.4 0.4 V 4.5 6 VIH or VIL IO = 8 mA IO = 10 mA September 1993 6 V Philips Semiconductors Product specification 5-Bit x 64-word FIFO register; 3-state 74HC/HCT7404 AC CHARACTERISTICS FOR 74HC GND = 0 V; tr = tf = 6 ns; CL = 50 pF. Tamb °C SYMBOL +25 PARAMETER MIN TYP MAX TEST CONDITION −40 to +85 −40 to +125 MIN MIN MAX UNIT MAX VCC (V) WAVEFORMS tPHL/tPLH propagation delay MR to DIR, DOR − − − 69 25 20 210 42 36 − − − 265 53 45 − − − 315 63 54 ns ns ns 2.0 4.5 6.0 Fig.9 tPHL propagation delay MR to Qn − − − 52 19 15 160 32 27 − − − 200 40 34 − − − 240 48 41 ns ns ns 2.0 4.5 6.0 Fig.9 tPHL/tPLH propagation delay SI to DIR − − − 66 24 19 205 41 35 − − − 255 51 43 − − − 310 62 53 ns ns ns 2.0 4.5 6.0 Fig.7 tPHL/tPLH propagation delay SO to DOR − − − 94 34 27 290 58 49 − − − 365 73 62 − − − 435 87 74 ns ns ns 2.0 4.5 6.0 Fig.10 tPHL/tPLH propagation delay DOR to Qn − − − 11 4 3 35 7 6.0 − − − 45 9 8 − − − 55 11 9 ns ns ns 2.0 4.5 6.0 Fig.11 tPHL/tPLH propagation delay SO to Qn − − − 105 38 30 325 65 55 − − − 406 81 69 − − − 488 98 83 ns ns ns 2.0 4.5 6.0 Fig.15 tPLH propagation delay/ripple through delay SI to DOR − − − 2.2 0.8 0.6 7.0 1.4 1.2 − − − 8.8 1.8 1.5 − − − 10.5 2.1 1.8 µs µs µs 2.0 4.5 6.0 Fig.16 tPLH − propagation delay/bubble-up − − delay SO to DIR 2.8 1.0 0.8 9.0 1.8 1.5 − − − 11.2 2.2 1.9 − − − 13.5 2.7 2.3 µs µs µs 2.0 4.5 6.0 Fig.8 tPZH/tPZL 3-state output enable OE to Qn − − − 44 16 13 150 30 26 − − − 190 38 32 − − − 225 45 38 ns ns ns 2.0 4.5 6.0 Fig.17 tPHZ/tPLZ 3-state output disable OE to Qn − − − 50 18 14 150 30 26 − − − 190 38 33 − − − 225 45 38 ns ns ns 2.0 4.5 6.0 Fig.17 tTHL/tTLH output transition − time − − 14 5 4 60 12 10 − − − 75 15 13 − − − 90 18 15 ns ns ns 2.0 4.5 6.0 Fig.17 tW SI pulse width HIGH or LOW 35 7 6 11 4 3 − − − 45 9 8 − − − 55 11 9 − − − ns ns ns 2.0 4.5 6.0 Fig.7 tW SO pulse width HIGH or LOW 70 14 12 22 8 6 − − − 90 18 15 − − − 105 21 18 − − − ns ns ns 2.0 4.5 6.0 Fig.10 September 1993 7 Philips Semiconductors Product specification 5-Bit x 64-word FIFO register; 3-state 74HC/HCT7404 Tamb °C SYMBOL PARAMETER +25 MIN TYP MAX TEST CONDITION −40 to +85 −40 to +125 MIN MIN MAX UNIT MAX VCC (V) WAVEFORMS tW DIR pulse width 10 HIGH 5 4 41 15 12 130 26 22 8 4 3 165 33 28 8 4 3 195 39 33 ns ns ns 2.0 4.5 6.0 Fig.8 tW DOR pulse width HIGH 14 7 6 52 19 15 160 32 27 12 6 5 200 40 34 12 6 5 240 48 41 ns ns ns 2.0 4.5 6.0 Fig.11 tW MR pulse width LOW 120 24 20 39 14 11 − − − 150 30 26 − − − 180 36 31 − − − ns ns ns 2.0 4.5 6.0 Fig.9 trem removal time MR to SI 80 16 14 24 8 7 − − − 100 20 17 − − − 120 24 20 − − − ns ns ns 2.0 4.5 6.0 Fig.16 tsu set-up time Dn to SI −8 −4 −3 −36 −13 −10 − − − −6 −3 −3 − − − −6 −3 −3 − − − ns ns ns 2.0 4.5 6.0 Fig.14 th hold time Dn to SI 135 27 23 44 16 13 − − − 170 34 29 − − − 205 41 35 − − − ns ns ns 2.0 4.5 6.0 Fig.14 fmax maximum clock 3.6 pulse frequency 18 SI, SO burst 21 mode 9.9 30 36 − − − 2.8 14 16 − − − 2.4 12 14 − − − MHz MHz MHz 2.0 4.5 6.0 Fig.12 and Fig.13 fmax maximum clock 3.6 pulse frequency 18 21 SI, SO using flags 9.9 30 36 − − − 2.8 14 16 − − − 2.4 12 14 − − − MHz MHz MHz 2.0 4.5 6.0 Fig.7 and Fig.10 fmax maximum clock − pulse frequency − SI, SO − cascaded 7.6 23 27 − − − − − − − − − − − − − − − MHz MHz MHz 2.0 4.5 6.0 Fig.7 and Fig.10 September 1993 8 Philips Semiconductors Product specification 5-Bit x 64-word FIFO register; 3-state 74HC/HCT7404 DC CHARACTERISTICS FOR 74HCT For the DC characteristics see “74HC/HCT/HCU/HCMOS Logic Family Specifications”, except that VOH and VOL are not valid for driver output. They are replaced by the values given below. Output capability: driver 8 mA ICC category: LSI. Voltages are referenced to GND (ground = 0 V). DC CHARACTERISTICS FOR 74HCT Tamb °C SYMBOL TEST CONDITION MIN TYP MAX MIN −40 to +125 UNIT V CC (V) MAX MIN MAX PARAMETER −40 to +85 +25 VI OTHER VOH HIGH level output voltage 3.98 4.32 − 3.84 − 3.7 − V 4.5 VIH or VIL IO = −8 mA VOL LOW level output voltage − 0.15 0.26 − 0.33 − 0.40 V 4.5 VIH or VIL IO = 8 mA Note to HCT types The value of additional quiescent supply current (∆ICC) for a unit load of 1 is given in the family specifications. To determine ∆ICC per input, multiply this value by the unit load coefficient shown in the table below. UNIT LOAD COEFFICIENT INPUT UNIT LOAD COEFFICIENT OE 1 SI 1.5 Dn 0.75 MR 1.5 SO 1.5 September 1993 9 Philips Semiconductors Product specification 5-Bit x 64-word FIFO register; 3-state 74HC/HCT7404 AC CHARACTERISTICS FOR 74HCT GND = 0 V; tr = tf = 6 ns; CL = 50 pF. Tamb °C SYMBOL +25 PARAMETER MIN TYP MAX TEST CONDITION −40 to +85 −40 to +125 MIN MIN MAX UNIT MAX VCC (V) WAVEFORMS tPHL/tPLH propagation delay MR to DIR, DOR − 30 51 − 53 − 63 ns 4.5 Fig.9 tPHL propagation delay MR to Qn − 22 38 − 48 − 57 ns 4.5 Fig.9 tPHL/tPLH propagation delay SI to DIR − 25 43 − 54 − 65 ns 4.5 Fig.7 tPHL/tPLH propagation delay SO to DOR − 36 61 − 76 − 92 ns 4.5 Fig.10 tPHL/tPLH propagation delay SO to Qn − 42 72 − 90 − 108 ns 4.5 Fig.15 tPHL/tPLH propagation delay DOR to Qn − 7 12 − 15 − 18 ns 4.5 Fig.11 tPLH propagation delay/ripple through delay SI to DOR − 0.8 1.4 − 1.75 − 2.1 µs 4.5 Fig.11 tPLH propagation delay/bubbleup delay SO to DIR − 1 1.8 − 2.25 − 2.7 µs 4.5 Fig.8 tPZH/tPZL 3-state output enable OE to Qn − 16 30 − 38 − 45 ns 4.5 Fig.17 tPHZ/tPLZ 3-state output disable OE to Qn − 19 30 − 38 − 45 ns 4.5 Fig.17 tTHL/tTLH output transition time − 5 12 − 15 − 18 ns 4.5 Fig.17 tW SI pulse width HIGH or LOW 9 5 − 6 − 8 − ns 4.5 Fig.7 tW SO pulse width HIGH or LOW 14 8 − 18 − 21 − ns 4.5 Fig.10 tW DIR pulse width 5 HIGH 17 29 4 36 4 44 ns 4.5 Fig.8 September 1993 10 Philips Semiconductors Product specification 5-Bit x 64-word FIFO register; 3-state 74HC/HCT7404 Tamb °C SYMBOL PARAMETER +25 MIN TYP MAX TEST CONDITION −40 to +85 −40 to +125 MIN MIN MAX UNIT MAX VCC (V) WAVEFORMS tW DOR pulse width HIGH 7 21 36 6 45 6 54 ns 4.5 Fig.11 tW MR pulse width LOW 26 15 − 33 − 39 − ns 4.5 Fig.9 trem removal time MR to SI 18 10 − 23 − 27 − ns 4.5 Fig.16 tsu set-up time Dn to SI −5 −16 − −4 − −4 − ns 4.5 Fig.14 th hold time Dn to SI 30 18 − 38 − 45 − ns 45 Fig.14 fmax maximum clock pulse frequency SI, SO burst mode 18 30 − 14 − 12 − MHz 4.5 Fig.12 and Fig.13 fmax maximum clock pulse frequency SI, SO using flags 18 30 − 14 − 12 − MHz 4.5 Fig.7 and Fig.10 fmax maximum clock pulse frequency SI, SO cascaded − 23 − − − − − MHz 4.5 Fig.7 and Fig.10 September 1993 11 Philips Semiconductors Product specification 5-Bit x 64-word FIFO register; 3-state 74HC/HCT7404 AC WAVEFORMS Shifting in sequence FIFO empty to FIFO full 1st word 1/f max handbook, full pagewidth VM (1) 4 2 SI INPUT 2nd word 64th word VM (1) 6 tW t PHL t PLH 1 5 DIR OUTPUT 3 7 Dn INPUT MGA659 (1) HC : HCT : Fig.7 VM = 50%; VI = GND to VCC. VM = 1.3 V; VI = GND to 3 V. Waveforms showing the SI input to DIR output propagation delay, the SI pulse width and SI maximum pulse frequency. Notes to Fig.7 1. DIR initially HIGH; FIFO is prepared for valid data 2. SI set HIGH; data loaded into input stage 3. DIR goes LOW, input stage “busy” 4. SI set LOW; data from first location “ripple through” 5. DIR goes HIGH, status flag indicates FIFO prepared for additional data 6. Repeat process to load 2nd word through to 64th word into FIFO DIR remains LOW; with attempt to shift into full FIFO, no data transfer occurs. September 1993 12 Philips Semiconductors Product specification 5-Bit x 64-word FIFO register; 3-state 74HC/HCT7404 With FIFO full; SI held HIGH in anticipation of empty location handbook, full pagewidth 2 SO INPUT SI INPUT 1 VM (1) VM (1) t PLH 5 tW bubble - up delay VM (1) DIR OUTPUT 3 4 MGA660 (1) HC : HCT : VM = 50%; VI = GND to VCC. VM = 1.3 V; VI = GND to 3 V. Fig.8 Waveforms showing bubble-up delay, SO input to DIR output and DIR output pulse width. Notes to Fig.8 1. FIFO is initially full, shift-in is held HIGH 2. SO pulse; data in the output stage is unloaded, “bubble-up” process of empty location begins 3. DIR HIGH; when empty location reaches input stage, flag indicates FIFO is prepared for data input 4. DIR returns to LOW; data shift-in to empty location is complete, FIFO is full again 5. SI set LOW; necessary to complete shift-in process, DIR remains LOW, because FIFO is full. September 1993 13 Philips Semiconductors Product specification 5-Bit x 64-word FIFO register; 3-state 74HC/HCT7404 Master reset applied with FIFO full handbook, halfpage MR INPUT 2 VM (1) tW t PLH VM (1) 3 DIR OUTPUT 1 t PHL 4 DOR OUTPUT VM (1) t PHL Qn OUTPUT 5 MGA668 (1) HC : HCT : VM = 50%; VI = GND to VCC. VM = 1.3 V; VI = GND to 3 V. Fig.9 Waveforms showing the MR input to DIR, DOR and Qn output propagation delays and the MR pulse width. Notes to Fig.9 1. DIR LOW, output ready HIGH; assume FIFO is full 2. MR pulse LOW; clears FIFO 3. DIR goes HIGH; flag indicates input prepared for valid data 4. DOR goes LOW; flag indicates FIFO empty 5. Qn outputs go LOW (only last bit will be reset). September 1993 14 Philips Semiconductors Product specification 5-Bit x 64-word FIFO register; 3-state 1st SO pulse handbook, full pagewidth 74HC/HCT7404 2nd SO pulse 64th SO pulse 1/f max VM (1) 4 2 SO INPUT VM (1) 6 tW t PHL t PLH 1 5 VM (1) DOR OUTPUT 3 Qn OUTPUT 1st word 7 2nd word 64th word MGA661 (1) HC : HCT : VM = 50%; VI = GND to VCC. VM = 1.3 V; VI = GND to 3 V. Fig.10 Waveforms showing the SO input to DOR output propagation delay, the SO pulse widths and maximum pulse frequency. Notes to Fig.10 1. DOR HIGH; no data transfer in progress, valid data is present at output stage 2. SO set HIGH; results in DOR going LOW 3. DOR goes LOW; output stage “busy” 4. SO set LOW; data in the input stage is unloaded, and new data replaces it as empty location “bubbles-up” to input stage 5. DOR goes HIGH; transfer process completed, valid data present at output after the specified propagation delay 6. Repeat process to unload the 3rd through to the 64th word from FIFO. 7. DOR remains LOW; FIFO is empty. September 1993 15 Philips Semiconductors Product specification 5-Bit x 64-word FIFO register; 3-state 74HC/HCT7404 With FIFO empty; SO is held HIGH in anticipation handbook, full pagewidth 2 SI INPUT SO INPUT 1 VM (1) VM (1) 6 t PLH ripple through delay 3 DOR OUTPUT tW VM (1) 5 t PHL t PLH 4 Qn OUTPUT MGA669 (1) HC : HCT : VM = 50%; VI = GND to VCC. VM = 1.3 V; VI = GND to 3 V. Fig.11 Waveforms showing ripple through delay SI input to DOR output, DOR output pulse width and propagation delay from the DOR pulse to the Qn output. Notes to Fig.11 1. FIFO is initially empty, SO is held HIGH 2. SI pulse; loads data into FIFO and initiates ripple through process 3. DOR flag signals the arrival of valid data at the output stage 4. Output transition; data arrives at output stage after the specified propagation delay between the rising edge of the DOR pulse to the Qn output 5. DOR goes LOW; data shift-out is complete, FIFO is empty again 6. SO set LOW; necessary to complete shift-out process. DOR remains LOW, because FIFO is empty. September 1993 16 Philips Semiconductors Product specification 5-Bit x 64-word FIFO register; 3-state 74HC/HCT7404 Shift-in operation; high-speed burst mode 1/ f max handbook, full pagewidth tW SI INPUT VM (1) Dn INPUT DIR OUTPUT MGA662 (1) HC : HCT : VM = 50%; VI = GND to VCC. VM = 1.3 V; VI = GND to 3 V. Fig.12 Waveforms showing SI minimum pulse width and maximum pulse frequency, in high-speed shift-in burst mode. Note to Fig.12 In the high-speed mode, the burst-in rate is determined by the minimum shift-in HIGH and shift-in LOW specifications. The DIR status flag is a don't care condition, and a shift-in pulse can be applied regardless of the flag. A SI pulse which would overflow the storage capacity of the FIFO is ignored. September 1993 17 Philips Semiconductors Product specification 5-Bit x 64-word FIFO register; 3-state 74HC/HCT7404 Shift-out operation; high-speed burst mode 1/ f max handbook, full pagewidth tW SO INPUT VM (1) Qn OUTPUT DOR OUTPUT MGA663 (1) HC : HCT : VM = 50%; VI = GND to VCC. VM = 1.3 V; VI = GND to 3 V. Fig.13 Waveforms showing SO minimum pulse width and maximum pulse frequency, in high-speed shift-out burst mode. Note to Fig.13 In the high-speed mode, the burst-out rate is determined by the minimum shift-out HIGH and shift-out LOW specifications. The DOR flag is a don't care condition and an SO pulse can be applied without regard to the flag. September 1993 18 Philips Semiconductors Product specification 5-Bit x 64-word FIFO register; 3-state 74HC/HCT7404 handbook, full pagewidth Dn INPUT VM (1) t su t su th th VM (1) SI INPUT MGA657 (1) HC : HCT : VM = 50%; VI = GND to VCC. VM = 1.3 V; VI = GND to 3 V. The shaded areas indicate when the input is permitted to change for predictable output performance. Fig.14 Waveforms showing hold and set-up times for Dn input to SI input. handbook, full pagewidth SO INPUT VM (1) t PLH VM (1) Qn OUTPUT MGA664 (1) HC : HCT : t PHL t TLH t THL VM = 50%; VI = GND to VCC. VM = 1.3 V; VI = GND to 3 V. Fig.15 Waveforms showing SO input to Qn output propagation delays and output transition time. handbook, halfpage VM (1) MR INPUT t rem VM (1) SI INPUT (1) HC : HCT : MGA665 VM = 50%; VI = GND to VCC. VM = 1.3 V; VI = GND to 3 V. Fig.16 Waveform showing the MR input to SI input removal time. September 1993 19 Philips Semiconductors Product specification 5-Bit x 64-word FIFO register; 3-state tr handbook, full pagewidth 74HC/HCT7404 tf 90 % VM (1) OE INPUT 10 % t PLZ Qn OUTPUT LOW - to - OFF OFF - to - LOW t PZL VM (1) 10 % t PHZ 90 % Q n OUTPUT HIGH - to - OFF OFF - to - HIGH MGA656 (1) HC : HCT : t PZH VM (1) outputs enabled outputs disabled outputs enabled VM = 50%; VI = GND to VCC. VM = 1.3 V; VI = GND to 3 V. Fig.17 Waveforms showing the 3-state enable and disable times for input OE. September 1993 20 Philips Semiconductors Product specification 5-Bit x 64-word FIFO register; 3-state 74HC/HCT7404 APPLICATION INFORMATION handbook, full pagewidth OE DOR SI SI OE DOR SI OE DOR D0 Q0 D0 Q0 D1 Q1 D1 Q1 D2 Q2 D2 D3 Q3 D3 D4 Q4 D4 7404 DIR MR SO 7404 Q2 Q3 Q4 DIR MR SO 10-bit data 10-bit data SI OE DOR SI OE DOR D0 Q0 D0 Q0 D1 Q1 D1 Q1 D2 Q2 D2 D3 Q3 D3 D4 Q4 D4 7404 DIR MR SO 7404 DIR MR Q2 Q3 Q4 SO DIR SO MR MGA686 Fig.18 Expanded FIFO (parallel and serial) for increased word length; 10 bits wide × 64 n-bits. September 1993 21 Philips Semiconductors Product specification 5-Bit x 64-word FIFO register; 3-state 74HC/HCT7404 handbook, full pagewidth DATA INPUT 5 COMPOSITE DIR FLAG Dn Qn DIR 5 DATA OUTPUT COMPOSITE DOR FLAG DOR 7404 SI MR SI SO SO MR OE OE DIR DOR SI SO 7404 DATA INPUT 5 MR OE Dn Qn 5 DATA OUTPUT MGA681 Fig.19 Expanded FIFO for increased word length; 64 words × 10 bits. Note to Fig.19 The ”7404” is easily expanded to increase word length. Composite DIR and DOR flags are formed with the addition of an AND gate. The basic operation and timing are identical to a single FIFO, with the exception of an added gate delay on the flags. September 1993 22 Philips Semiconductors Product specification 5-Bit x 64-word FIFO register; 3-state 74HC/HCT7404 handbook, full pagewidth 5 Dn Qn DIR Q DOR 7404 D 74 composite DIR 5 CP SI SO MR OE D Q 74 Q Q Q D D DIR CP Q R composite DOR CP SI DOR SI Q CP SO SO MR OE OE Dn Qn R Q 7404 MR 5 5 MGA685 Fig.20 Expanded FIFO for increased word length. Note to Fig.20 This circuit is only required if the SI input is constantly held HIGH, when the FIFO is empty and the automatic shift-in cycles are started or if SO output is constantly held HIGH, when the FIFO is full and the automatic shift-out cycles are started (see Fig.8 and Fig.10). Expanded format Figure 21 shows two cascaded FIFOs providing a capacity of 128 words x 5 bits. Figure 22 shows the signals on the nodes of both FIFOs after the application of a SI pulse, when both FIFOs are initially empty. After a ripple through delay, data arrives at the output of FIFOA. Due to SOA being HIGH, a DORA pulse is generated. The requirements of SIB and DnB are satisfied by the DORA pulse width and the timing between the rising edge of DORA and QnA. After a second ripple through delay, data arrives at the output of FIFOB. Figure 23 shows the signals on the nodes of both FIFOs after the application of a SOB pulse, when both FIFOs are initially full. After a bubble-up delay a DIRB pulse is generated, which acts as a SOA pulse for FIFOA. One word is transferred from the output of FIFOA to the input of FIFOB. The requirements of the SOA pulse for FIFOA is satisfied by the pulse width of DORB. After a second bubble-up delay an empty space arrives at DnA, at which time DIRA goes HIGH. Figure 24 shows the waveforms at all external nodes of both FIFOs during a complete shift-in and shift-out sequence. September 1993 23 Philips Semiconductors Product specification 5-Bit x 64-word FIFO register; 3-state handbook, full pagewidth SI B DOR A DIR A DIR DATA INPUT 5 FIFO A Q nA 5 DnB SO SOB 7404 Q nB 7404 SI A DOR DOR B DIR B SO A SI 74HC/HCT7404 5 DATA OUTPUT FIFO B DnA MR OE MR OE MR MGA682 OE Fig.21 Cascading for increased word capacity; 128 word × 5 bits. Note to Fig.21 The “7404” is easily cascaded to increase word capacity without any external circuitry. In cascaded format, all necessary communications are handled by the FIFOs. Figures 22 and 23 demonstrate the intercommunication timing between FIFOA and FIFOB. Figure 24 provides an overview of pulses and timing of two cascaded FIFOs, when shifted full and shifted empty again. September 1993 24 Philips Semiconductors Product specification 5-Bit x 64-word FIFO register; 3-state 74HC/HCT7404 handbook, full pagewidth DIR A SI A VM VM (1) (1) 2 ripple through delay 4 DOR A SI B VM DIR B SO A 1 5 Q nA DnB (1) VM (1) 6 3 ripple through delay DOR B 7 VM (1) Q nB MGA666 Fig.22 FIFO to FIFO communication; input timing under empty condition. Notes to Fig.22 1. FIFOA and FIFOB initially empty, SOA held HIGH in anticipation of data 2. Load one word into FIFOA; SI pulse applied, results in DIR pulse 3. Data-out A/data-in B transition; valid data arrives at FIFOA output stage after a specified delay of the DOR flag, meeting data input set-up requirements of FIFOB 4. DORA and SIB pulse HIGH; (ripple through delay after SIA LOW) data is unloaded from FIFOA as a result of the data output ready pulse, data is shifted into FIFOB 5. DIRB and SOA go LOW; flag indicates input stage of FIFOB is busy, shift-out of FIFOA is complete 6. DIRB and SOA go HIGH automatically; the input stage of FIFOB is again able to receive data, SO is held HIGH in anticipation of additional data 7. DORB goes HIGH; (ripple through delay after SIB LOW) valid data is present one propagation delay later at the FIFOB output stage. September 1993 25 Philips Semiconductors Product specification 5-Bit x 64-word FIFO register; 3-state 74HC/HCT7404 handbook, full pagewidth VM (1) DOR B SO B VM (1) 2 bubble - up delay DOR A SI B 3 VM (1) DIR B SO A 1 4 VM (1) 5 Q nA DnB bubble - up delay 6 VM (1) DIR A MGA667 Fig.23 FIFO to FIFO communication; output timing under full condition. Notes to Fig.23 1. FIFOA and FIFOB initially full, SIB held HIGH in anticipation of shifting in new data as an empty location bubbles-up 2. Unload one word from FIFOB; SO pulse applied, results in DOR pulse 3. DIRB and SOA pulse HIGH; (bubble-up delay after SOB LOW) data is loaded into FIFOB as a result of the DIR pulse, data is shifted out of FIFOA 4. DORA and SIB go LOW; flag indicates the output stage of FIFOA is busy, shift-in to FIFOB is complete 5. DORA and SIB go HIGH; flag indicates valid data is again available at FIFOA output stage, SIB is held HIGH, awaiting bubble-up of empty location 6. DIRA goes HIGH; (bubble-up delay after SOA LOW) an empty location is present at input stage of FIFOA. September 1993 26 Philips Semiconductors Product specification 5-Bit x 64-word FIFO register; 3-state handbook, full pagewidth sequence 1 sequence 2 74HC/HCT7404 sequence 3 sequence 4 sequence 5 sequence 6 (8) SO B INPUT (3) (4) (14) DORB OUTPUT Q nB OUTPUT (13) (5) DIRB OUTPUT (9) (2) DORA OUTPUT (12) (6) QnA OUTPUT (10) (7) DIRA OUTPUT SI A INPUT (11) (1) DnA INPUT MR INPUT MGA687 Fig.24 Waveforms showing the functionality and intercommunication between two FIFOs (refer to Fig.19). Note to Fig.24 Sequence 1 (both FIFOS empty, starting SHIFT-IN process) After a MR pulse has been applied FIFOA and FIFOB are empty. The DOR flags of FIFOA and FIFOB go LOW due to no valid data being present at the outputs. The DIR flags are set HIGH due to the FIFOs being ready to accept data. SOB is held HIGH and two SIA pulses are applied (1). These pulses allow two data words to ripple through to the output stage of FIFOA and to the input stage of FIFOB (2). When data arrives at the output of FIFOB, a DORB pulse is generated (3). When SOB goes LOW, the first bit is shifted out and a second bit ripples through to the output after which DORB goes HIGH (4). September 1993 27 Philips Semiconductors Product specification 5-Bit x 64-word FIFO register; 3-state Sequence 2 (FIFOB runs full) After the MR pulse, a series of 64 SI pulses are applied. When 64 words are shifted in, DIRB remains LOW due to FIFOB being full (5). DORA goes LOW due to FIFOA being empty. Sequence 3 (FIFOA runs full) When 65 words are shifted in, DORA remains HIGH due to valid data remaining at the output of FIFOA. QnA remains HIGH, being the polarity of the 65th data word (6). After the 128th SI pulse, DIR remains LOW and both FIFOs are full (7). Additional pulses have no effect. Sequence 4 (both FIFOs full, starting SHIFT-OUT process) SIA is held HIGH and two SOB pulses are applied (8). These pulses shift out two words and thus allow two empty locations to bubble-up to the input stage of FIFOB, and proceed to FIFOA (9). When the first empty location arrives at the input of FIFOA, a DIRA pulse is generated (10) and a new word is shifted into FIFOA. SIA is made LOW and now the second empty location reaches the input stage of FIFOA, after which DIRA remains HIGH (11). 74HC/HCT7404 Sequence 5 (FIFOA runs empty) At the start of sequence 5 FIFOA contains 63 valid words due to two words being shifted out and one word being shifted in, in sequence 4. An additional series of SOB pulses are applied. After 63 SOB pulses, all words from FIFOA are shifted into FIFOB. DORA remains LOW (12). Sequence 6 (FIFOB runs empty) After the next SOB pulse, DIRB remains HIGH due to the input stage of FIFOB being empty. After another 63 SOB pulses, DORB remains LOW due to both FIFOs being empty (14). Additional SOB pulses have no effect. The last word remains available at the output Qn. PACKAGE OUTLINES See “74HC/HCT/HCU/HCMOS Logic Package Outlines”. September 1993 28