Philips Semiconductors Product specification Dual 1-of-4 decoder (3-State) 74F539 DESCRIPTION PIN CONFIGURATION The 74F539 contains two independent decoders. Each accepts two address (A0 - A1) input signals and decodes them to select one of four mutually exclusive outputs. A Polarity control (P) input determines whether the outputs are active Low (P=H) or active High (P=L). An active-Low Enable (E) is available for data demultiplexing. Data is routed to the selected output in non-inverted or inverted form in the active-Low mode or inverted form in the active-High mode. A High signal on the Output Enable (OEn) input forces the 3-State outputs to the high impedance state. TYPE TYPICAL PROPAGATION DELAY TYPICAL SUPPLY CURRENT (TOTAL) 74F539 7.5ns 40mA Q2b 1 20 VCC Q1b 2 19 Q3b Q0b 3 18 A1b Pb 4 17 A0b OEb 5 16 Eb A0a 6 15 Ea A1a 7 14 OEa Q3a 8 13 Pa Q2a 9 12 Q0a 11 Q1a GND 10 SF01013 ORDERING INFORMATION DESCRIPTION COMMERCIAL RANGE VCC = 5V ±10%, Tamb = 0°C to +70°C 20-Pin Plastic DIP N74F539N 20-Pin Plastic SOL N74F539D INPUT AND OUTPUT LOADING AND FAN-OUT TABLE PINS DESCRIPTION 74F(U.L.) HIGH/LOW LOAD VALUE HIGH/LOW A0a - A1a Decoder A Address inputs 1.0/1.0 20µA/0.6mA A0b - A1b Decoder B Address inputs 1.0/1.0 20µA/0.6mA Ea, Eb Enable inputs (active Low) 1.0/1.0 20µA/0.6mA OEa, OEb Output Enable inputs (active Low) 1.0/1.0 20µA/0.6mA Pa, Pb Polarity control inputs 1.0/1.0 20µA/0.6mA Q0a–Q3a Decoder A Data outputs 150/40 3.0mA/24mA Q0b–Q3b Decoder A Data outputs 150/40 3.0mA/24mA NOTE: One (1.0) FAST Unit Load is defined as: 20µA in the High state and 0.6mA in the Low state. LOGIC SYMBOL LOGIC SYMBOL (IEEE/IEC) 6 7 17 18 DMUX 13 Pa 15 Ea A0a A1a A0b 4 A1b 5 OEa 18 Pb 16 16 Eb 5 3 0,4 1,4 17 4 14 N4 EN 13 14 OEb 0 1 0 G 3 2,4 3,4 2 1 19 12 11 6 Q0a Q1a Q2a Q3a Q0b Q1b Q2b Q3b 7 15 VCC = Pin 20 GND = Pin 10 1990 Feb 23 12 11 9 8 3 2 1 9 8 19 SF01014 SF01015 1 853–1274 98905 Philips Semiconductors Product specification Dual 1-of-4 decoder (3-State) 74F539 LOGIC DIAGRAM A1n A0n En Pn OEn 7, 18 6, 17 15, 16 13, 4 14, 5 12, 3 VCC = GND = Pin 20 Pin 10 Q0n 11, 2 Q1n 9, 1 Q2n 8, 19 Q3n SF01016 FUNCTION TABLE INPUTS H L X Z OUTPUTS OPERATING MODE OEn En A1n A0n Q0n Q1n Q2n Q3n H X X X Z Z Z Z L H X X L L L L L L L L L L H H L H L H H L L L L H L L L L H L L L L H Active High output (P = L) L L L L L L L L L L H H L H L H L H H H H L H H H H L H H H H L Active Low output (P = H) = = = = Qn=P High Impedance Disable High voltage level Low voltage level Don’t care High impedance “off” state ABSOLUTE MAXIMUM RATINGS (Operation beyond the limits set forth in this table may impair the useful life of the device. Unless otherwise noted these limits are over the operating free-air temperature range.) PARAMETER SYMBOL RATING UNIT V VCC Supply voltage –0.5 to +7.0 VIN Input voltage –0.5 to +7.0 V IIN Input current –30 to +5 mA VOUT Voltage applied to output in High output state –0.5 to +VCC V IOUT Current applied to output in Low output state 48 mA Tamb Operating free-air temperature range 0 to +70 °C Tstg Storage temperature –65 to +150 °C 1990 Feb 23 2 Philips Semiconductors Product specification Dual 1-of-4 decoder (3-State) 74F539 RECOMMENDED OPERATING CONDITIONS SYMBOL LIMITS PARAMETER MIN NOM MAX 5.0 5.5 UNIT VCC Supply voltage 4.5 V VIH High-level input voltage 2.0 VIL Low-level input voltage 0.8 V IIK Input clamp current –18 mA IOH High-level output current –3 mA IOL Low-level output current 24 mA Tamb Operating free-air temperature range 70 °C V 0 DC ELECTRICAL CHARACTERISTICS (Over recommended operating free-air temperature range unless otherwise noted.) SYMBOL VOH O TEST CONDITIONS1 PARAMETER VCC = MIN, VIL = MAX, VIH = MIN, IOH = MAX High level output voltage High-level VOL Low-level output voltage VIK Input clamp voltage VCC = MIN, VIL = MAX, VIH = MIN, IOL = MAX LIMITS MIN ±10%VCC 2.4 ±5%VCC 2.7 ±10%VCC ±5%VCC VCC = MIN, II = IIK TYP2 MAX UNIT V 3.4 V 0.35 0.50 V 0.35 0.50 V –0.73 –1.2 V 100 µA IIH Input current at maximum input voltage High-level input current VCC = MAX, VI = 2.7V 20 µA IIL Low-level input current VCC = MAX, VI = 0.5V –0.6 mA IOZH Off-state output current High-level voltage applied VCC = MAX, VO = 2.7V 50 µA IOZL Off-state output current Low-level voltage applied VCC = MAX, VO = 0.5V –50 µA IOS Short-circuit output current3 –150 mA 35 50 mA ICC Supply current 40 55 mA II VCC = MAX, VI = 7.0V VCC = MAX ICCH ICCL VCC = MAX –60 ICCZ 40 60 mA NOTES: 1. For conditions shown as MIN or MAX, use the appropriate value under the recommended operating conditions for the applicable type. 2. All typical values are at VCC = 5V, Tamb = 25°C. 3. Not more than one output should be shorted at a time. For testing IOS, the use of high-speed test apparatus and/or sample-and-hold techniques are preferable in order to minimize internal heating and more accurately reflect operational values. Otherwise, prolonged shorting of a High output may raise the chip temperature well above normal and thereby cause invalid readings in other parameter tests. In any sequence of parameter tests, IOS should be performed last. 1990 Feb 23 3 Philips Semiconductors Product specification Dual 1-of-4 decoder (3-State) 74F539 AC ELECTRICAL CHARACTERISTICS LIMITS SYMBOL PARAMETER Tamb = +25°C VCC = +5.0V CL = 50pF, RL = 500Ω TEST CONDITIONS Tamb = 0°C to +70°C VCC = +5.0V ± 10% CL = 50pF, RL = 500Ω UNIT MIN TYP MAX MIN MAX Waveform 1 4.5 3.0 8.5 8.0 12.5 12.5 4.0 3.0 13.5 13.0 ns ns Propagation delay En to Qn Waveform 2 5.0 3.0 7.5 7.0 11.0 11.0 4.5 3.0 12.0 11.5 ns ns tPLH tPHL Propagation delay Pn to Qn Waveform 1 4.0 3.5 6.5 5.5 9.5 9.0 3.5 3.0 10.5 9.5 ns ns tPLH tPHL Propagation delay Pn to Qn (INV) Waveform 2 6.0 4.0 11.5 6.0 14.5 9.0 5.0 4.0 15.5 9.5 ns ns tPZH tPZL Output Enable time OEn to Qn Waveform 3 Waveform 4 2.5 5.5 4.0 7.0 7.5 10.5 2.0 5.0 8.5 11.5 ns ns tPHZ tPLZ Output Disable time OEn to Qn Waveform 3 Waveform 4 1.5 2.0 3.0 4.0 6.0 8.0 1.0 1.5 6.5 8.5 ns ns tPLH tPHL Propagation delay An to Qn tPLH tPHL AC WAVEFORMS For all waveforms, VM = 1.5V. An, Pn VM VM tPLH tPHL VM Qn En, Pn VM VM tPHL tPLH VM Qn VM VM SF01017 SF01018 Waveform 1. Propagation Delay for Non-Inverting Outputs OEn VM OEn VM tPZH Qn Waveform 2. Propagation Delay for Inverting Outputs tPHZ VOH -0.3V VM tPZL Qn VM 0V tPLZ VM VOL +0.3V SF01020 SF01019 Waveform 3. 3-State Output Enable Time to High Level and Output Disable Time from High Level 1990 Feb 23 VM Waveform 4. 3-State Output Enable Time to Low Level and Output Disable Time from Low Level 4 Philips Semiconductors Product specification Dual 1-of-4 decoder (3-State) 74F539 TEST CIRCUIT AND WAVEFORM VCC 7.0V VIN RL VOUT PULSE GENERATOR tw 90% NEGATIVE PULSE VM CL AMP (V) VM 10% D.U.T. RT 90% 10% tTHL (tf ) tTLH (tr ) tTLH (tr ) tTHL (tf ) 0V RL AMP (V) 90% 90% Test Circuit for 3-State Outputs POSITIVE PULSE VM VM 10% TEST tPLZ tPZL All other SWITCH closed closed open DEFINITIONS: RL = Load resistor; see AC electrical characteristics for value. CL = Load capacitance includes jig and probe capacitance; see AC electrical characteristics for value. RT = Termination resistance should be equal to ZOUT of pulse generators. 10% tw SWITCH POSITION 0V Input Pulse Definition INPUT PULSE REQUIREMENTS family amplitude VM 74F 3.0V 1.5V rep. rate tw tTLH tTHL 1MHz 500ns 2.5ns 2.5ns SF00777 1990 Feb 23 5