ADC1412D065/080/105/125 Dual 14-bit ADC 65, 80, 105 or 125 Msps CMOS or LVDS DDR digital outputs Rev. 02 — 4 June 2009 Objective data sheet 1. General description The ADC1412D is a dual channel 14-bit Analog-to-Digital Converter (ADC) optimized for high dynamic performances and low power consumption at sample rates up to 125 Msps. Pipelined architecture and output error correction ensure the ADC1412D is accurate enough to guarantee zero missing codes over the entire operating range. Supplied from a single 3 V source, it can handle output logic levels from 1.8 V to 3.3 V in CMOS mode, thanks to a separate digital output supply. It supports the LVDS (Low Voltage Differential Signalling) DDR (Double Data Rate) output standard. An integrated SPI (Serial Peripheral Interface) allows the user to easily configure the ADC. The device also includes a programmable gain amplifier with a flexible input voltage range. With excellent dynamic performance from the baseband to input frequencies of 170 MHz or more, the ADC1412D is ideal for use in communications, imaging and medical applications. 005aaa040 1.5 005aaa042 0 005aaa041 1.5 dB 1 1 0.5 0.5 0 0 -0.5 -0.5 -1 -1 -40 -80 -120 -1.5 -1.5 0 Fig 1. 4000 8000 12000 16000 Integral Non-Linearity (INL) 0 0 Fig 2. 4000 8000 12000 16000 Differential Non-Linearity (DNL) 10 20 30 40 f (MHz) Fig 3. Output spectrum: −1 dBFS, 80 Msps, fi = 4.43 MHz 2. Features n n n n n n SNR, 73 dB SFDR, 90 dBc Sample rate up to 125 Msps Dual-channel14-bit pipelined ADC core Single 3 V supply Flexible input voltage range: 1 V to 2 V (p-p) with 6 dB programmable fine gain n CMOS or LVDS DDR digital outputs n INL ±1 LSB, DNL ±0.5 LSB (typical) n n n n n n Input bandwidth, 650 MHz Power dissipation, 775 mW at 80 Msps SPI Interface Duty cycle stabilizer Fast OTR detection Offset binary, 2’s complement, gray code n Power-down and Sleep modes n HVQFN64 package ADC1412D065/080/105/125 NXP Semiconductors Dual 14-bit ADC 65, 80, 105 or 125 Msps 3. Applications n Wireless and wired broadband communications n Spectral analysis n Portable instrumentation n Ultrasound equipment n Imaging systems 4. Ordering information Table 1. Ordering information Type number fs (Msps) Package Name Description Version ADC1412D125HN/C1 125 HVQFN64 plastic thermal enhanced very thin quad flat package; no leads; 64 terminals; body 9 x 9 x 0.85 mm SOT804-3 ADC1412D105HN/C1 105 HVQFN64 plastic thermal enhanced very thin quad flat package; no leads; 64 terminals; body 9 x 9 x 0.85 mm SOT804-3 ADC1412D080HN/C1 80 HVQFN64 plastic thermal enhanced very thin quad flat package; no leads; 64 terminals; body 9 x 9 x 0.85 mm SOT804-3 ADC1412D065HN/C1 65 HVQFN64 plastic thermal enhanced very thin quad flat package; no leads; 64 terminals; body 9 x 9 x 0.85 mm SOT804-3 ADC1412D065_080_105_125_2 Objective data sheet © NXP B.V. 2009. All rights reserved. Rev. 02 — 4 June 2009 2 of 37 ADC1412D065/080/105/125 NXP Semiconductors Dual 14-bit ADC 65, 80, 105 or 125 Msps CSB SDIO/ODS SCLK/DFS 5. Block diagram ADC1412D ERROR CORRECTION AND DIGITAL PROCESSING SPI INTERFACE OTRA PGA CMOS: DA13 to DA0 or LVDS/DDR: DA13P, DA13M to DA0P, DA0M INAP T/H INPUT STAGE ADC CORE 14-BIT PIPELINED OUTPUT DRIVERS INAM CLKP CMOS: DAV or LVDS/DDR: DAVP DAVM CLOCK INPUT STAGE AND DUTY CYCLE CONTROL CLKM CMOS: DB13 to DB0 or LVDS/DDR: DB13P, DB13M to DB0P, DB0M INBP T/H INPUT STAGE ADC CORE 14-BIT PIPELINED OUTPUT DRIVERS INBM OTRB PGA REFAT CTRL REFAB VCMA VREF VCMB SENSE REFBT VDDO OGND VDDA AGND REFBB SYSTEM REFERENCE AND POWER MANAGEMENT ERROR CORRECTION AND DIGITAL PROCESSING 005aaa096 Fig 4. Block diagram ADC1412D065_080_105_125_2 Objective data sheet © NXP B.V. 2009. All rights reserved. Rev. 02 — 4 June 2009 3 of 37 ADC1412D065/080/105/125 NXP Semiconductors Dual 14-bit ADC 65, 80, 105 or 125 Msps 6. Pinning information 6.1 CMOS outputs selected 49 VDDO 50 VDDO 51 DA6 52 DA7 53 DA8 54 DA9 55 DA10 56 DA11 57 DA12 58 DA13 59 OTRA 60 DECA 61 VDDA INAP 1 48 DA5 INAM 2 47 DA4 AGND 3 46 DA3 VCMA 4 45 DA2 REFAT 5 44 DA1 REFAB 6 43 DA0 AGND 7 42 DAV CLKP 8 CLKM 9 41 n.c. ADC1412D HVQFN64 40 DB0 VDDO 32 VDDO 31 DB8 30 DB9 29 DB10 28 DB11 27 DB12 26 DB13 25 33 DB7 OTRB 24 34 DB6 INBP 16 DECB 23 35 DB5 INBM 15 CTRL 22 36 DB4 AGND 14 CSB 21 37 DB3 VCMB 13 SDIO/ODS 20 38 DB2 REFBT 12 SCLK/DFS 19 39 DB1 REFBB 11 VDDA 18 AGND 10 VDDA 17 Fig 5. 62 SENSE terminal 1 index area 63 VREF 64 VDDA 6.1.1 Pinning 005aaa097 Transparent top view Pin configuration with CMOS digital outputs selected 6.1.2 Pin description Table 2. Pin description (CMOS digital outputs) Symbol Pin Type [1] Description INAP 1 I analog input; channel A INAM 2 I complementary analog input; channel A AGND 3 G analog ground VCMA 4 O common-mode output voltage; channel A REFAT 5 O top reference; channel A REFAB 6 O bottom reference; channel A AGND 7 G analog ground CLKP 8 I clock input CLKM 9 I complementary clock input AGND 10 G analog ground REFBB 11 O bottom reference; channel B REFBT 12 O top reference; channel B ADC1412D065_080_105_125_2 Objective data sheet © NXP B.V. 2009. All rights reserved. Rev. 02 — 4 June 2009 4 of 37 ADC1412D065/080/105/125 NXP Semiconductors Dual 14-bit ADC 65, 80, 105 or 125 Msps Table 2. Pin description (CMOS digital outputs) Symbol Pin Type [1] Description VCMB 13 O common-mode output voltage; channel B AGND 14 G analog ground INBM 15 I complementary analog input; channel B INBP 16 I analog input; channel B VDDA 17 P analog power supply VDDA 18 P analog power supply SCLK/DFS 19 I SPI clock / data format select SDIO/ODS 20 I/O SPI data IO / output data standard CS 21 I SPI chip select CTRL 22 I control mode select DECB 23 O regulator decoupling node; channel B OTRB 24 O out of range; channel B DB13 25 O data output bit 13 (MSB); channel B DB12 26 O data output bit 12; channel B DB11 27 O data output bit 11; channel B DB10 28 O data output bit 10; channel B DB9 29 O data output bit 9; channel B DB8 30 O data output bit 8; channel B VDDO 31 P output power supply VDDO 32 P output power supply DB7 33 O data output bit 7; channel B DB6 34 O data output bit 6; channel B DB5 35 O data output bit 5; channel B DB4 36 O data output bit 4; channel B DB3 37 O data output bit 3; channel B DB2 38 O data output bit 2; channel B DB1 39 O data output bit 1; channel B DB0 40 O data output bit 0 (LSB); channel B n.c. 41 - - DAV 42 O data valid output clock DA0 43 O data output bit 0 (LSB); channel A DA1 44 O data output bit 1; channel A DA2 45 O data output bit 2; channel A DA3 46 O data output bit 3; channel A DA4 47 O data output bit 4; channel A DA5 48 O data output bit 5; channel A VDDO 49 P output power supply VDDO 50 P output power supply DA6 51 O data output bit 6; channel A DA7 52 O data output bit 7; channel A DA8 53 O data output bit 8; channel A DA9 54 O data output bit 9; channel A DA10 55 O data output bit 10; channel A DA11 56 O data output bit 11; channel A ADC1412D065_080_105_125_2 Objective data sheet © NXP B.V. 2009. All rights reserved. Rev. 02 — 4 June 2009 5 of 37 ADC1412D065/080/105/125 NXP Semiconductors Dual 14-bit ADC 65, 80, 105 or 125 Msps Table 2. Pin description (CMOS digital outputs) Symbol Pin Type [1] Description DA12 57 O data output bit 12; channel A DA13 58 O data output bit 13 (MSB); channel A OTRA 59 O out of range; channel A DECA 60 O regulator decoupling node; channel A VDDA 61 P analog power supply SENSE 62 I reference programming pin VREF 63 I/O voltage reference input/output VDDA 64 P analog power supply [1] P: power supply; G: ground; I: input; O: output; I/O: input/output. 6.2 LVDS/DDR outputs selected 49 VDDO 50 VDDO 51 DA6_DA7_P 52 DA6_DA7_M 53 DA8_DA9_P 54 DA8_DA9_M 55 DA10_DA11_P 56 DA10_DA11_M 57 DA12_DA13_P 58 DA12_DA13_M 59 OTRA 60 DECA 61 VDDA 62 SENSE terminal 1 index area 63 VREF 64 VDDA 6.2.1 Pinning INAP 1 48 DA4_DA5_M INAM 2 47 DA4_DA5_P AGND 3 46 DA2_DA3_M VCMA 4 45 DA2_DA3_P REFAT 5 44 DA0_DA1_ M REFAB 6 43 DA0_DA1_P AGND 7 42 DAVP CLKP 8 CLKM 9 41 DAVM ADC1412D HVQFN64 40 DB0_DB1_P VDDO 32 VDDO 31 DB8_DB9_P 30 DB8_DB9_M 29 DB10_DB11_P 28 DB10_DB11_M 27 DB12_DB13_P 26 DB12_DB13_M 25 OTRB 24 33 DB6_DB7_M DECB 23 34 DB6_DB7_P INBP 16 CTRL 22 35 DB4_DB5_M INBM 15 CSB 21 36 DB4_DB5_P AGND 14 SDIO/ODS 20 37 DB2_DB3_M VCMB 13 SCLK/DFS 19 38 DB2_DB3_P REFBT 12 VDDA 18 39 DB0_DB1_M REFBB 11 VDDA 17 AGND 10 005aaa098 Transparent top view Fig 6. Pin configuration with LVDS/DDR digital outputs selected ADC1412D065_080_105_125_2 Objective data sheet © NXP B.V. 2009. All rights reserved. Rev. 02 — 4 June 2009 6 of 37 ADC1412D065/080/105/125 NXP Semiconductors Dual 14-bit ADC 65, 80, 105 or 125 Msps 6.2.2 Pin description Table 3. Pin description (LVDS/DDR) digital outputs) [1] Type [2] Description O differential output data DB12 and DB13 multiplexed, complement DB12_DB13_P 26 O differential output data DB12 and DB13 multiplexed, true DB10_DB11_M 27 O differential output data DB10 and DB11 multiplexed, complement DB10_DB11_P 28 O differential output data DB10 and DB11 multiplexed, true DB8_DB9_M 29 O differential output data DB8 and DB9 multiplexed, complement DB8_DB9_P 30 O differential output data DB8 and DB9 multiplexed, true DB6_DB7_M 33 O differential output data DB6 and DB7 multiplexed, complement DB6_DB7_P 34 O differential output data DB6 and DB7 multiplexed, true DB4_DB5_M 35 O differential output data DB4 and DB5 multiplexed, complement DB4_DB5_P 36 O differential output data DB4 and DB5 multiplexed, true DB2_DB3_M 37 O differential output data DB2 and DB3 multiplexed, complement DB2_DB3_P 38 O differential output data DB2 and DB3 multiplexed, true DB0_DB1_M 39 O differential output data DB0 and DB1 multiplexed, complement DB0_DB1_P 40 O differential output data DB0 and DB1 multiplexed, true DAVM 41 O data valid output clock, complement Symbol Pin DB12_DB13_M 25 DAVP 42 O data valid output clock, true DA0_DA1_P 43 O differential output data DA0 and DA1 multiplexed, true DA0_DA1_M 44 O differential output data DA0 and DA1 multiplexed, complement DA2_DA3_P 45 O differential output data DA2 and DA3 multiplexed, true DA2_DA3_M 46 O differential output data DA2 and DA3 multiplexed, complement DA4_DA5_P 47 O differential output data DA4 and DA5 multiplexed, true DA4_DA5_M 48 O differential output data DA4 and DA5 multiplexed, complement DA6_DA7_P 51 O differential output data DA6 and DA7 multiplexed, true DA6_DA7_M 52 O differential output data DA6 and DA7 multiplexed, complement DA8_DA9_P 53 O differential output data DA8 and DA9 multiplexed, true DA8_DA9_M 54 O differential output data DA8 and DA9 multiplexed, complement DA10_DA11_P 55 O differential output data DA10 and DA11 multiplexed, true DA10_DA11_M 56 O differential output data DA10 and DA11 multiplexed, complement DA12_DA13_P 57 O differential output data DA12 and DA13 multiplexed, true DA12_DA13_M 58 O differential output data DA12 and DA13 multiplexed, complement [1] Pins 1 to 24, pin 59 to 64 and pins 31, 32, 49 and 50 are the same for both CMOS and LVDS DDR outputs (see Table 2). [2] P: power supply; G: ground; I: input; O: output; I/O: input/output. ADC1412D065_080_105_125_2 Objective data sheet © NXP B.V. 2009. All rights reserved. Rev. 02 — 4 June 2009 7 of 37 ADC1412D065/080/105/125 NXP Semiconductors Dual 14-bit ADC 65, 80, 105 or 125 Msps 7. Limiting values Table 4. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol Parameter Conditions VDDA analog supply voltage VDDO output supply voltage ∆VCC supply voltage difference Tstg Min Max Unit <tbd> <tbd> V <tbd> <tbd> V <tbd> <tbd> V storage temperature −55 +125 °C Tamb ambient temperature −40 +85 °C Tj junction temperature - <tbd> °C VDDA − VDDO 8. Thermal characteristics Table 5. Thermal characteristics Symbol Rth(j-a) Rth(j-c) [1] Parameter Conditions Typ Unit thermal resistance from junction to ambient [1] <tbd> K/W thermal resistance from junction to case [1] <tbd> K/W In compliance with JEDEC test board, in free air. 9. Static characteristics Table 6. Static characteristics Typical values measured at VDDA = 3 V, VDDO = 1.8 V, Tamb = 25 °C and CL = 5 pF; min and max values are across the full temperature range Tamb = −40 °C to +85 °C at VDDA = 3 V, VDDO = 1.8 V; VINAP − VINAM = −1 dBFS; VINBP − VINBM = −1 dBFS; internal reference mode; applied to CMOS and LVDS interface; unless otherwise specified. Symbol Parameter Conditions Min Typ Max Unit 2.85 3.0 3.4 V 1.65 1.8 3.6 V Supplies VDDA analog supply voltage VDDO output supply voltage LVDS DDR mode 2.85 3.0 3.6 V IDDA analog supply current fclk = 125 Msps; fi =70 MHz - 370 - mA IDDO output supply current CMOS mode; fclk = 125 Msps; fi =70 MHz - 40 - mA LVDS DDR mode: fclk = 125 Msps; fi =70 MHz - 90 - mA ADC1412D125 - 1100 - mW ADC1412D105 - 975 - mW ADC1412D080 - 775 - mW ADC1412D065 - 670 - mW Power-down mode - <tbd> - mW Sleep mode - <tbd> - mW P power dissipation CMOS mode ADC1412D065_080_105_125_2 Objective data sheet © NXP B.V. 2009. All rights reserved. Rev. 02 — 4 June 2009 8 of 37 ADC1412D065/080/105/125 NXP Semiconductors Dual 14-bit ADC 65, 80, 105 or 125 Msps Table 6. Static characteristics …continued Typical values measured at VDDA = 3 V, VDDO = 1.8 V, Tamb = 25 °C and CL = 5 pF; min and max values are across the full temperature range Tamb = −40 °C to +85 °C at VDDA = 3 V, VDDO = 1.8 V; VINAP − VINAM = −1 dBFS; VINBP − VINBM = −1 dBFS; internal reference mode; applied to CMOS and LVDS interface; unless otherwise specified. Symbol Parameter Conditions Min Typ Max Unit peak-to-peak 0.2 0.8 <tbd> V 0.3VDDA - 0.7VDDA V - 0 - V - 0.3VDDA - V Clock inputs: pins CLKP and CLKM AC coupled; LVPECL, LVDS and sine wave Vi(clk)dif differential clock input voltage LVCMOS VI input voltage Logic Input: pin CTRL VIL LOW-level input voltage LOW-medium level - 0.6VDDA - VIH HIGH-level input voltage - VDDA - V IIL LOW-level input current <tbd> - <tbd> µA IIH HIGH-level input current −10 - +10 µA medium-HIGH level Serial Peripheral Interface: pins CS, SDIO/ODS, SCLK/DFS VIL LOW-level input voltage 0 - 0.3VDDA V VIH HIGH-level input voltage 0.7VDDA - VDDA V IIL LOW-level input current −10 - +10 µA IIH HIGH-level input current −50 - +50 µA CI input capacitance - 4 - pF Digital Outputs: CMOS mode - pins DA13 to DA0, DB13 to DB0, OTRA, OTRB AND DAV Output levels, VDDO=3 V VOL LOW-level output voltage IOL = <tbd> OGND - 0.2VDDO V VOH HIGH-level output voltage IOH = <tbd> 0.8VDDO - VDDO V IOL LOW-level output current 3-state; output level = 0 V - <tbd> - µA IOH HIGH-level output current 3-state; output level = VDDA - <tbd> - µA CO output capacitance high impedance; OE = HIGH - 3 - pF Output levels, VDDO=1.8 V VOL LOW-level output voltage IOL = <tbd> OGND - 0.2VDDO V VOH HIGH-level output voltage IOH = <tbd> 0.8VDDO - VDDO V Digital Outputs, LVDS DDR mode - pins DA13P/DA13M to DA0P/DA0M, DB13P/DB13M to DB0P/DBOM, DAVP and DAVM Output levels, VDDO = 3 V only, RL = 100 Ω VO(offset) output offset voltage output buffer current set to 3.5 mA - 1.2 - V VO(dif) differential output voltage output buffer current set to 3.5 mA - 350 - mV CO output capacitance - <tbd> - pF Analog inputs: pins INAP, INAM, INBP and INBM II Input current −5 - +5 µA RI Input resistance - <tbd> - Ω ADC1412D065_080_105_125_2 Objective data sheet © NXP B.V. 2009. All rights reserved. Rev. 02 — 4 June 2009 9 of 37 ADC1412D065/080/105/125 NXP Semiconductors Dual 14-bit ADC 65, 80, 105 or 125 Msps Table 6. Static characteristics …continued Typical values measured at VDDA = 3 V, VDDO = 1.8 V, Tamb = 25 °C and CL = 5 pF; min and max values are across the full temperature range Tamb = −40 °C to +85 °C at VDDA = 3 V, VDDO = 1.8 V; VINAP − VINAM = −1 dBFS; VINBP − VINBM = −1 dBFS; internal reference mode; applied to CMOS and LVDS interface; unless otherwise specified. Symbol Parameter CI Input capacitance VI(cm) common-mode input voltage Bi input bandwidth VI(dif) differential input voltage Conditions VINAP = VINAM; VINBP = VINBM peak-to-peak Min Typ Max Unit - 5 - pF 0.9 1.5 2 V - 600 - MHz 1 - 2 V Common mode output voltage: pins VCMA and VCMB VO(cm) common-mode output voltage - 0.5VDDA - V IO(cm) common-mode output current - <tbd> - µA output - 0.5 to 1 - V input 0.5 - 1 V −5 ±1 +5 LSB I/O reference voltage: pin VREF VVREF voltage on pin VREF Accuracy INL integral non-linearity DNL differential non-linearity −0.95 ±0.5 +0.95 LSB Eoffset offset error - ±2 - mV EG gain error - ±0.5 - %FS MG(CTC) channel-to-channel gain matching - <tbd> - % - 35 - dBc guaranteed no missing codes Supply PSRR power supply rejection ratio 100 mV (p-p) on VDDA ADC1412D065_080_105_125_2 Objective data sheet © NXP B.V. 2009. All rights reserved. Rev. 02 — 4 June 2009 10 of 37 ADC1412D065/080/105/125 NXP Semiconductors Dual 14-bit ADC 65, 80, 105 or 125 Msps 10. Dynamic characteristics 10.1 Dynamic Characteristics Table 7. Dynamic characteristics Typical values measured at VDDA = 3 V, VDDO = 1.8 V, Tamb = 25 °C and CL = 5 pF; min and max values are across the full temperature range Tamb = −40 °C to +85 °C at VDDA = 3 V, VDDO = 1.8 V; VINAP − VINAM = −1 dBFS; VINBP − VINBM = −1 dBFS; internal reference mode; applied to CMOS and LVDS interface; unless otherwise specified. Symbol Parameter Conditions ADC1412D065 Min ADC1412D080 ADC1412D105 ADC1412D125 Typ Max Min Typ Max Min Typ Max Min Typ Max Unit Analog signal processing α2H α3H THD ENOB SNR SFDR IMD αct(ch) second harmonic level third harmonic level total harmonic distortion effective number of bits signal-tonoise ratio spuriousfree dynamic range fi = 3 MHz - 94 - - 94 - - 96 - - 96 - dBc fi = 30 MHz - 93 - - 93 - - 92 - - 93 - dBc fi = 70 MHz - 90 - - 91 - - 91 - - 91 - dBc fi = 170 MHz - 88 - - 88 - - 85 - - 85 - dBc fi = 3 MHz - 92 - - 93 - - 91 - - 90 - dBc fi = 30 MHz - 91 - - 92 - - 91 - - 89 - dBc fi = 70 MHz - 90 - - 90 - - 90 - - 87 - dBc fi = 170 MHz - 88 - - 87 - - 88 - - 87 - dBc fi = 3 MHz - 88 - - 88 - - 87 - - 87 - dBc fi = 30 MHz - 87 - - 87 - - 87 - - 86 - dBc fi = 70 MHz - 86 - - 86 - - 85 - - 84 - dBc fi = 170 MHz - 83 - - 83 - - 82 - - 82 - dBc fi = 3 MHz - 11.9 - - 11.9 - - 11.8 - - 11.8 - bits fi = 30 MHz - 11.7 - - 11.7 - - 11.7 - - 11.7 - bits fi = 70 MHz - 11.6 - - 11.6 - - 11.6 - - 11.6 - bits fi = 170 MHz - 11.6 - - 11.5 - - 11.5 - - 11.5 - bits fi = 3 MHz - 73.2 - - 73.1 - - 72.9 - - 72.5 - dBFS fi = 30 MHz - 72.4 - - 72.3 - - 72.3 - - 72.2 - dBFS fi = 70 MHz - 71.8 - - 71.8 - - 71.7 - - 71.6 - dBFS fi = 170 MHz - 71.3 - - 71.2 - - 71.1 - - 71 - dBFS fi = 3 MHz - 91 - - 91 - - 90 - - 90 - dBc fi = 30 MHz - 90 - - 90 - - 90 - - 89 - dBc fi = 70 MHz - 89 - - 89 - - 88 - - 87 - dBc fi = 170 MHz - 86 - - 86 - - 85 - - 85 - dBc Intermodul- fi = 3 MHz ation fi = 30 MHz distortion fi = 70 MHz channel crosstalk - 94 - - 94 - - 93 - - 93 - dBc - 93 - - 93 - - 93 - - 92 - dBc - 92 - - 92 - - 91 - - 90 - dBc fi = 170 MHz - 89 - - 89 - - 88 - - 88 - dBc fi = 70 MHz - tbd - - tbd - - tbd - - tbd - dB ADC1412D065_080_105_125_2 Objective data sheet © NXP B.V. 2009. All rights reserved. Rev. 02 — 4 June 2009 11 of 37 ADC1412D065/080/105/125 NXP Semiconductors Dual 14-bit ADC 65, 80, 105 or 125 Msps 10.2 Clock and Digital Output Timing Table 8. Clock and digital output timing characteristics Typical values measured at VDDA = 3 V, VDDO = 1.8 V, Tamb = 25 °C and CL = 5 pF; min and max values are across the full temperature range Tamb = −40 °C to +85 °C at VDDA = 3 V, VDDO = 1.8 V ; VINAP − VINAM = −1 dBFS; VINBP − VINBM = −1 dBFS; unless otherwise specified. Symbol Parameter Conditions ADC1412D065 Min ADC1412D080 ADC1412D105 ADC1412D125 Typ Max Min Typ Max Min Typ Max Min Typ Max Unit Clock timing input: pins CLKP and CLKM fclk clock frequency 20 - 65 60 - 80 60 - 105 60 - 125 MHz tlat(data) data latency time - 14 - - 14 - - 14 - - 14 - clk/cy δclk clock duty cycle 50 70 30 50 70 30 50 70 30 50 70 % 50 55 45 50 55 45 50 55 45 50 55 % td(s) sampling delay time - 0.8 - - 0.8 - - 0.8 - - 0.8 - ns twake wake-up time - tbd - - tbd - - tbd - - tbd - ns DCS_EN = 1 30 DCS_EN = 0 45 CMOS mode timing: pins DA13 to DA0, DB13 to DB0 and DAV propagation DATA delay DAV - 3.9 - - 3.9 - - 3.9 - - 3.9 - ns - 4.2 - - 4.2 - - 4.2 - - 4.2 - ns tsu set-up time - 7.7 - - 6.5 - - 4.7 - - 4.3 - ns th hold time - 6.7 - - 5.5 - - 3.8 - - 3.5 - ns DATA 0.5 - 2.4 0.5 - 2.4 0.5 - 2.4 0.5 - 2.4 ns DAV 0.5 - 2.4 0.5 - 2.4 0.5 - 2.4 0.5 - 2.4 ns DATA 0.5 - 2.4 0.5 - 2.4 0.5 - 2.4 0.5 - 2.4 ns tPD tr tf rise fall time[1] time[1] LVDS DDR mode timing: pins DA13P/DA13M to DA0P/DA0M, DAVP and DAVM; DB13P/DB13M to DB0P/DB0M tPD [1] propagation DATA delay DAV 3.9 3.9 3.9 3.9 ns 4.2 4.2 4.2 4.2 ns Measured between 20 % to 80 % of VDDO; rise time measured from −50 mV to +50 mV; fall time measured from +50 mV to −50 mV. ADC1412D065_080_105_125_2 Objective data sheet © NXP B.V. 2009. All rights reserved. Rev. 02 — 4 June 2009 12 of 37 NXP Semiconductors ADC1412D065/080/105/125 Dual 14-bit ADC 65, 80, 105 or 125 Msps 10.3 SPI Timings Table 9. Characteristics Typical values measured at VDDA = 3 V, VDDO = 1.8 V, Tamb = 25 °C and CL = 5 pF; min and max values are across the full temperature range Tamb = −40 °C to +85 °C at VDDA = 3 V, VDDO = 1.8 V Symbol Parameter Conditions Min Typ Max Unit SPI timings tw(SCLK) SCLK pulse width 40 - - ns tw(SCLKH) SCLK HIGH pulse width 16 - - ns tw(SCLKL) SCLK LOW pulse width 16 - - ns tsu set-up time th fclk(max) hold time data to SCLKH 5 - - ns CS to SCLKH 5 - - ns data to SCLKH 2 - - ns CS to SCLKH 2 - - ns - - 25 MHz maximum clock frequency ADC1412D065_080_105_125_2 Objective data sheet © NXP B.V. 2009. All rights reserved. Rev. 02 — 4 June 2009 13 of 37 ADC1412D065/080/105/125 NXP Semiconductors Dual 14-bit ADC 65, 80, 105 or 125 Msps 11. Application information 11.1 Device control The ADC1412D can be controlled via the Serial Peripheral Interface (SPI control mode) or directly via the I/O pins (PIN control mode). 11.1.1 SPI and PIN control modes The device enters PIN control mode at power-up, and remains in this mode as long as pin CS is held HIGH. In PIN control mode, the SPI pins SDIO, CS and SCLK are used as static control pins. SPI settings are ignored. SPI control mode is enabled by forcing pin CS LOW. It is not possible to toggle between PIN control and SPI control modes. Once SPI control mode has been enabled, the device will remain in this mode until it is powered down. The transition from PIN control mode to SPI control mode is illustrated in Figure 7. CS SCLK/DFS SDIO/ODS PIN control mode Data Format 2's complement SPI control mode Data Format offset binary LVDS DDR R/W CMOS W1 W0 A12 005aaa039 Fig 7. Control mode selection. When the device enters SPI control mode, the output data standard (CMOS or LVD DDR) is not determined by the state of the relevant SPI control bit (LVDS/CMOS; see Table 22), but by the level on pin SDIO at the instant a transition is triggered by a falling edge on CS (SDIO = LOW = CMOS). 11.1.2 Operating mode selection The active ADC1412D operating mode (Power-up, Power-down or Sleep) can be selected via the SPI interface (see Table 19) or using pins PWD and OE in PIN control mode, as described in Table 10. Table 10. Operating mode selection via pin CTRL Pin CTRL Operating mode Output high-Z 0 Power-down yes 0.3VDDA Sleep yes 0.6VDDA Power-up yes VDDA Power-up no 11.1.3 Selecting the output data standard The output data standard (CMOS or LVDS DDR) can be selected via the SPI interface (see Table 22) or using pin ODS in PIN control mode. LVDS DDR is selected when ODS is HIGH, otherwise CMOS is selected. ADC1412D065_080_105_125_2 Objective data sheet © NXP B.V. 2009. All rights reserved. Rev. 02 — 4 June 2009 14 of 37 ADC1412D065/080/105/125 NXP Semiconductors Dual 14-bit ADC 65, 80, 105 or 125 Msps 11.1.4 Selecting the output data format The output data format can be selected via the SPI interface (offset binary, 2’s complement or gray code; see Table 22) or using pin DFS in PIN control mode (offset binary or 2’s complement). Offset binary is selected when DFS is LOW. When DFS is HIGH, 2’s complement is selected. 11.2 Analog inputs 11.2.1 Input stage The analog input of the ADC1412D supports differential or single-ended input drive. Optimal performance is achieved using differential inputs with the common-mode input voltage (VI(cm)) on pins INAP, INAM, INBP and INBM set to 0.5VDDA. The full scale analog input voltage range is configurable between 1 V (p-p) and 2 V (p-p) via a programmable internal reference (see Section 11.3 and Table 21 further details). The equivalent circuit of the sample and hold input stage, including ESD protection and circuit and package parasitics, is shown in Figure 8. Package ESD Parasitics Switch Ron = 14 Ω 4 pF INAP/INBP internal clock Sampling Capacitor Switch Ron = 14 Ω 4 pF INAM/INBM internal clock Sampling Capacitor 005aaa092 Fig 8. Input sampling circuit The sample phase occurs when the internal clock (derived from the clock signal on pin CLKP/CLKM) is HIGH. The voltage is then held on the sampling capacitors. When the clock signal goes LOW, the stage enters the hold phase and the voltage information is transmitted to the ADC core. 11.2.2 Anti-kickback circuitry Anti-kickback circuitry (R-C filter in Figure 9 is needed to counteract the effects of charge injection generated by the sampling capacitance. ADC1412D065_080_105_125_2 Objective data sheet © NXP B.V. 2009. All rights reserved. Rev. 02 — 4 June 2009 15 of 37 ADC1412D065/080/105/125 NXP Semiconductors Dual 14-bit ADC 65, 80, 105 or 125 Msps The RC filter is also used to filter noise from the signal before it reaches the sampling stage. The value of the capacitor should be chosen to maximize noise attenuation without degrading the settling time excessively. R INAP/INBP C R INAM/INBM 005aaa093 Fig 9. Anti-kickback circuit The component values are determined by the input frequency and should be selected so as not to affect the input bandwidth. Table 11. RC coupling versus input frequency - recommended values Input frequency R C 3 MHz 25 ohms 12 pF 70 MHz 12 ohms 8 pF 170 MHz 12 ohms 8 pF 11.2.3 Transformer The configuration of the transformer circuit is determined by the input frequency. The configuration shown in Figure 10 would be suitable for a baseband application. ADT1-1WT 100 nF Analog lnput 25 Ω 100 nF INAP/INBP 25 Ω 12 pF 100 nF 100 nF 25 Ω 25 Ω INAM/INBM VCMA/VCMB 100 nF 100 nF 005aaa094 Fig 10. Single transformer configuration suitable for baseband applications The configuration shown in Figure 11 is recommended for high frequency applications. In both cases, the choice of transformer will be a compromise between cost and performance. ADC1412D065_080_105_125_2 Objective data sheet © NXP B.V. 2009. All rights reserved. Rev. 02 — 4 June 2009 16 of 37 ADC1412D065/080/105/125 NXP Semiconductors Dual 14-bit ADC 65, 80, 105 or 125 Msps ADT1-1WT Analog lnput 100 nF ADT1-1WT 12 Ω 50 Ω 50 Ω 50 Ω 50 Ω INAP/INBP 8.2 pF 12 Ω 100 nF INAM/INBM VCMA/VCMB 100 nF 100 nF 005aaa045 Fig 11. Dual transformer configuration suitable for high frequency application 11.3 System reference and power management 11.3.1 Internal/external references The ADC1412D has a stable and accurate built-in internal reference voltage. This reference voltage can be set internally, externally or via the SPI (programmable in 1 dB steps between 0 dB and −6 dB via control bits INTREF when bit INTREF_EN = 1; see Table 21). The equivalent reference circuit is shown in Figure 12. REFAT/REFBT REFERENCE AMP VREF BUFFER REFAB/REFBB BANDGAP REFERENCE ADC CORE SENSE SELECTION LOGIC 005aaa110 Fig 12. Single transformer configuration suitable for baseband applications If bit INTREF_EN is set to 0, the reference voltage will be determined either internally or externally as detailed in Table 12. ADC1412D065_080_105_125_2 Objective data sheet © NXP B.V. 2009. All rights reserved. Rev. 02 — 4 June 2009 17 of 37 ADC1412D065/080/105/125 NXP Semiconductors Dual 14-bit ADC 65, 80, 105 or 125 Msps Table 12. Reference selection Selection SPI bit INTREF_EN SENSE pin VREF pin full scale (p-p) internal 0 AGND 330 pF capacitor to AGND 2V internal 0 pin VREF connected to pin SENSE and via a 330 pF capacitor to AGND external 0 VDDA external voltage between 0.5 V and 1 V[1] 1 V to 2 V internal via SPI 1 pin VREF connected to pin SENSE and via 330 pF capacitor to AGND 1 V to 2 V [1] 1V The voltage on pin VREF is doubled internally to generate the internal reference voltage. Figure 13 to Figure 16 illustrate how to connect the SENSE and VREF pins to select the required reference voltage source. VREF VREF REFAT/REFBT SENSE REFAB/REFBB REFAT/REFBT 330 pF 330 pF REFAB/REFBB SENSE 005aaa117 005aaa116 Fig 13. Internal reference, 2 V (p-p) full scale VREF Fig 14. Internal reference, 1 V (p-p) full scale REFAT/REFBT VREF V 330 pF SPI SETTINGS INTREF_EN = 1, active INTREF = XXX 0.1 µF REFAB/REFBB SENSE Fig 15. Internal reference via SPI, 1 V to 2 V (p-p) full scale 005aaa119 Fig 16. External reference, 1 V to 2 V (p-p) full scale ADC1412D065_080_105_125_2 Objective data sheet REFAB/REFBB SENSE VDDA 005aaa118 REFAT/REFBT © NXP B.V. 2009. All rights reserved. Rev. 02 — 4 June 2009 18 of 37 ADC1412D065/080/105/125 NXP Semiconductors Dual 14-bit ADC 65, 80, 105 or 125 Msps 11.3.2 Gain control The gain is programmable between 0 dB to −6 dB in 1 dB steps via the SPI (see Table 21). This makes it possible to improve the Spurious-Free Dynamic Range (SFDR) of the ADC1412D. The corresponding full scale input voltage range varies between 2 V (p-p) and 1 V (p-p), as shown in Table 13: Table 13. Reference SPI Gain Control INTREF Gain full scale (p-p) 000 0 dB 2V 001 −1 dB 1.78 V 010 −2 dB 1.59 V 011 −3 dB 1.42 V 100 −4 dB 1.26 V 101 −5 dB 1.12 V 110 −6 dB 1V 111 reserved x 11.3.3 Common-mode output voltage (VO(cm)) A 0.1 µF filter capacitor should be connected between pin VCMA/VCMB and ground to ensure a low-noise common-mode output voltage. When AC-coupled, pin VCMA/VCMB can then be used to set the common-mode reference for the analog inputs, for instance via a transformer middle point. PACKAGE ESD PARASITICS COMMON MODE REFERENCE VCMA/VCMB 1.5 V 0.1 µF ADC CORE 005aaa099 Fig 17. Equivalent schematic of the common-mode reference circuit 11.3.4 Biasing The common-mode input voltage (VI(cm)) on pins INAP/INBP and INAM/INBM should be set externally to 0.5VDDA for optimal performance and should always be between 0.9 V and 2 V. The graph in Figure 18 illustrates how the SFDR and SNR characteristics vary with changes in the common-mode input voltage. ADC1412D065_080_105_125_2 Objective data sheet © NXP B.V. 2009. All rights reserved. Rev. 02 — 4 June 2009 19 of 37 ADC1412D065/080/105/125 NXP Semiconductors Dual 14-bit ADC 65, 80, 105 or 125 Msps Package ESD Parasitics Switch Ron = 14 Ω 4 pF INAP/INBP internal clock Sampling Capacitor Switch Ron = 14 Ω 4 pF INAM/INBM internal clock Sampling Capacitor 005aaa092 Fig 18. SFDR and SNR performances versus VI(cm) 11.4 Clock input 11.4.1 Drive modes The ADC1412D can be driven differentially (SINE, LVPECL or LVDS) without the performance being affected by the choice of configuration. It can also be driven by a single-ended LVCMOS signal connected to pin CLKP (CLKM should be connected to ground via a capacitor) or CLKM (CLKP should be connected to ground via a capacitor). LVCMOS Clock lnput CLKP CLKP CLKM LVCMOS Clock lnput CLKM 005aaa053 Fig 19. LVCMOS Single Ended Clock Input ADC1412D065_080_105_125_2 Objective data sheet © NXP B.V. 2009. All rights reserved. Rev. 02 — 4 June 2009 20 of 37 ADC1412D065/080/105/125 NXP Semiconductors Dual 14-bit ADC 65, 80, 105 or 125 Msps CLKP Sine Clock lnput CLKP Sine Clock lnput CLKM CLKM 005aaa054 Fig 20. Sine differential clock input CLKP LVDS Clock lnput CLKM 005aaa055 Fig 21. LVDS differential clock input 11.4.2 Equivalent input circuit The equivalent circuit of the input clock buffer is shown in Figure 22. The common-mode voltage of the differential input stage is set via internal 5 kΩ resistors. PACKAGE ESD PARASITICS CLKP Vcm(clk) SE_SEL SE_SEL 5k 5k CLKM 005aaa056 Fig 22. Equivalent Input circuit Single-ended or differential clock inputs can be selected via the SPI interface (see Table 20). If single-ended is enabled, the input pin (CLKM or CLKP) is selected via control bit SE_SEL. ADC1412D065_080_105_125_2 Objective data sheet © NXP B.V. 2009. All rights reserved. Rev. 02 — 4 June 2009 21 of 37 ADC1412D065/080/105/125 NXP Semiconductors Dual 14-bit ADC 65, 80, 105 or 125 Msps If single-ended is implemented without setting SE_SEL to the appropriate value, the unused pin should be connected to ground via a capacitor. 11.4.3 Duty cycle stabilizer The duty cycle stabilizer can improve the overall performances of the ADC by compensating the duty cycle of the input clock signal. When the duty cycle stabilizer is active (bit DCS_EN = 1; see Table 20), the circuit can handle signals with duty cycles of between 30 % and 70 % (typical). When the duty cycle stabilizer is disabled (DCS_EN = 0), the input clock signal should have a duty cycle of between 45 % and 55 %. 11.4.4 Clock input divider The ADC1412D contains an input clock divider that divides the incoming clock by a factor of 2 (when bit CLKDIV = 1; see Table 20). This feature allows the user to deliver a higher clock frequency with better jitter performance, leading to a better SNR result once acquisition has been performed. 11.5 Digital outputs 11.5.1 Digital output buffers: CMOS mode The digital output buffers can be configured as CMOS by setting bit LVDS/CMOS to 0 (see Table 22). Each digital output has a dedicated output buffer. The equivalent circuit of the CMOS digital output buffer is shown in Figure 23. The buffer is powered by a separate OGND/VDDO to ensure 1.8 V to 3.4 V compatibility and is isolated from the ADC core. Each buffer can be loaded by a maximum of 10 pF. VDDO PARASITICS ESD PACKAGE 50 Ω LOGIC DRIVER Dx OGND 005aaa057 Fig 23. CMOS digital output buffer The output resistance is 50 Ω and is the combination of the an internal resistor and the equivalent output resistance of the buffer. There is no need for an external damping resistor. The drive strength of both data and DAV buffers can be programmed via the SPI in order to adjust the rise and fall times of the output digital signals (see Table 29): ADC1412D065_080_105_125_2 Objective data sheet © NXP B.V. 2009. All rights reserved. Rev. 02 — 4 June 2009 22 of 37 ADC1412D065/080/105/125 NXP Semiconductors Dual 14-bit ADC 65, 80, 105 or 125 Msps 11.5.2 Digital output buffers: LVDS DDR mode The digital output buffers can be configured as LVDS DDR by setting bit LVDS/CMOS to 1 (see Table 22). VCCO 3.5 mA typ − + DAnP/DAn + 1P, DBnP/DBn + 1P 100 Ω − + RECEIVER DAnM/DA + 1M, DBnM/DBn + 1M OGND 005aaa112 Fig 24. LVDS DDR digital output buffer - externally terminated Each output should be terminated externally with a 100 Ω resistor (typical) at the receiver side (Figure 24) or internally via SPI control bits LVDS_INTTER (see Figure 25 and Table 31). VCCO 3.5 mA typ − + DAnP/DAn + 1P, DBnP/DBn + 1P 100 Ω + − RECEIVER DAnM/DA + 1M, DBnM/DBn + 1M OGND Fig 25. LVDS DDR digital output buffer - internally terminated The default LVDS DDR output buffer current is set to 3.5 mA. It can be programmed via the SPI (bits DAVI and DATAI; see Table 30) in order to adjust the output logic voltage levels. 11.5.3 Data valid (DAV) output clock A data valid output clock signal (DAV) is provided that can be used to capture the data delivered by the ADC1412D. Detailed timing diagrams for CMOS and LVDS DDR modes are provided in Figure 26 and Figure 27 respectively. 11.5.4 Out-of-Range (OTR) An out-of-range signal is provided on pin OTRA for ADC channel A and on pin OTRB for ADC channel B. By default, pins OTRA/B go HIGH fourteen clock cycles after an OTR event has occurred. The OTR response can be speeded up by enabling Fast OTR (bit ADC1412D065_080_105_125_2 Objective data sheet © NXP B.V. 2009. All rights reserved. Rev. 02 — 4 June 2009 23 of 37 ADC1412D065/080/105/125 NXP Semiconductors Dual 14-bit ADC 65, 80, 105 or 125 Msps FASTOTR = 1; see Table 28). When Fast OTR is enabled, OTRA/B goes HIGH four clock cycles after the OTR event (separately for each ADC channel). The Fast OTR detection threshold (below full scale) can be programmed via bits FASTOTR_DET. 11.5.5 Digital offset By default, the ADC1412D delivers output code that corresponds to the analog input. However it is possible to add a digital offset to the output code via the SPI (bits DIG_OFFSET; see Table 24). 11.5.6 Test patterns For test purposes, the ADC1412D can be configured to transmit one of a number of predefined test patterns (via bits TESTPAT_SEL; see Table 25). A custom test pattern can be defined by the user (TESTPAT_USER; see Table 26 and Table 27) and is selected when TESTPAT_SEL = 101. The selected test pattern will be transmitted regardless of the analog input. 11.5.7 Output codes versus input voltage Table 14. Output codes VINAP − VINAM/ Offset binary VINBP − VINBM Two’s complement OTRA/B pin < −1 00 0000 0000 0000 10 0000 0000 0000 1 −1 00 0000 0000 0000 10 0000 0000 0000 0 −0.9998779 00 0000 0000 0001 10 0000 0000 0001 0 −0.9997559 00 0000 0000 0010 10 0000 0000 0010 0 −0.9996338 00 0000 0000 0011 10 0000 0000 0011 0 −0.9995117 00 0000 0000 0100 10 0000 0000 0100 0 .... .... .... 0 −0.0002441 01 1111 1111 1110 11 1111 1111 1110 0 −0.0001221 01 1111 1111 1111 11 1111 1111 1111 0 0 10 0000 0000 0000 00 0000 0000 0000 0 +0.0001221 10 0000 0000 0001 00 0000 0000 0001 0 +0.0002441 10 0000 0000 0010 00 0000 0000 0010 0 .... .... .... 0 +0.9995117 11 1111 1111 1011 01 1111 1111 1011 0 +0.9996338 11 1111 1111 1100 01 1111 1111 1100 0 +0.9997559 11 1111 1111 1101 01 1111 1111 1101 0 +0.9998779 11 1111 1111 1110 01 1111 1111 1110 0 +1 11 1111 1111 1111 01 1111 1111 1111 0 > +1 11 1111 1111 1111 01 1111 1111 1111 1 ADC1412D065_080_105_125_2 Objective data sheet © NXP B.V. 2009. All rights reserved. Rev. 02 — 4 June 2009 24 of 37 ADC1412D065/080/105/125 NXP Semiconductors Dual 14-bit ADC 65, 80, 105 or 125 Msps 11.6 Timings summary 11.6.1 CMOS mode timings N N+1 td(s) N+2 tclk CLKP CLKM tPD (N − 14) (N − 13) (N − 12) (N − 11) DATA tPD th tsu DAV tclk 005aaa060 Fig 26. CMOS mode timing 11.6.2 LVDS DDR mode timing N N+1 td(s) N+2 tclk CLKP CLKM tPD DAx_DAx + 1_P/ DBx_DBx + 1_P DAx_DAx + 1_M/ DBx_DBx + 1_M DAx/ DBx DAx+1/ DBx+1 (N − 14) DAx/ DBx DAx+1/ DBx+1 (N − 13) DAx/ DBx tsu th tsu th DAx+1/ DBx+1 (N − 12) DAx/ DBx DAx+1/ DBx+1 (N − 11) DAx/ DBx DAx+1/ DBx+1 tPD DAVP DAVM tclk 005aaa114 Fig 27. LDVS DDR mode timing ADC1412D065_080_105_125_2 Objective data sheet © NXP B.V. 2009. All rights reserved. Rev. 02 — 4 June 2009 25 of 37 ADC1412D065/080/105/125 NXP Semiconductors Dual 14-bit ADC 65, 80, 105 or 125 Msps 11.7 Serial Peripheral Interface (SPI) 11.7.1 Register Description The ADC1412D serial interface is a synchronous serial communications port that allows for easy interfacing with many commonly-used microprocessors. It provides access to the registers that control the operation of the chip. This interface is configured as a 3-wire type (SDIO as bidirectional pin) Pin SCLK is the serial clock input and CS is the chip select pin. Each read/write operation is initiated by a LOW level on CS. A minimum of three bytes will be transmitted (two instruction bytes and at least one data byte). The number of data bytes is determined by the value of bits W1 and W2 (see Table 16). Table 15. Instruction bytes for the SPI MSB LSB Bit 7 6 5 4 3 2 1 0 Description R/W[1] W1[2] W0[2] A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 [1] Bit R/W indicates whether it is a read (1) or a write (0) operation. [2] Bits W1 and W0 indicate the number of bytes to be transferred after the instruction byte (see Table 16). Table 16. Number of data bytes to be transferred after the instruction bytes W1 W0 Number of bytes transmitted 0 0 1 byte 0 1 2 bytes 1 0 3 bytes 1 1 4 bytes or more Bits A12 to A0 indicate the address of the register being accessed. In the case of a multiple byte transfer, this address is the first register to be accessed. An address counter is incriminated to access subsequent addresses. The steps involved in a data transfer are as follows: 1. A falling edge on CS in combination with a rising edge on SCLK determine the start of communications. 2. The first phase is the transfer of the 2-byte instruction. 3. The second phase is the transfer of the data which can vary in length but will always be a multiple of 8 bits. The MSB is always sent first (for instruction and data bytes). 4. A rising edge on CS indicates the end on data transmission. ADC1412D065_080_105_125_2 Objective data sheet © NXP B.V. 2009. All rights reserved. Rev. 02 — 4 June 2009 26 of 37 ADC1412D065/080/105/125 NXP Semiconductors Dual 14-bit ADC 65, 80, 105 or 125 Msps CS SCLK SDIO R/W W1 W0 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 Instruction bytes A0 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 Register N (data) Register N + 1 (data) 005aaa062 Fig 28. SPI mode timing 11.7.2 Default modes at start-up During circuit initialization, it doesn’t matter which output data standard has been selected. At power-up, the device defaults to PIN control mode. A falling edge on CS will trigger a transition to SPI control mode. When the ADC1412D enters SPI control mode, the output data standard (CMOS/LVDS DDR) is determined by the level on pin SDIO (see Figure 29). Once in SPI control mode, the output data standard can be changed via bit LVDS/CMOS in Table 22. When the ADC1412D enters SPI control mode, the output data format (2’s complement or offset binary) is determined by the level on pin SCLK (grey code can only be selected via the SPI). Once in SPI control mode, the output data format can be changed via bit DATA_FORMAT in Table 22. CS SCLK (Data Format) SDIO (CMOS LVDS DDR) Offset binary, LVDS DDR default mode at startup 005aaa063 Fig 29. Default mode at start-up: SCLK LOW = offset binary; SDIO HIGH = LVDS DDR CS SCLK (Data Format) SDIO (CMOS LVDS DDR) 2's complement, CMOS default mode at startup 005aaa064 Fig 30. Default mode at start-up: SCLK HIGH = 2’s complement; SDIO LOW = CMOS ADC1412D065_080_105_125_2 Objective data sheet © NXP B.V. 2009. All rights reserved. Rev. 02 — 4 June 2009 27 of 37 ADC1412D065/080/105/125 NXP Semiconductors Dual 14-bit ADC 65, 80, 105 or 125 Msps 11.7.3 Register allocation map Table 17. Register allocation map Addr Register name Hex R/W Bit definition 0003 Channel index Bit 7 Default Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Bin R/W - - - - - - ADCB ADCA 0000 0011 0005 Reset and operating mode R/W SW_ RST - - - - - OP_MODE 0006 Clock R/W - - - SE_SEL DIFF/SE - CLKDIV 0008 Internal reference R/W - - - - INTREF_ EN INTREF 0011 Output data standard. R/W - - - LVDS/ CMOS OUTBUF - 0012 Output clock R/W - - - - DAVINV DAVPHASE 0013 Offset R/W - - DIG_OFFSET 0014 Test pattern 1 R/W - - - 0015 Test pattern 2 R/W TESTPAT_USER 0016 Test pattern 2 R/W TESTPAT_USER 0017 Fast OTR R/W - - - - FASTOTR 0020 CMOS output R/W - - - - DAV_DRV 0021 LVDS DDR O/P 1 R/W - - - DAVI 0022 LVDS DDR O/P 2 R/W - - Table 18. Bit - 0000 0000 DCS_EN 0000 0001 0000 0000 DATA_FORMAT 0000 0000 0000 1110 0000 0000 - TESTPAT_SEL 0000 0000 0000 0000 - - - - FASTOTR_DET 0000 0000 0000 0000 DATA_DRV 0000 1110 DATAI 0000 0000 BIT/BYTE_ LVDS_INTTER WISE 0000 0000 - Channel index control register (address 0003h) bit description Symbol Access Value Description 7 to 2 reserved 1 0 ADCB ADCA R/W next SPI command for ADC B 0 ADC B not selected 1 ADC B selected R/W next SPI command for ADC A 0 ADC A not selected 1 ADC A selected ADC1412D065_080_105_125_2 Objective data sheet © NXP B.V. 2009. All rights reserved. Rev. 02 — 4 June 2009 28 of 37 ADC1412D065/080/105/125 NXP Semiconductors Dual 14-bit ADC 65, 80, 105 or 125 Msps Table 19. Reset and operating mode control register (address 0005h) bit description Bit Symbol Access 7 SW_RST R/W Value Description reset digital section 0 no reset 1 performs a reset of the digital section 6 to 2 reserved 1 to 0 OP_MODE Table 20. Bit R/W operating mode 00 normal (Power-up) 01 Power-down 10 Sleep 11 normal (Power-up) Clock control register (address 0006h) bit description Symbol Access Value Description R/W single-ended clock input pin select 7 to 5 reserved 4 3 SE_SEL DIFF/SE 2 reserved 1 CLKDIV 0 CLKM 1 CLKP R/W differential/single ended clock input select 0 fully differential 1 single-ended R/W clock input divide by 2 0 disabled 1 0 DCS_EN Table 21. Bit R/W enabled duty cycle stabilizer 0 disabled 1 enabled Internal reference control register (address 0008h) bit description Symbol Access Value Description 7 to 4 reserved 3 INTREF_EN R/W programmable internal reference enable 0 disable 1 active ADC1412D065_080_105_125_2 Objective data sheet © NXP B.V. 2009. All rights reserved. Rev. 02 — 4 June 2009 29 of 37 ADC1412D065/080/105/125 NXP Semiconductors Dual 14-bit ADC 65, 80, 105 or 125 Msps Table 21. Bit Internal reference control register (address 0008h) bit description …continued Symbol 2 to 0 INTREF Table 22. Bit Access Value R/W Description programmable internal reference 000 0 dB (FS = 2 V) 001 −1 dB (FS = 1.78 V) 010 −2 dB (FS = 1.59 V) 011 −3 dB (FS = 1.42 V) 100 −4 dB (FS = 1.26 V) 101 −5 dB (FS = 1.12 V) 110 −6 dB (FS = 1 V) 111 reserved Output data standard control register (address 0011h) bit description Symbol Access Value Description 7 to 5 reserved 4 3 2 LVDS/CMOS OUTBUF output data standard: LVDS DDR or CMOS 0 CMOS 1 LVDS DDR R/W output buffers enable 0 output enabled 1 output disabled (high Z) reserved 1 to 0 DATA_FORMAT Table 23. Bit R/W R/W output data format 00 offset binary 01 2’s complement 10 gray code 11 offset binary Output clock register (address 0012h) bit description Symbol Access Value Description 7 to 4 reserved 3 DAVINV R/W output clock data valid (DAV) polarity 0 normal 1 2 to 0 DAVPHASE R/W inverted DAV phase select 000 output clock shifted (ahead) by 3 ns 001 output clock shifted (ahead) by 2.5 ns 010 output clock shifted (ahead) by 2 ns 011 output clock shifted (ahead) by 1.5 ns 100 output clock shifted (ahead) by 1 ns 101 output clock shifted (ahead) by 0.5 ns 110 default value as defined in timing section 111 output clock shifted (delayed) by 0.5 ns ADC1412D065_080_105_125_2 Objective data sheet © NXP B.V. 2009. All rights reserved. Rev. 02 — 4 June 2009 30 of 37 ADC1412D065/080/105/125 NXP Semiconductors Dual 14-bit ADC 65, 80, 105 or 125 Msps Table 24. Bit Offset register (address 0013h) bit description Symbol Access Value Description 7 to 6 reset 5 to 0 DIG_OFFSET R/W digital offset adjustment 011111 +31 LSB ... ... 000000 0 ... ... −32 LSB 100000 Table 25. Bit Test pattern register 1(address 0014h) bit description Symbol Access Value Description R/W digital test pattern select 7 to 3 reserved 2 to 0 TESTPAT_SEL Table 26. Bit 7 to 0 TESTPAT_USER Bit off 001 mid scale 010 −FS 011 +FS 100 toggle ‘1111..1111’/’0000..0000’ 101 custom test pattern 110 ‘1010..1010.’ 111 ‘010..1010’ Test pattern register 2 (address 0015h) bit description Symbol Table 27. 000 Access Value Description R/W custom digital test pattern (bits 13 to 6) Test pattern register 3 (address 0016h) bit description Symbol 7 to 2 TESTPAT_USER Access Value Description R/W custom digital test pattern (bits 5 to 0) 1 to 0 reserved Table 28. Bit Fast OTR register (address 0017h) bit description Symbol Access Value Description R/W fast Out-of-Range (OTR) detection 7 to 4 reset 3 FASTOTR 0 disabled 1 enabled ADC1412D065_080_105_125_2 Objective data sheet © NXP B.V. 2009. All rights reserved. Rev. 02 — 4 June 2009 31 of 37 ADC1412D065/080/105/125 NXP Semiconductors Dual 14-bit ADC 65, 80, 105 or 125 Msps Table 28. Bit Fast OTR register (address 0017h) bit description …continued Symbol 2 to 0 FASTOTR_DET Table 29. Bit Access Value Description R/W set fast OTR detect level 000 −20.56 dB 001 −16.12 dB 010 −11.02 dB 011 −7.82 dB 100 −5.49 dB 101 −3.66 dB 110 −2.14 dB 111 −0.86 dB CMOS output register (address 0020h) bit description Symbol Access Value Description 7 to 4 reserved 3 to 2 DAV_DRV 1 to 0 DATA_DRV Table 30. Bit R/W drive strength for DAV CMOS output buffer 00 low 01 medium 10 high 11 very high R/W drive strength for DATA CMOS output buffer 00 low 01 medium 10 high 11 very high LVDS DDR output register 1 (address 0021h) bit description Symbol Access Value Description 7 to 5 reserved 4 to 3 DAVI 2 R/W LVDS current for DAV LVDS buffer 00 3.5 mA 01 4.5 mA 10 1.25 mA 11 2.5 mA reserved 1 to 0 DATAI R/W LVDS current for DATA LVDS buffer 00 3.5 mA 01 4.5 mA 10 1.25 mA 11 2.5 mA ADC1412D065_080_105_125_2 Objective data sheet © NXP B.V. 2009. All rights reserved. Rev. 02 — 4 June 2009 32 of 37 ADC1412D065/080/105/125 NXP Semiconductors Dual 14-bit ADC 65, 80, 105 or 125 Msps Table 31. Bit LVDS DDR output register 2 (address 0022h) bit description Symbol Access Value Description 7 to 4 reserved 3 BIT/BYTE_WISE R/W 2 to 0 LVDS_INTTER DDR mode for LVDS output 0 bit wise (even data bits output on DAV rising edge / odd data bits output on DAV falling edge) 1 byte wise (MSB data bits output on DAV rising edge / LSB data bits output on DAV falling edge) R/W internal termination for LVDS buffer (DAV and DATA) 000 no internal termination 001 300 Ω 010 180 Ω 011 110 Ω 100 150 Ω 101 100 Ω 110 81 Ω 111 60 Ω 11.7.4 Serial timing interface SPI timing is shown in Figure 31. tsu tsu th CS tw(SCLKL) th tw(SCLKH) tw(SCLK) SCLK SDIO R/W W1 W0 A12 A11 D2 D1 D0 005aaa065 Fig 31. SPI timing SPI timing characteristics are detailed in Table 9. ADC1412D065_080_105_125_2 Objective data sheet © NXP B.V. 2009. All rights reserved. Rev. 02 — 4 June 2009 33 of 37 ADC1412D065/080/105/125 NXP Semiconductors Dual 14-bit ADC 65, 80, 105 or 125 Msps 12. Package outline HVQFN64: plastic thermal enhanced very thin quad flat package; no leads; 64 terminals; body 9 x 9 x 0.85 mm B D SOT804-3 A terminal 1 index area E A A1 c detail X e1 1/2 e e L 17 32 C C A B C v w b y1 C y 33 16 e e2 Eh 1/2 e 1 terminal 1 index area 48 64 49 X Dh 0 2.5 scale Dimensions Unit mm 5 mm A A1 b max 1.00 0.05 0.30 nom 0.85 0.02 0.21 min 0.80 0.00 0.18 c D(1) Dh E(1) Eh 0.2 9.1 9.0 8.9 7.25 7.10 6.95 9.1 9.0 8.9 7.25 7.10 6.95 e e1 0.5 7.5 e2 L v 7.5 0.5 0.4 0.3 0.1 w y 0.05 0.05 y1 0.1 Note 1. Plastic or metal protrusions of 0.075 mm maximum per side are not included. References Outline version IEC JEDEC JEITA SOT804-6 --- --- --- sot804-3_po European projection Issue date 09-02-23 09-02-24 Fig 32. Package outline SOT804-3 (HVQFN64) ADC1412D065_080_105_125_2 Objective data sheet © NXP B.V. 2009. All rights reserved. Rev. 02 — 4 June 2009 34 of 37 ADC1412D065/080/105/125 NXP Semiconductors Dual 14-bit ADC 65, 80, 105 or 125 Msps 13. Revision history Table 32. Revision history Document ID Release date ADC1412D065_080_105_125_2 20090604 Modifications: • Data sheet status Change notice Supersedes Objective data sheet - ADC1412D065_080_105_125_1 - - Values in Table 7 have been updated. ADC1412D065_080_105_125_1 20090528 Objective data sheet ADC1412D065_080_105_125_2 Objective data sheet © NXP B.V. 2009. All rights reserved. Rev. 02 — 4 June 2009 35 of 37 ADC1412D065/080/105/125 NXP Semiconductors Dual 14-bit ADC 65, 80, 105 or 125 Msps 14. Legal information 14.1 Data sheet status Document status[1][2] Product status[3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification. [1] Please consult the most recently issued document before initiating or completing a design. [2] The term ‘short data sheet’ is explained in section “Definitions”. [3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com. 14.2 Definitions Draft — The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet — A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. 14.3 Disclaimers General — Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use — NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk. Applications — Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Limiting values — Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) may cause permanent damage to the device. Limiting values are stress ratings only and operation of the device at these or any other conditions above those given in the Characteristics sections of this document is not implied. Exposure to limiting values for extended periods may affect device reliability. Terms and conditions of sale — NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, including those pertaining to warranty, intellectual property rights infringement and limitation of liability, unless explicitly otherwise agreed to in writing by NXP Semiconductors. In case of any inconsistency or conflict between information in this document and such terms and conditions, the latter will prevail. No offer to sell or license — Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. Export control — This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from national authorities. 14.4 Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. 15. Contact information For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: [email protected] ADC1412D065_080_105_125_2 Objective data sheet © NXP B.V. 2009. All rights reserved. Rev. 02 — 4 June 2009 36 of 37 NXP Semiconductors ADC1412D065/080/105/125 Dual 14-bit ADC 65, 80, 105 or 125 Msps 16. Contents 1 2 3 4 5 6 6.1 6.1.1 6.1.2 6.2 6.2.1 6.2.2 7 8 9 10 10.1 10.2 10.3 11 11.1 11.1.1 11.1.2 11.1.3 11.1.4 11.2 11.2.1 11.2.2 11.2.3 11.3 11.3.1 11.3.2 11.3.3 11.3.4 11.4 11.4.1 11.4.2 11.4.3 11.4.4 11.5 11.5.1 11.5.2 11.5.3 11.5.4 11.5.5 11.5.6 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Pinning information . . . . . . . . . . . . . . . . . . . . . . 4 CMOS outputs selected . . . . . . . . . . . . . . . . . . 4 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4 LVDS/DDR outputs selected. . . . . . . . . . . . . . . 6 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 7 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 8 Thermal characteristics. . . . . . . . . . . . . . . . . . . 8 Static characteristics. . . . . . . . . . . . . . . . . . . . . 8 Dynamic characteristics . . . . . . . . . . . . . . . . . 11 Dynamic Characteristics . . . . . . . . . . . . . . . . . 11 Clock and Digital Output Timing . . . . . . . . . . . 12 SPI Timings . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Application information. . . . . . . . . . . . . . . . . . 14 Device control . . . . . . . . . . . . . . . . . . . . . . . . . 14 SPI and PIN control modes . . . . . . . . . . . . . . 14 Operating mode selection. . . . . . . . . . . . . . . . 14 Selecting the output data standard . . . . . . . . . 14 Selecting the output data format. . . . . . . . . . . 15 Analog inputs . . . . . . . . . . . . . . . . . . . . . . . . . 15 Input stage . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Anti-kickback circuitry . . . . . . . . . . . . . . . . . . . 15 Transformer. . . . . . . . . . . . . . . . . . . . . . . . . . . 16 System reference and power management . . 17 Internal/external references . . . . . . . . . . . . . . 17 Gain control . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Common-mode output voltage (VO(cm)) . . . . . 19 Biasing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Clock input . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Drive modes . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Equivalent input circuit . . . . . . . . . . . . . . . . . . 21 Duty cycle stabilizer . . . . . . . . . . . . . . . . . . . . 22 Clock input divider . . . . . . . . . . . . . . . . . . . . . 22 Digital outputs . . . . . . . . . . . . . . . . . . . . . . . . . 22 Digital output buffers: CMOS mode . . . . . . . . 22 Digital output buffers: LVDS DDR mode . . . . . 23 Data valid (DAV) output clock . . . . . . . . . . . . . 23 Out-of-Range (OTR) . . . . . . . . . . . . . . . . . . . . 23 Digital offset . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Test patterns . . . . . . . . . . . . . . . . . . . . . . . . . . 24 11.5.7 11.6 11.6.1 11.6.2 11.7 11.7.1 11.7.2 11.7.3 11.7.4 12 13 14 14.1 14.2 14.3 14.4 15 16 Output codes versus input voltage . . . . . . . . . Timings summary. . . . . . . . . . . . . . . . . . . . . . CMOS mode timings . . . . . . . . . . . . . . . . . . . LVDS DDR mode timing. . . . . . . . . . . . . . . . . Serial Peripheral Interface (SPI). . . . . . . . . . . Register Description. . . . . . . . . . . . . . . . . . . . Default modes at start-up. . . . . . . . . . . . . . . . Register allocation map . . . . . . . . . . . . . . . . . Serial timing interface. . . . . . . . . . . . . . . . . . . Package outline . . . . . . . . . . . . . . . . . . . . . . . . Revision history . . . . . . . . . . . . . . . . . . . . . . . Legal information . . . . . . . . . . . . . . . . . . . . . . Data sheet status . . . . . . . . . . . . . . . . . . . . . . Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . Contact information . . . . . . . . . . . . . . . . . . . . Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 25 25 25 26 26 27 28 33 34 35 36 36 36 36 36 36 37 Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. © NXP B.V. 2009. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: [email protected] Date of release: 4 June 2009 Document identifier: ADC1412D065_080_105_125_2