74CBTLV1G125 Single bus switch Rev. 01 — 2 February 2007 Product data sheet 1. General description The 74CBTLV1G125 is a high-performance, low-power, low-voltage, Si-gate CMOS device, superior to most advanced CMOS compatible TTL families. Schmitt trigger action at control input makes the circuit tolerant to slower input rise and fall times across the entire VCC range from 2.3 V to 3.6 V. This device is fully specified for partial power-down applications using IOFF. The IOFF circuitry disables the output, preventing the damaging backflow current through the device when it is powered down. The 74CBTLV1G125 provides a single high-speed line switch. The switch is disabled when the output enable (OE) input is high. To ensure the high-impedance OFF-state during power up or power down, OE should be tied to the VCC through a pullup resistor. The minimum value of the resistor is determined by the current-sinking capability of the driver. 2. Features ■ Supply voltage range from 2.3 V to 3.6 V ■ High noise immunity ■ Complies with JEDEC standard: ◆ JESD8-5 (2.3 V to 2.7 V) ◆ JESD8-B/JESD36 (2.7 V to 3.6 V). ■ ESD protection: ◆ HBM JESD22-A114-D exceeds 2000 V ◆ MM JESD22-A115-A exceeds 200 V ◆ CDM JESD22-C101-C exceeds 1000 V ■ 5 Ω switch connection between two ports ■ Rail to rail switching on data I/O ports ■ CMOS low power consumption ■ Latch-up performance meets requirements of JESD78 Class I ■ IOFF circuitry provides partial power down mode operation ■ Multiple package options ■ Specified from −40 °C to +85 °C and −40 °C to +125 °C 74CBTLV1G125 NXP Semiconductors Single bus switch 3. Ordering information Table 1. Ordering information Type number Package Temperature range Name Description Version 74CBTLV1G125GW −40 °C to +125 °C TSSOP5 plastic thin shrink small outline package; 5 leads; body width 1.25 mm SOT353-1 74CBTLV1G125GV −40 °C to +125 °C SC-74A plastic surface-mounted package; 5 leads SOT753 74CBTLV1G125GM −40 °C to +125 °C XSON6 plastic extremely thin small outline package; no leads; SOT886 6 terminals; body 1 × 1.45 × 0.5 mm 74CBTLV1G125GF −40 °C to +125 °C XSON6 plastic extremely thin small outline package; no leads; SOT891 6 terminals; body 1 × 1 × 0.5 mm 4. Marking Table 2. Marking Type number Marking code 74CBTLV1G125GW bM 74CBTLV1G125GV b25 74CBTLV1G125GM bM 74CBTLV1G125GF bM 5. Functional diagram A OE 2 SWITCH 4 A OE 1 Fig 1. Logic symbol 001aad713 001aad714 Fig 2. Logic diagram 74CBTLV1G125 Product data sheet B B © NXP B.V. 2007. All rights reserved. Rev. 01 — 2 February 2007 2 of 18 74CBTLV1G125 NXP Semiconductors Single bus switch 6. Pinning information 6.1 Pinning 74CBTLV1G125 74CBTLV1G125 OE 1 A 2 GND 3 5 VCC OE 1 6 VCC A 2 5 n.c. GND 4 3 B 4 74CBTLV1G125 B OE 1 6 VCC A 2 5 n.c. GND 3 4 B 001aad717 001aaf817 Transparent top view Transparent top view 001aad715 Fig 3. Pin configuration SOT353-1 and SOT753 Fig 4. Pin configuration SOT886 Fig 5. Pin configuration SOT891 6.2 Pin description Table 3. Pin description Symbol Pin Description SOT353-1/SOT753 SOT886/SOT891 OE 1 1 output enable input OE (active LOW) A 2 2 data input or output A GND 3 3 ground (0 V) B 4 4 data input or output B n.c. - 5 not connected VCC 5 6 supply voltage 7. Functional description 7.1 Function table Table 4. Function table[1] Output enable input OE Function switch L ON-state H OFF-state [1] H = HIGH voltage level; L = LOW voltage level; 74CBTLV1G125 Product data sheet © NXP B.V. 2007. All rights reserved. Rev. 01 — 2 February 2007 3 of 18 74CBTLV1G125 NXP Semiconductors Single bus switch 8. Limiting values Table 5. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V). Symbol Parameter VCC supply voltage Conditions Min Max Unit −0.5 +4.6 V VI input voltage −0.5 +4.6 V VSW switch voltage enable and disable mode −0.5 VCC + 0.5 V IIK input clamping current VI/O < −0.5 V - −50 mA ISK switch clamping current VI < −0.5 V or VI > VCC + 0.5 V - ±50 mA ISW switch current VSW = 0 V to VCC - ±128 mA ICC supply current - +50 mA IGND ground current −50 - mA Tstg storage temperature −65 +150 °C - 250 mW [1] Tamb = −40 °C to +125 °C total power dissipation Ptot [2] [1] The minimum input and output voltage ratings may be exceeded if the input and output current ratings are observed. [2] For TSSOP5 and SC-74A packages: above 87.5 °C the value of Ptot derates linearly with 4.0 mW/K. For XSON6 packages: above 45 °C the value of Ptot derates linearly with 2.4 mW/K. 9. Recommended operating conditions Table 6. Recommended operating conditions Symbol Parameter VCC supply voltage VI input voltage VSW switch voltage Tamb ambient temperature ∆t/∆V [1] Conditions enable and disable mode input transition rise and fall rate [1] VCC = 2.3 V to 3.6 V Min Max Unit 2.3 3.6 V 0 3.6 V 0 VCC V −40 +125 °C 0 20 ns/V Applies to control signal levels. 10. Static characteristics Table 7. Static characteristics At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter Conditions Min Typ[1] Max Unit VCC = 2.3 V to 2.7 V 1.7 - - V VCC = 2.7 V to 3.6 V 2.0 - - V VCC = 2.3 V to 2.7 V - - 0.7 V VCC = 2.7 V to 3.6 V - - 0.8 V Tamb = −40 °C to +85 °C VIH VIL HIGH-level input voltage LOW-level input voltage II input leakage current VI = GND to VCC; VCC = 3.6 V - - ±1.0 µA IS(OFF) OFF-state leakage current VI = VIH or VIL; VO = VCC − GND; VCC = 3.6 V; see Figure 6 - ±0.1 ±5 µA IS(ON) ON-state leakage current VI = VIH or VIL; VCC = 3.6 V; see Figure 7 - ±0.1 ±5 µA 74CBTLV1G125 Product data sheet © NXP B.V. 2007. All rights reserved. Rev. 01 — 2 February 2007 4 of 18 74CBTLV1G125 NXP Semiconductors Single bus switch Table 7. Static characteristics …continued At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter Conditions Min Typ[1] Max Unit IOFF power-off leakage current VI or VO = 0 V to 3.6 V; VCC = 0 V - - ±10 µA ICC supply current VI = GND or VCC; IO = 0 A; VCC = 3.6 V - - 10 µA ∆ICC additional supply current control input; VI = VCC − 0.6 V; VCC = 3.6 V - - 300 µA CI input capacitance control input; VI = 0 V or 3 V - 2.5 - pF Csw switch capacitance OFF-state - 7.0 - pF ON-state - 10.3 - pF VCC = 2.3 V to 2.7 V 1.7 - - V VCC = 2.7 V to 3.6 V 2.0 - - V VCC = 2.3 V to 2.7 V - - 0.7 V VCC = 2.7 V to 3.6 V - - 0.8 V [2] Tamb = −40 °C to +125 °C HIGH-level input voltage VIH LOW-level input voltage VIL II input leakage current VI = GND to VCC; VCC = 3.6 V - - ±100 µA IS(OFF) OFF-state leakage current VI = VIH or VIL; VO = VCC − GND; VCC = 3.6 V; see Figure 6 - - ±200 µA IS(ON) ON-state leakage current VI = VIH or VIL; VCC = 3.6 V; see Figure 7 - - ±200 µA IOFF power-off leakage current VI or VO = 0 V to 3.6 V; VCC = 0 V - - ±10 µA ICC supply current VI = GND or VCC; IO = 0 A; VCC = 3.6 V - - 200 µA ∆ICC additional supply current control input; VI = VCC − 0.6 V; VCC = 3.6 V - - 5000 µA [1] Typical values are measured at Tamb = 25 °C and at VCC = 3.3 V. [2] One input at 3 V, other inputs at VCC or GND. [2] Table 8. Resistance RON At recommended operating conditions; voltages are referenced to GND (ground = 0 V); see test circuit Figure 8. Symbol Parameter RON −40 °C to +85 °C Conditions −40 °C to +125 °C Unit Min Typ[1] Max Min Max ISW = 64 mA; VI = 0 V - 4.7 10 - 15.0 Ω ISW = 24 mA; VI = 0 V - 4.5 10 - 15.0 Ω ISW = 15 mA; VI = 1.7 V - 11 25 - 38.0 Ω ISW = 64 mA; VI = 0 V - 4.2 7 - 11.0 Ω ISW = 24 mA; VI = 0 V - 4.1 7 - 11.0 Ω ISW = 15 mA; VI = 2.4 V - 7.3 15 - 25.5 Ω ON resistance VCC = 2.3 V; see Figure 9 [2] VCC = 3.0 V; see Figure 10 [1] Typical values are measured at Tamb = 25 °C. [2] Measured by the voltage drop between the A and B terminals at the indicated current through the switch. ON-state resistance is determined by the lower of the voltages of the two (A or B) terminals 74CBTLV1G125 Product data sheet © NXP B.V. 2007. All rights reserved. Rev. 01 — 2 February 2007 5 of 18 74CBTLV1G125 NXP Semiconductors Single bus switch VCC VCC OE VIH IS OE VIL A B IS IS VO VI A B n.c. VI GND GND 001aad716 001aad718 Fig 6. Test circuit for measuring OFF-state leakage current Fig 7. Test circuit for measuring ON-state leakage current VSW VCC OE VIL B A ISW VI GND 001aad729 RON = VSW / ISW. Fig 8. Test circuit for measuring ON-resistance 74CBTLV1G125 Product data sheet © NXP B.V. 2007. All rights reserved. Rev. 01 — 2 February 2007 6 of 18 74CBTLV1G125 NXP Semiconductors Single bus switch 001aad732 16 RON (Ω) 001aad733 16 RON (Ω) 12 12 (1) 8 (1) 8 (2) (2) (3) (3) (4) 4 (4) 4 0 0 0 1 2 3 0 VSW (V) 1 2 3 VSW (V) (1) Tamb = 125 °C (1) Tamb = 125 °C (2) Tamb = 85 °C (2) Tamb = 85 °C (3) Tamb = 25 °C (3) Tamb = 25 °C (4) Tamb = −40 °C (4) Tamb = −40 °C a. VCC = 2.5 V; ISW = 15 mA; VSW = 1.7 V b. VCC = 2.5 V; ISW = 24 mA; VSW = 0 V 001aad734 14 RON (Ω) 10 (1) (2) (3) 6 (4) 2 0 1 2 3 VSW (V) (1) Tamb = 125 °C (2) Tamb = 85 °C (3) Tamb = 25 °C (4) Tamb = −40 °C c. VCC = 2.5 V; ISW = 64 mA; VSW = 0 V Fig 9. Switch ON-resistance as a function of input voltage at VCC = 2.5 V 74CBTLV1G125 Product data sheet © NXP B.V. 2007. All rights reserved. Rev. 01 — 2 February 2007 7 of 18 74CBTLV1G125 NXP Semiconductors Single bus switch 001aad737 11 RON (Ω) 001aad736 11 RON (Ω) 9 9 7 7 (1) (1) (2) (2) 5 5 (3) (3) (4) (4) 3 3 0 1 2 3 4 0 1 VSW (V) 2 3 4 VSW (V) (1) Tamb = 125 °C (1) Tamb = 125 °C (2) Tamb = 85 °C (2) Tamb = 85 °C (3) Tamb = 25 °C (3) Tamb = 25 °C (4) Tamb = −40 °C (4) Tamb = −40 °C a. VCC = 3.3 V; ISW = 15 mA; VSW = 2.4 V b. VCC = 3.3 V; ISW = 24 mA; VSW = 0 V 001aad735 10 RON (Ω) 8 (1) (2) 6 (3) 4 (4) 2 0 1 2 3 4 VSW (V) (1) Tamb = 125 °C (2) Tamb = 85 °C (3) Tamb = 25 °C (4) Tamb = −40 °C c. VCC = 3.3 V; ISW = 64 mA; VSW = 0 V Fig 10. Switch ON-resistance as a function of input voltage at VCC = 3.3 V 74CBTLV1G125 Product data sheet © NXP B.V. 2007. All rights reserved. Rev. 01 — 2 February 2007 8 of 18 74CBTLV1G125 NXP Semiconductors Single bus switch 11. Dynamic characteristics Table 9. Dynamic characteristics GND = 0 V; see Figure 13 Symbol Parameter −40 °C to +85 °C Conditions Min Max Min Max - - 0.21 - 0.32 ns - 0.16 0.25 - 0.39 ns 1.0 2.50 4.00 1.0 5.00 ns 1.0 2.05 4.00 1.0 5.00 ns VCC = 2.3 V to 2.7 V 1.0 2.80 5.00 1.0 6.30 ns VCC = 3.0 V to 3.6 V 1.0 3.40 4.10 1.0 5.40 ns VCC = 2.3 V to 2.7 V VCC = 3.0 V to 3.6 V enable time ten OE to A or B; see Figure 12; RL = 500 Ω [4] VCC = 2.3 V to 2.7 V VCC = 3.0 V to 3.6 V disable time tdis Unit [2][3] propagation delay A to B or B to A; see Figure 11; RL = ∞ tpd −40 °C to +125 °C Typ[1] OE to A or B; see Figure 12; RL = 500 Ω [5] [1] All typical values are measured at Tamb = 25 °C and at nominal VCC. [2] The propagation delay is the calculated RC time constant of the maximum on-state resistance of the switch and the load capacitance, when driven by an ideal voltage source (zero output impedance). [3] tpd is the same as tPLH and tPHL. [4] ten is the same as tPZH and tPZL. [5] tdis is the same as tPHZ and tPLZ. 12. Waveforms VI A or B input VM VM GND t PLH t PHL VOH B or A output VM VM VOL 001aad719 Measurement points are given in Table 10. Logic levels: VOL and VOH are typical output voltage drop that occur with the output load. Fig 11. The data input (A or B) to output (B or A) propagation delays Table 10. Measurement points Supply voltage Output Inputs VCC VM VM VI tr = tf 2.3 V to 3.6 V 0.5 × VCC 0.5 × VCC VCC ≤ 2.0 ns 74CBTLV1G125 Product data sheet © NXP B.V. 2007. All rights reserved. Rev. 01 — 2 February 2007 9 of 18 74CBTLV1G125 NXP Semiconductors Single bus switch VI OE input VM GND t PLZ A or B output LOW-to-OFF OFF-to-LOW t PZL VCC VM VX VOL t PHZ VOH t PZH VY output A or B HIGH-to-OFF OFF-to-HIGH VM GND switch enabled switch disabled switch enabled 001aad720 Measurement points are given in Table 11. Logic levels: VOL and VOH are typical output voltage drop that occur with the output load. Fig 12. enable and disable times Table 11. Measurement points Supply voltage Input Output VCC VM VM VX VY 2.3 V to 2.7 V 0.5VCC 0.5VCC VOL + 0.15 V VOH − 0.15 V 3.0 V to 3.6 V 0.5VCC 0.5VCC VOL + 0.3 V VOH − 0.3 V 74CBTLV1G125 Product data sheet © NXP B.V. 2007. All rights reserved. Rev. 01 — 2 February 2007 10 of 18 74CBTLV1G125 NXP Semiconductors Single bus switch VEXT VCC PULSE GENERATOR VI RL VO DUT RT CL RL mna616 Test data is given in Table 12. Definitions for test circuit: RL = Load resistance. CL = Load capacitance including jig and probe capacitance. RT = Termination resistance should be equal to the output impedance Zo of the pulse generator. VEXT = Test voltage for switching times. Fig 13. Load circuitry for switching times Table 12. Test data Supply voltage Load VEXT VCC CL tPLH, tPHL tPZH, tPHZ tPZL, tPLZ 2.3 V to 2.7 V 30 pF open GND 2 × VCC 3.0 V to 3.6 V 50 pF open GND 2 × VCC 74CBTLV1G125 Product data sheet © NXP B.V. 2007. All rights reserved. Rev. 01 — 2 February 2007 11 of 18 74CBTLV1G125 NXP Semiconductors Single bus switch 13. Package outline TSSOP5: plastic thin shrink small outline package; 5 leads; body width 1.25 mm E D SOT353-1 A X c y HE v M A Z 5 4 A2 A (A3) A1 θ 1 Lp 3 L e w M bp detail X e1 0 1.5 3 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max. A1 A2 A3 bp c D(1) E(1) e e1 HE L Lp v w y Z(1) θ mm 1.1 0.1 0 1.0 0.8 0.15 0.30 0.15 0.25 0.08 2.25 1.85 1.35 1.15 0.65 1.3 2.25 2.0 0.425 0.46 0.21 0.3 0.1 0.1 0.60 0.15 7° 0° Note 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. OUTLINE VERSION SOT353-1 REFERENCES IEC JEDEC JEITA MO-203 SC-88A EUROPEAN PROJECTION ISSUE DATE 00-09-01 03-02-19 Fig 14. Package outline SOT353-1 (TSSOP5) 74CBTLV1G125 Product data sheet © NXP B.V. 2007. All rights reserved. Rev. 01 — 2 February 2007 12 of 18 74CBTLV1G125 NXP Semiconductors Single bus switch Plastic surface-mounted package; 5 leads SOT753 D E B y A X HE 5 v M A 4 Q A A1 c 1 2 3 Lp detail X bp e w M B 0 1 2 mm scale DIMENSIONS (mm are the original dimensions) UNIT A A1 bp c D E e HE Lp Q v w y mm 1.1 0.9 0.100 0.013 0.40 0.25 0.26 0.10 3.1 2.7 1.7 1.3 0.95 3.0 2.5 0.6 0.2 0.33 0.23 0.2 0.2 0.1 OUTLINE VERSION REFERENCES IEC SOT753 JEDEC JEITA SC-74A EUROPEAN PROJECTION ISSUE DATE 02-04-16 06-03-16 Fig 15. Package outline SOT753 74CBTLV1G125 Product data sheet © NXP B.V. 2007. All rights reserved. Rev. 01 — 2 February 2007 13 of 18 74CBTLV1G125 NXP Semiconductors Single bus switch XSON6: plastic extremely thin small outline package; no leads; 6 terminals; body 1 x 1.45 x 0.5 mm SOT886 b 1 2 3 4× (2) L L1 e 6 5 4 e1 e1 6× A (2) A1 D E terminal 1 index area 0 1 2 mm scale DIMENSIONS (mm are the original dimensions) UNIT A (1) max A1 max b D E e e1 L L1 mm 0.5 0.04 0.25 0.17 1.5 1.4 1.05 0.95 0.6 0.5 0.35 0.27 0.40 0.32 Notes 1. Including plating thickness. 2. Can be visible in some manufacturing processes. OUTLINE VERSION SOT886 REFERENCES IEC JEDEC JEITA EUROPEAN PROJECTION ISSUE DATE 04-07-15 04-07-22 MO-252 Fig 16. Package outline SOT886 (XSON6) 74CBTLV1G125 Product data sheet © NXP B.V. 2007. All rights reserved. Rev. 01 — 2 February 2007 14 of 18 74CBTLV1G125 NXP Semiconductors Single bus switch XSON6: plastic extremely thin small outline package; no leads; 6 terminals; body 1 x 1 x 0.5 mm 1 SOT891 b 3 2 L L1 e 6 5 4 e1 e1 A A1 D E terminal 1 index area 0 1 2 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max A1 max b D E e e1 L L1 mm 0.5 0.04 0.20 0.12 1.05 0.95 1.05 0.95 0.55 0.35 0.35 0.27 0.40 0.32 OUTLINE VERSION REFERENCES IEC JEDEC JEITA EUROPEAN PROJECTION ISSUE DATE 05-03-11 05-04-06 SOT891 Fig 17. Package outline SOT891 (XSON6) 74CBTLV1G125 Product data sheet © NXP B.V. 2007. All rights reserved. Rev. 01 — 2 February 2007 15 of 18 74CBTLV1G125 NXP Semiconductors Single bus switch 14. Abbreviations Table 13: Abbreviations Acronym Description CDM Charged Device Model CMOS Complementary Metal Oxide Semiconductor DUT Device Under Test ESD ElectroStatic Discharge HBM Human Body Model MM Machine Model TTL Transistor-Transistor Logic 15. Revision history Table 14. Revision history Document ID Release date Data sheet status Change notice Supersedes 74CBTLV1G125_1 20070202 Product data sheet - - 74CBTLV1G125 Product data sheet © NXP B.V. 2007. All rights reserved. Rev. 01 — 2 February 2007 16 of 18 74CBTLV1G125 NXP Semiconductors Single bus switch 16. Legal information 16.1 Data sheet status Document status[1][2] Product status[3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification. [1] Please consult the most recently issued document before initiating or completing a design. [2] The term ‘short data sheet’ is explained in section “Definitions”. [3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com. 16.2 Definitions Draft — The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet — A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. 16.3 Disclaimers General — Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use — NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or malfunction of a NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk. Applications — Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Limiting values — Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) may cause permanent damage to the device. Limiting values are stress ratings only and operation of the device at these or any other conditions above those given in the Characteristics sections of this document is not implied. Exposure to limiting values for extended periods may affect device reliability. Terms and conditions of sale — NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, including those pertaining to warranty, intellectual property rights infringement and limitation of liability, unless explicitly otherwise agreed to in writing by NXP Semiconductors. In case of any inconsistency or conflict between information in this document and such terms and conditions, the latter will prevail. No offer to sell or license — Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. 16.4 Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. 17. Contact information For additional information, please visit: http://www.nxp.com For sales office addresses, send an email to: [email protected] 74CBTLV1G125 Product data sheet © NXP B.V. 2007. All rights reserved. Rev. 01 — 2 February 2007 17 of 18 74CBTLV1G125 NXP Semiconductors Single bus switch 18. Contents 1 2 3 4 5 6 6.1 6.2 7 7.1 8 9 10 11 12 13 14 15 16 16.1 16.2 16.3 16.4 17 18 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2 Pinning information . . . . . . . . . . . . . . . . . . . . . . 3 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3 Functional description . . . . . . . . . . . . . . . . . . . 3 Function table . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 4 Recommended operating conditions. . . . . . . . 4 Static characteristics. . . . . . . . . . . . . . . . . . . . . 4 Dynamic characteristics . . . . . . . . . . . . . . . . . . 9 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 12 Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Revision history . . . . . . . . . . . . . . . . . . . . . . . . 16 Legal information. . . . . . . . . . . . . . . . . . . . . . . 17 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 17 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Contact information. . . . . . . . . . . . . . . . . . . . . 17 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. © NXP B.V. 2007. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: [email protected] Date of release: 2 February 2007 Document identifier: 74CBTLV1G125