PHILIPS 74LVC1G10GF

74LVC1G10
Single 3-input NAND gate
Rev. 01 — 2 October 2007
Product data sheet
1. General description
The 74LVC1G10 provides a low-power, low-voltage single 3-input NAND gate.
The inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of
this device in a mixed 3.3 V and 5 V environment.
Schmitt trigger action at all inputs makes the circuit tolerant to slower input rise and fall
time.
This device is fully specified for partial power-down applications using IOFF.
The IOFF circuitry disables the output, preventing the damaging backflow current through
the device when it is powered down.
2. Features
■ Wide supply voltage range from 1.65 V to 5.5 V
■ High noise immunity
■ Complies with JEDEC standard:
◆ JESD8-7 (1.65 V to 1.95 V)
◆ JESD8-5 (2.3 V to 2.7 V)
◆ JESD8-B/JESD36 (2.7 V to 3.6 V).
■ ±24 mA output drive (VCC = 3.0 V)
■ CMOS low power consumption
■ Latch-up performance exceeds 250 mA
■ Direct interface with TTL levels
■ Inputs accept voltages up to 5 V
■ ESD protection:
◆ HBM JESD22-A114E exceeds 2000 V
◆ MM JESD22-A115-A exceeds 200 V
◆ CDM JESD22-C101-C exceeds 1000 V
■ Multiple package options
■ Specified from −40 °C to +85 °C and −40 °C to +125 °C
74LVC1G10
NXP Semiconductors
Single 3-input NAND gate
3. Ordering information
Table 1.
Ordering information
Type number
Package
Temperature range Name
Description
Version
74LVC1G10GW
−40 °C to +125 °C
SC-88
plastic surface-mounted package; 6 leads
SOT363
74LVC1G10GV
−40 °C to +125 °C
SC-74
plastic surface-mounted package (TSOP6); 6 leads
SOT457
74LVC1G10GM
−40 °C to +125 °C
XSON6
plastic extremely thin small outline package;
no leads; 6 terminals; body 1 × 1.45 × 0.5 mm
SOT886
74LVC1G10GF
−40 °C to +125 °C
XSON6
plastic extremely thin small outline package;
no leads; 6 terminals; body 1 × 1 × 0.5 mm
SOT891
4. Marking
Table 2.
Marking
Type number
Marking code
74LVC1G10GW
YM
74LVC1G10GV
YM
74LVC1G10GM
YM
74LVC1G10GF
YM
5. Functional diagram
A
B
C
1
A
4
3
Y
6
001aag686
Fig 1. Logic symbol
1
3
6
&
B
001aag687
Fig 2. IEC logic symbol
74LVC1G10_1
Product data sheet
Y
4
C
001aag688
Fig 3. Logic diagram
© NXP B.V. 2007. All rights reserved.
Rev. 01 — 2 October 2007
2 of 14
74LVC1G10
NXP Semiconductors
Single 3-input NAND gate
6. Pinning information
6.1 Pinning
74LVC1G10
74LVC1G10
A
1
6
A
1
6
C
GND
2
5
VCC
C
GND
2
5
VCC
B
3
4
Y
B
3
4
Y
74LVC1G10
A
1
6
C
GND
2
5
VCC
B
3
4
Y
001aag690
001aag691
Transparent top view
Transparent top view
001aag689
Fig 4. Pin configuration SOT363
and SOT457
Fig 5. Pin configuration SOT886
Fig 6. Pin configuration SOT891
6.2 Pin description
Table 3.
Pin description
Symbol
Pin
Description
A
1
data input
GND
2
ground (0 V)
B
3
data input
Y
4
data output
VCC
5
supply voltage
C
6
data input
7. Functional description
Table 4.
Function table[1]
Input
Output
A
B
C
Y
H
H
H
L
L
X
X
H
X
L
X
H
X
X
L
H
[1]
H = HIGH voltage level;
L = LOW voltage level;
X = don’t care.
74LVC1G10_1
Product data sheet
© NXP B.V. 2007. All rights reserved.
Rev. 01 — 2 October 2007
3 of 14
74LVC1G10
NXP Semiconductors
Single 3-input NAND gate
8. Limiting values
Table 5.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol
Parameter
VCC
supply voltage
IIK
input clamping current
VI
input voltage
IOK
output clamping current
output voltage
VO
IO
output current
ICC
supply current
IGND
ground current
Ptot
total power dissipation
Tstg
storage temperature
Conditions
VI < 0 V
[1]
Min
Max
Unit
−0.5
+6.5
V
−50
-
mA
−0.5
+6.5
V
-
±50
mA
Active mode
[1][2]
−0.5
VCC + 0.5
V
Power-down mode
[1][2]
−0.5
+6.5
V
-
±50
mA
-
100
mA
−100
-
mA
-
250
mW
−65
+150
°C
VO > VCC or VO < 0 V
VO = 0 V to VCC
Tamb = −40 °C to +125 °C
[3]
[1]
The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
[2]
When VCC = 0 V (Power-down mode), the output voltage can be 5.5 V in normal operation.
[3]
For SC-88 and SC-74A packages: above 87.5 °C the value of Ptot derates linearly with 4.0 mW/K.
For XSON6 packages: above 45 °C the value of Ptot derates linearly with 2.4 mW/K.
9. Recommended operating conditions
Table 6.
Recommended operating conditions
Symbol
Parameter
VCC
Min
Typ
Max
Unit
supply voltage
1.65
-
5.5
V
VI
input voltage
0
-
5.5
V
VO
output voltage
Tamb
ambient temperature
∆t/∆V
input transition rise and fall rate
Conditions
Active mode
0
-
VCC
V
Power-down mode; VCC = 0 V
0
-
5.5
V
−40
-
+125
°C
VCC = 1.65 V to 2.7 V
-
-
20
ns/V
VCC = 2.7 V to 5.5 V
-
-
10
ns/V
74LVC1G10_1
Product data sheet
© NXP B.V. 2007. All rights reserved.
Rev. 01 — 2 October 2007
4 of 14
74LVC1G10
NXP Semiconductors
Single 3-input NAND gate
10. Static characteristics
Table 7.
Static characteristics
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol Parameter
HIGH-level input
voltage
VIH
LOW-level input
voltage
VIL
VOH
HIGH-level
output voltage
−40 °C to +85 °C
Conditions
VCC = 1.65 V to 1.95 V
Min
Max
Min
Max
Unit
0.65VCC
-
-
0.65VCC
-
V
VCC = 2.3 V to 2.7 V
1.7
-
-
1.7
-
V
VCC = 2.7 V to 3.6 V
2.0
-
-
2.0
-
V
VCC = 4.5 V to 5.5 V
0.7VCC
-
-
0.7VCC
-
V
VCC = 1.65 V to 1.95 V
-
-
0.35VCC
-
VCC = 2.3 V to 2.7 V
-
-
0.7
-
0.7
V
VCC = 2.7 V to 3.6 V
-
-
0.8
-
0.8
V
VCC = 4.5 V to 5.5 V
-
-
0.3VCC
-
0.3VCC
V
VCC − 0.1
-
-
VCC − 0.1
-
V
1.2
-
-
0.95
-
V
0.35VCC V
VI = VIH or VIL
IO = −100 µA;
VCC = 1.65 V to 5.5 V
IO = −4 mA; VCC = 1.65 V
IO = −8 mA; VCC = 2.3 V
1.9
-
-
1.7
-
V
IO = −12 mA; VCC = 2.7 V
2.2
-
-
1.9
-
V
IO = −24 mA; VCC = 3.0 V
2.3
-
-
2.0
-
V
IO = −32 mA; VCC = 4.5 V
3.8
-
-
3.4
-
V
-
-
0.10
-
0.10
V
-
-
0.45
-
0.70
V
LOW-level output VI = VIH or VIL
voltage
IO = 100 µA;
VCC = 1.65 V to 5.5 V
VOL
−40 °C to +125 °C
Typ[1]
IO = 4 mA; VCC = 1.65 V
IO = 8 mA; VCC = 2.3 V
-
-
0.30
-
0.45
V
IO = 12 mA; VCC = 2.7 V
-
-
0.40
-
0.60
V
IO = 24 mA; VCC = 3.0 V
-
-
0.55
-
0.80
V
IO = 32 mA; VCC = 4.5 V
-
-
0.55
-
0.80
V
II
input leakage
current
VI = 5.5 V or GND;
VCC = 0 V to 5.5 V
-
±0.1
±5
-
±100
µA
IOFF
power-off
leakage current
VI or VO = 5.5 V; VCC = 0 V
-
±0.1
±10
-
±200
µA
ICC
supply current
VI = 5.5 V or GND; IO = 0 A;
VCC = 1.65 V to 5.5 V
-
0.1
10
-
200
µA
∆ICC
additional supply VI = VCC − 0.6 V; IO = 0 A;
current
VCC = 2.3 V to 5.5 V; per pin
-
5
500
-
5000
µA
CI
input
capacitance
-
3
-
-
-
pF
[1]
VCC = 3.3 V;
VI = GND to VCC
All typical values are measured at Tamb = 25 °C.
74LVC1G10_1
Product data sheet
© NXP B.V. 2007. All rights reserved.
Rev. 01 — 2 October 2007
5 of 14
74LVC1G10
NXP Semiconductors
Single 3-input NAND gate
11. Dynamic characteristics
Table 8.
Dynamic characteristics
Voltages are referenced to GND (ground = 0 V). For test circuit see Figure 8.
Symbol Parameter
−40 °C to +85 °C
Conditions
Min
Max
Min
Max
VCC = 1.65 V to 1.95 V
1.5
4.7
18.0
1.5
21.5
ns
VCC = 2.3 V to 2.7 V
1.0
3.0
6.5
1.0
7.8
ns
VCC = 2.7 V
1.0
3.0
6.0
1.0
7.5
ns
VCC = 3.0 V to 3.6 V
1.0
2.6
5.0
1.0
6.2
ns
VCC = 4.5 V to 5.5 V
1.0
1.9
3.6
1.0
4.4
ns
-
12
-
-
-
pF
[2]
propagation delay A, B and C to Y; see Figure 7
tpd
power dissipation
capacitance
CPD
−40 °C to +125 °C Unit
Typ[1]
[3]
VI = GND to VCC; VCC = 3.3 V
[1]
Typical values are measured at Tamb = 25 °C and VCC = 1.8 V, 2.5 V, 2.7 V, 3.3 V and 5.0 V respectively.
[2]
tpd is the same as tPLH and tPHL.
[3]
CPD is used to determine the dynamic power dissipation (PD in µW).
PD = CPD × VCC2 × fi × N + Σ(CL × VCC2 × fo) where:
fi = input frequency in MHz;
fo = output frequency in MHz;
CL = output load capacitance in pF;
VCC = supply voltage in V;
N = number of inputs switching;
Σ(CL × VCC2 × fo) = sum of the outputs.
12. Waveforms
VI
A, B, C,
input
VM
GND
tPLH
tPHL
VOH
VM
Y output
VOL
001aag692
Measurement points are given in Table 9.
VOL and VOH are typical output voltage levels that occur with the output load.
Fig 7. The input (A, B, C) to output (Y) propagation delays
74LVC1G10_1
Product data sheet
© NXP B.V. 2007. All rights reserved.
Rev. 01 — 2 October 2007
6 of 14
74LVC1G10
NXP Semiconductors
Single 3-input NAND gate
Table 9.
Measurement points
Supply voltage
Input
Output
VCC
VM
VM
1.65 V to 1.95 V
0.5VCC
0.5VCC
2.3 V to 2.7 V
0.5VCC
0.5VCC
2.7 V
1.5 V
1.5 V
3.0 V to 3.6 V
1.5 V
1.5 V
4.5 V to 5.5 V
0.5VCC
0.5VCC
VEXT
VCC
VI
RL
VO
G
DUT
RT
CL
RL
mna616
Test data is given in Table 10.
Definitions for test circuit:
RL = Load resistance.
CL = Load capacitance including jig and probe capacitance.
RT = Termination resistance should be equal to the output impedance Zo of the pulse generator.
VEXT = External voltage for measuring switching times.
Fig 8. Load circuit for switching times
Table 10.
Test data
Supply voltage
Input
Load
VEXT
VCC
VI
tr = t f
CL
RL
tPLH, tPHL
1.65 V to 1.95 V
VCC
≤ 2.0 ns
30 pF
1 kΩ
open
2.3 V to 2.7 V
VCC
≤ 2.0 ns
30 pF
500 Ω
open
2.7 V
2.7 V
≤ 2.5 ns
50 pF
500 Ω
open
3.0 V to 3.6 V
2.7 V
≤ 2.5 ns
50 pF
500 Ω
open
4.5 V to 5.5 V
VCC
≤ 2.5 ns
50 pF
500 Ω
open
74LVC1G10_1
Product data sheet
© NXP B.V. 2007. All rights reserved.
Rev. 01 — 2 October 2007
7 of 14
74LVC1G10
NXP Semiconductors
Single 3-input NAND gate
13. Package outline
Plastic surface-mounted package; 6 leads
SOT363
D
E
B
y
X
A
HE
6
5
v M A
4
Q
pin 1
index
A
A1
1
2
e1
3
bp
c
Lp
w M B
e
detail X
0
1
2 mm
scale
DIMENSIONS (mm are the original dimensions)
UNIT
A
A1
max
bp
c
D
E
e
e1
HE
Lp
Q
v
w
y
mm
1.1
0.8
0.1
0.30
0.20
0.25
0.10
2.2
1.8
1.35
1.15
1.3
0.65
2.2
2.0
0.45
0.15
0.25
0.15
0.2
0.2
0.1
OUTLINE
VERSION
REFERENCES
IEC
SOT363
JEDEC
JEITA
SC-88
EUROPEAN
PROJECTION
ISSUE DATE
04-11-08
06-03-16
Fig 9. Package outline SOT363 (SC-88)
74LVC1G10_1
Product data sheet
© NXP B.V. 2007. All rights reserved.
Rev. 01 — 2 October 2007
8 of 14
74LVC1G10
NXP Semiconductors
Single 3-input NAND gate
Plastic surface-mounted package (TSOP6); 6 leads
D
SOT457
E
B
y
A
HE
6
X
v M A
4
5
Q
pin 1
index
A
A1
c
1
2
3
Lp
bp
e
w M B
detail X
0
1
2 mm
scale
DIMENSIONS (mm are the original dimensions)
UNIT
A
A1
bp
c
D
E
e
HE
Lp
Q
v
w
y
mm
1.1
0.9
0.1
0.013
0.40
0.25
0.26
0.10
3.1
2.7
1.7
1.3
0.95
3.0
2.5
0.6
0.2
0.33
0.23
0.2
0.2
0.1
OUTLINE
VERSION
REFERENCES
IEC
SOT457
JEDEC
JEITA
SC-74
EUROPEAN
PROJECTION
ISSUE DATE
05-11-07
06-03-16
Fig 10. Package outline SOT457 (SC-74)
74LVC1G10_1
Product data sheet
© NXP B.V. 2007. All rights reserved.
Rev. 01 — 2 October 2007
9 of 14
74LVC1G10
NXP Semiconductors
Single 3-input NAND gate
XSON6: plastic extremely thin small outline package; no leads; 6 terminals; body 1 x 1.45 x 0.5 mm
SOT886
b
1
2
3
4×
(2)
L
L1
e
6
5
4
e1
e1
6×
A
(2)
A1
D
E
terminal 1
index area
0
1
2 mm
scale
DIMENSIONS (mm are the original dimensions)
UNIT
A (1)
max
A1
max
b
D
E
e
e1
L
L1
mm
0.5
0.04
0.25
0.17
1.5
1.4
1.05
0.95
0.6
0.5
0.35
0.27
0.40
0.32
Notes
1. Including plating thickness.
2. Can be visible in some manufacturing processes.
OUTLINE
VERSION
SOT886
REFERENCES
IEC
JEDEC
JEITA
EUROPEAN
PROJECTION
ISSUE DATE
04-07-15
04-07-22
MO-252
Fig 11. Package outline SOT886 (XSON6)
74LVC1G10_1
Product data sheet
© NXP B.V. 2007. All rights reserved.
Rev. 01 — 2 October 2007
10 of 14
74LVC1G10
NXP Semiconductors
Single 3-input NAND gate
XSON6: plastic extremely thin small outline package; no leads; 6 terminals; body 1 x 1 x 0.5 mm
1
SOT891
b
3
2
4×
(1)
L
L1
e
6
5
4
e1
e1
6×
A
(1)
A1
D
E
terminal 1
index area
0
1
2 mm
scale
DIMENSIONS (mm are the original dimensions)
UNIT
A
max
A1
max
b
D
E
e
e1
L
L1
mm
0.5
0.04
0.20
0.12
1.05
0.95
1.05
0.95
0.55
0.35
0.35
0.27
0.40
0.32
Note
1. Can be visible in some manufacturing processes.
OUTLINE
VERSION
REFERENCES
IEC
JEDEC
JEITA
EUROPEAN
PROJECTION
ISSUE DATE
05-04-06
07-05-15
SOT891
Fig 12. Package outline SOT891 (XSON6)
74LVC1G10_1
Product data sheet
© NXP B.V. 2007. All rights reserved.
Rev. 01 — 2 October 2007
11 of 14
74LVC1G10
NXP Semiconductors
Single 3-input NAND gate
14. Abbreviations
Table 11.
Abbreviations
Acronym
Description
CDM
Charged Device Model
CMOS
Complementary Metal Oxide Semiconductor
DUT
Device Under Test
ESD
ElectroStatic Discharge
HBM
Human Body Model
MM
Machine Model
TTL
Transistor-Transistor Logic
15. Revision history
Table 12.
Revision history
Document ID
Release date
Data sheet status
Change notice
Supersedes
74LVC1G10_1
20071002
Product data sheet
-
-
74LVC1G10_1
Product data sheet
© NXP B.V. 2007. All rights reserved.
Rev. 01 — 2 October 2007
12 of 14
74LVC1G10
NXP Semiconductors
Single 3-input NAND gate
16. Legal information
16.1 Data sheet status
Document status[1][2]
Product status[3]
Definition
Objective [short] data sheet
Development
This document contains data from the objective specification for product development.
Preliminary [short] data sheet
Qualification
This document contains data from the preliminary specification.
Product [short] data sheet
Production
This document contains the product specification.
[1]
Please consult the most recently issued document before initiating or completing a design.
[2]
The term ‘short data sheet’ is explained in section “Definitions”.
[3]
The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.
16.2 Definitions
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liability for the consequences of
use of such information.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is intended
for quick reference only and should not be relied upon to contain detailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall prevail.
16.3 Disclaimers
General — Information in this document is believed to be accurate and
reliable. However, NXP Semiconductors does not give any representations or
warranties, expressed or implied, as to the accuracy or completeness of such
information and shall have no liability for the consequences of use of such
information.
Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
Suitability for use — NXP Semiconductors products are not designed,
authorized or warranted to be suitable for use in medical, military, aircraft,
space or life support equipment, nor in applications where failure or
malfunction of a NXP Semiconductors product can reasonably be expected to
result in personal injury, death or severe property or environmental damage.
NXP Semiconductors accepts no liability for inclusion and/or use of NXP
Semiconductors products in such equipment or applications and therefore
such inclusion and/or use is at the customer’s own risk.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty that such applications will be suitable for the
specified use without further testing or modification.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) may cause permanent
damage to the device. Limiting values are stress ratings only and operation of
the device at these or any other conditions above those given in the
Characteristics sections of this document is not implied. Exposure to limiting
values for extended periods may affect device reliability.
Terms and conditions of sale — NXP Semiconductors products are sold
subject to the general terms and conditions of commercial sale, as published
at http://www.nxp.com/profile/terms, including those pertaining to warranty,
intellectual property rights infringement and limitation of liability, unless
explicitly otherwise agreed to in writing by NXP Semiconductors. In case of
any inconsistency or conflict between information in this document and such
terms and conditions, the latter will prevail.
No offer to sell or license — Nothing in this document may be interpreted
or construed as an offer to sell products that is open for acceptance or the
grant, conveyance or implication of any license under any copyrights, patents
or other industrial or intellectual property rights.
16.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks
are the property of their respective owners.
17. Contact information
For additional information, please visit: http://www.nxp.com
For sales office addresses, send an email to: [email protected]
74LVC1G10_1
Product data sheet
© NXP B.V. 2007. All rights reserved.
Rev. 01 — 2 October 2007
13 of 14
74LVC1G10
NXP Semiconductors
Single 3-input NAND gate
18. Contents
1
2
3
4
5
6
6.1
6.2
7
8
9
10
11
12
13
14
15
16
16.1
16.2
16.3
16.4
17
18
General description . . . . . . . . . . . . . . . . . . . . . . 1
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Ordering information . . . . . . . . . . . . . . . . . . . . . 2
Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2
Pinning information . . . . . . . . . . . . . . . . . . . . . . 3
Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3
Functional description . . . . . . . . . . . . . . . . . . . 3
Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 4
Recommended operating conditions. . . . . . . . 4
Static characteristics. . . . . . . . . . . . . . . . . . . . . 5
Dynamic characteristics . . . . . . . . . . . . . . . . . . 6
Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Package outline . . . . . . . . . . . . . . . . . . . . . . . . . 8
Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Revision history . . . . . . . . . . . . . . . . . . . . . . . . 12
Legal information. . . . . . . . . . . . . . . . . . . . . . . 13
Data sheet status . . . . . . . . . . . . . . . . . . . . . . 13
Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Contact information. . . . . . . . . . . . . . . . . . . . . 13
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
© NXP B.V. 2007.
All rights reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: [email protected]
Date of release: 2 October 2007
Document identifier: 74LVC1G10_1