Philips Semiconductors Product specification PowerMOS transistors Avalanche energy rated PHU2N50E FEATURES QUICK REFERENCE DATA • Repetitive Avalanche Rated • Fast switching • Stable off-state characteristics • High thermal cycling performance • Low thermal resistance • Extremely high dV/dt capability VDSS = 500 V ID = 2 A RDS(ON) ≤ 5 Ω GENERAL DESCRIPTION N-channel, enhancement mode field-effect power transistor, intended for use in Compact Fluorescent Lamps (CFL) and low power ballasts. The PHU2N50E is compatible with self oscillating and IC driven circuits, including the UBA2021 ballast controller IC. Other applications include off line switched mode power supplies and D.C. to D.C. converters. The PHU2N50E is supplied in the SOT533 (I-PAK) leaded package. PINNING SYMBOL PIN DESCRIPTION ------------- --------------------------------1 gate 2 drain 3 source tab SOT533 d g drain 1 s Top view 2 3 MBK915 LIMITING VALUES Limiting values in accordance with the Absolute Maximum System (IEC 134) SYMBOL PARAMETER CONDITIONS VDSS VDGR VGS ID Drain-source voltage Drain-gate voltage Gate-source voltage Continuous drain current Tj = 25 ˚C to 150˚C Tj = 25 ˚C to 150˚C; RGS = 20 kΩ IDM PD dV/dt Pulsed drain current Total dissipation Peak Diode Recovery voltage slope. (See fig. 19) Operating junction and storage temperature range Tj, Tstg May 1999 Tmb = 25 ˚C; VGS = 10 V Tmb = 100 ˚C; VGS = 10 V Tmb = 25 ˚C Tmb = 25 ˚C Ids 2.0 A; dI/dt = 100 A/µs; Vs = 8V; Tj < Tjmax 1 MIN. MAX. UNIT - 500 500 ± 30 2 1.3 8 50 5.2 V V V A A A W V/ns - 55 150 ˚C Rev 1.000 Philips Semiconductors Product specification PowerMOS transistors Avalanche energy rated PHU2N50E AVALANCHE ENERGY LIMITING VALUES Limiting values in accordance with the Absolute Maximum System (IEC 134) SYMBOL PARAMETER EAS EAR IAS, IAR CONDITIONS MIN. MAX. UNIT - 82 mJ - 3.3 mJ - 2 A Non-repetitive avalanche energy Unclamped inductive load, IAS = 1.26 A; tp = 0.2 ms; Tj prior to avalanche = 25˚C; VDD ≤ 50 V; RGS = 50 Ω; VGS = 10 V; refer to fig:17 Repetitive avalanche energy1 IAR = 2 A; tp = 2.5 µs; Tj prior to avalanche = 25˚C; RGS = 50 Ω; VGS = 10 V; refer to fig:18 Repetitive and non-repetitive avalanche current THERMAL RESISTANCES SYMBOL PARAMETER Rth j-mb Rth j-a Thermal resistance junction to mounting base Thermal resistance junction to ambient CONDITIONS MIN. In free air TYP. MAX. UNIT - - 2.5 K/W - 70 - K/W ELECTRICAL CHARACTERISTICS Tj = 25 ˚C unless otherwise specified SYMBOL PARAMETER CONDITIONS MIN. V(BR)DSS VGS = 0 V; ID = 0.25 mA 500 - - V VDS = VGS; ID = 0.25 mA - 0.1 - %/K 2.0 0.5 - 3.1 3.0 1.3 1 77 10 5 4.0 25 250 200 Ω V S µA µA nA Drain-source breakdown voltage ∆V(BR)DSS / Drain-source breakdown ∆Tj voltage temperature coefficient Drain-source on resistance RDS(ON) VGS(TO) Gate threshold voltage gfs Forward transconductance Drain-source leakage current IDSS TYP. MAX. UNIT IGSS VGS = 10 V; ID = 1 A VDS = VGS; ID = 0.25 mA VDS = 30 V; ID = 1 A VDS = 500 V; VGS = 0 V VDS = 500 V; VGS = 0 V; Tj = 125 ˚C Gate-source leakage current VGS = ±30 V; VDS = 0 V Qg(tot) Qgs Qgd Total gate charge Gate-source charge Gate-drain (Miller) charge ID = 2 A; VDD = 400 V; VGS = 10 V - 20 2 12 25 3 15 nC nC nC td(on) tr td(off) tf Turn-on delay time Turn-on rise time Turn-off delay time Turn-off fall time VDD = 250 V; RD = 120 Ω; RG = 24 Ω - 10 20 60 20 - ns ns ns ns Ld Ls Internal drain inductance Internal source inductance Measured from tab to centre of die Measured from source lead to source bond pad - 3.5 7.5 - nH nH Ciss Coss Crss Input capacitance Output capacitance Feedback capacitance VGS = 0 V; VDS = 25 V; f = 1 MHz - 236 40 22 - pF pF pF 1 pulse width and repetition rate limited by Tj max. May 1999 2 Rev 1.000 Philips Semiconductors Product specification PowerMOS transistors Avalanche energy rated PHU2N50E SOURCE-DRAIN DIODE RATINGS AND CHARACTERISTICS Tj = 25 ˚C unless otherwise specified SYMBOL PARAMETER CONDITIONS IS Tmb = 25˚C - - 2 A Tmb = 25˚C - - 8 A VSD Continuous source current (body diode) Pulsed source current (body diode) Diode forward voltage IS = 2 A; VGS = 0 V - - 1.2 V trr Qrr Reverse recovery time Reverse recovery charge IS = 2 A; VGS = 0 V; dI/dt = 100 A/µs - 300 2.1 - ns µC ISM May 1999 MIN. 3 TYP. MAX. UNIT Rev 1.000 Philips Semiconductors Product specification PowerMOS transistors Avalanche energy rated Normalised Power Derating PD% 120 PHU2N50E 10 Zth j-mb / (K/W) 110 D= 100 90 80 1 70 0.5 0.2 60 50 0.1 0.05 40 0.1 30 0.02 20 10 PD tp D= tp T 0 t T 0 0.01 0 20 40 60 80 100 Tmb / C 120 140 10us Fig.1. Normalised power dissipation. PD% = 100⋅PD/PD 25 ˚C = f(Tmb) 0.1s 10ms Fig.4. Transient thermal impedance. Zth j-mb = f(t); parameter D = tp/T Normalised Current Derating ID% 120 1ms t/s 6 PHP2N50 ID, Drain current (Amps) Tj = 25 C 110 100 90 5 20 V 80 4 10 V 70 60 50 3 40 2 7V 6.5 V 30 6V 20 10 1 5.5 V 0 0 VGS = 5 V 0 20 40 60 80 Tmb / C 100 120 140 0 5 Fig.2. Normalised continuous drain current. ID% = 100⋅ID/ID 25 ˚C = f(Tmb); conditions: VGS ≥ 10 V 10 )= Drain-Source on resistance, RDS(ON) (Ohms) 5V 5.5 V 6 V 6.5 V 10 D S/I Tmb = 25 C tp = 10 us VD (ON 25 30 Fig.5. Typical output characteristics. ID = f(VDS); parameter VGS PHP2N50 Drain current, ID (Amps) 10 15 20 VDS, Drain-Source voltage (Volts) S RD PHP2N50 Tj = 25 C 8 7V 100us 1 6 1 ms DC 0.1 10 V 10 ms VGS = 20 V 4 100ms 2 0.01 10 100 Drain-source voltage, VDS (Volts) 0 1000 Fig.3. Safe operating area. Tmb = 25 ˚C ID & IDM = f(VDS); IDM single pulse; parameter tp May 1999 0 1 2 3 Drain current, ID (Amps) 4 5 Fig.6. Typical on-state resistance. RDS(ON) = f(ID); parameter VGS 4 Rev 1.000 Philips Semiconductors Product specification PowerMOS transistors Avalanche energy rated 6 PHU2N50E VGS(TO) / V PHP2N50 Drain current, ID (A) VDS > ID x RDS(on)max max. 4 5 typ. 3 4 min. 3 2 2 1 1 150 C 0 Tj = 25 C 0 0 2 4 6 Gate-source voltage, VGS (V) 8 -60 10 Transconductance, gfs (S) -20 0 20 40 60 Tj / C 80 100 120 140 Fig.10. Gate threshold voltage. VGS(TO) = f(Tj); conditions: ID = 0.25 mA; VDS = VGS Fig.7. Typical transfer characteristics. ID = f(VGS); parameter Tj 2.5 -40 PHP2N50 1E-01 SUB-THRESHOLD CONDUCTION ID / A VDS > ID x RDS(on)max 1E-02 2 Tj = 25 C 2% 1E-03 1.5 typ 98 % 150 C 1 1E-04 0.5 1E-05 0 1E-06 0 1 2 3 4 Drain current, ID (A) 5 0 6 Fig.8. Typical transconductance. gfs = f(ID); parameter Tj 2 VGS / V 3 4 Fig.11. Sub-threshold drain current. ID = f(VGS); conditions: Tj = 25 ˚C; VDS = VGS Normalised RDS(ON) = f(Tj) a 1 1000 PHP2N50 Capacitances, Ciss, Coss, Crss (pF) 2 Ciss 100 Coss 1 10 0 -60 -40 -20 0 20 40 60 Tj / C 80 1 100 120 140 Fig.9. Normalised drain-source on-state resistance. a = RDS(ON)/RDS(ON)25 ˚C = f(Tj); ID = 1 A; VGS = 10 V May 1999 Crss 1 10 100 Drain-source voltage, VDS (V) 1000 Fig.12. Typical capacitances, Ciss, Coss, Crss. C = f(VDS); conditions: VGS = 0 V; f = 1 MHz 5 Rev 1.000 Philips Semiconductors Product specification PowerMOS transistors Avalanche energy rated 20 PHU2N50E Gate-Source voltage, VGS (Volts) ID = 2 A PHP2N50 200 V 15 PHP2N50 Source-drain diode current, IF(A) 10 VGS = 0 V 300 V 8 VDD = 400 V 150 C Tj = 25 C 6 10 4 5 2 0 0 10 20 Gate charge, Qg (nC) 30 0 40 Switching times, td(on), tr, td(off), tf (ns) 0.5 1 Source-Drain voltage, VSDS (V) 1.5 Fig.16. Source-Drain diode characteristic. IF = f(VSDS); parameter Tj Fig.13. Typical turn-on gate-charge characteristics. VGS = f(QG); parameter VDS 1000 0 PHP2N50 VDD = 250V RD = 120 Ohms Tj = 25 C 10 Non-repetitive Avalanche current, IAS (A) Tj prior to avalanche = 25 C 100 1 td(off) 125 C VDS tr tf 10 0.1 tp td(on) 1 ID 0.01 1E-06 0 20 40 60 Gate resistance, RG (Ohms) 80 1E-05 100 1E-04 1E-03 1E-02 Avalanche time, tp (s) Fig.14. Typical switching times; td(on), tr, td(off), tf = f(RG) 1.15 PHP2N50E Fig.17. Maximum permissible non-repetitive avalanche current (IAS) versus avalanche time (tp); unclamped inductive load Normalised Drain-source breakdown voltage V(BR)DSS @ Tj V(BR)DSS @ 25 C 10 1.1 1.05 1 1 0.1 0.95 Maximum Repetitive Avalanche Current, IAR (A) Tj prior to avalanche = 25 C 125 C 0.01 0.9 0.85 -100 PHP2N50E 0.001 1E-06 -50 0 50 Tj, Junction temperature (C) 100 150 1E-04 1E-03 1E-02 Avalanche time, tp (s) Fig.15. Normalised drain-source breakdown voltage; V(BR)DSS/V(BR)DSS 25 ˚C = f(Tj) May 1999 1E-05 Fig.18. Maximum permissible repetitive avalanche current (IAR) versus avalanche time (tp) 6 Rev 1.000 Philips Semiconductors Product specification PowerMOS transistors Avalanche energy rated PHU2N50E dV/dt (V/ns) 7 6.5 6 5.5 5 4.5 4 3.5 3 0.4 0.8 1 5 Ids (A) Fig.19. Peak body recovery voltage dV/dt. The dV/dt = f(IDS). The dI/dt is 100A/µs. May 1999 7 Rev 1.000 Philips Semiconductors Product specification PowerMOS transistors Avalanche energy rated PHU2N50E MECHANICAL DATA Plastic single-ended package (Philips version of I-PAK); 3 leads (in-line) SOT533 E A A1 E1 D1 mounting base D Q L 1 2 e1 3 b c w M e 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT A A1 mm 2.38 2.22 0.89 0.71 OUTLINE VERSION SOT533 b c 0.89 0.56 0.71 0.46 D D1 E E1 7.28 6.94 1.06 0.96 6.73 6.47 5.36 5.26 e L Q 9.8 9.4 1.00 1.10 e1 4.57 2.285 REFERENCES IEC JEDEC EIAJ TO-251 EUROPEAN PROJECTION ISSUE DATE 99-02-18 Fig.20. SOT533 surface mounting package. Pin 2 connected to mounting base. May 1999 8 Rev 1.000 Philips Semiconductors Product specification PowerMOS transistors Avalanche energy rated PHU2N50E DEFINITIONS Data sheet status Objective specification This data sheet contains target or goal specifications for product development. Preliminary specification This data sheet contains preliminary data; supplementary data may be published later. Product specification This data sheet contains final product specifications. Limiting values Limiting values are given in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of this specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Where application information is given, it is advisory and does not form part of the specification. Philips Electronics N.V. 1999 All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, it is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent or other industrial or intellectual property rights. LIFE SUPPORT APPLICATIONS These products are not designed for use in life support appliances, devices or systems where malfunction of these products can be reasonably expected to result in personal injury. Philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such improper use or sale. May 1999 9 Rev 1.000