INTEGRATED CIRCUITS DATA SHEET For a complete data sheet, please also download: • The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications • The IC06 74HC/HCT/HCU/HCMOS Logic Package Information • The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines 74HC/HCT7540 Octal Schmitt trigger buffer/line driver; 3-state; inverting Product specification Supersedes data of March 1988 File under Integrated Circuits, IC06 December 1990 Philips Semiconductors Product specification Octal Schmitt trigger buffer/line driver; 3-state; inverting 74HC/HCT7540 The 74HC/HCT7540 are octal Schmitt trigger inverting buffer/line drivers with 3-state outputs. The 3-state outputs are controlled by the output enable inputs OE1 and OE2. FEATURES • Inverting outputs • Schmitt trigger action on all data inputs A HIGH on OEn causes the outputs to assume a high impedance OFF-state. • Output capability: bus driver • ICC category: MSI The Schmitt trigger action in the data inputs transforms slowly changing input signals into sharply defined jitter-free output signals. GENERAL DESCRIPTION The “7540” is identical to the “540” but has hysteresis on the data inputs. The 74HC/HCT7540 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. QUICK REFERENCE DATA GND = 0 V; Tamb = 25 °C; tr = tf = 6 ns TYPICAL SYMBOL PARAMETER tPHL/ tPLH propagation delay An to Yn CI input capacitance CPD power dissipation capacitance per buffer CONDITIONS CL = 15 pF; VCC = 5 V notes 1 and 2 Notes 1. CPD is used to determine the dynamic power dissipation (PD in µW): PD = CPD × VCC2 × fi + ∑ (CL × VCC2 × fo) where: fi = input frequency in MHz fo = output frequency in MHz ∑ (CL × VCC2 × fo) = sum of outputs CL = output load capacitance in pF VCC = supply voltage in V 2. For HC the condition is VI = GND to VCC For HCT the condition is VI = GND to VCC − 1.5 V ORDERING INFORMATION See “74HC/HCT/HCU/HCMOS Logic Package Information”. December 1990 2 UNIT HC HCT 11 16 ns 3.5 3.5 pF 29 31 pF Philips Semiconductors Product specification Octal Schmitt trigger buffer/line driver; 3-state; inverting 74HC/HCT7540 PIN DESCRIPTION PIN NO. SYMBOL NAME AND FUNCTION 1, 19 OE1, OE2 output enable inputs (active LOW) 2, 3, 4, 5, 6, 7, 8, 9 A0 to A7 data inputs 10 GND ground (0 V) 18, 17, 16, 15, 14, 13, 12, 11 Y0 to Y7 bus outputs 20 VCC positive supply voltage Fig.1 Pin configuration. December 1990 Fig.2 Logic symbol. 3 Fig.3 IEC logic symbol. Philips Semiconductors Product specification Octal Schmitt trigger buffer/line driver; 3-state; inverting 74HC/HCT7540 FUNCTION TABLE INPUTS OUTPUTS OE1 OE2 An Yn L L X H L L H X L H X X H L Z Z Notes 1. H = HIGH voltage level L = LOW voltage level X = don’t care Z = high impedance OFF-state Fig.4 Functional diagram. Fig.5 Logic diagram. December 1990 4 Philips Semiconductors Product specification Octal Schmitt trigger buffer/line driver; 3-state; inverting 74HC/HCT7540 DC CHARACTERISTICS FOR 74HC For the DC characteristics see “74HC/HCT/HCU/HCMOS Logic Family Specifications”. Transfer characteristics are given below (not applicable for OEn inputs). Output capability: bus driver ICC category: MSI AC CHARACTERISTICS FOR 74HC GND = 0 V; tr = tf = 6 ns; CL = 50 pF Tamb (°C) TEST CONDITIONS 74HC SYMBOL PARAMETER +25 −40 to +85 min. typ. max. min. max. −40 to +125 min. UNIT VCC WAVEFORMS (V) max. tPHL/ tPLH propagation delay An to Yn 39 14 11 120 24 20 150 30 26 180 36 31 ns 2.0 4.5 6.0 Fig.8 tPZH/ tPZL 3-state output enable time OEn to Yn 41 15 12 150 30 26 190 38 33 225 45 38 ns 2.0 4.5 6.0 Fig.9 tPHZ/ tPLZ 3-state output disable time OEn to Yn 52 19 15 150 30 26 190 38 33 225 45 38 ns 2.0 4.5 6.0 Fig.9 tTHL/ tTLH output transition time 14 5 4 60 12 10 75 15 13 90 18 15 ns 2.0 4.5 6.0 Fig.8 TRANSFER CHARACTERISTICS FOR 74HC Voltages are referred to GND (ground = 0 V) Tamb (°C) TEST CONDITIONS 74HC SYMBOL PARAMETER +25 min. typ. VT+ positive-going threshold VT− negative-going threshold 0.30 1.35 1.80 VH hysteresis (VT+ − VT−) December 1990 −40 to +85 max. min. max. 1.50 3.15 4.20 0.10 0.25 0.30 −40 to +125 min. 1.50 3.15 4.20 0.20 0.40 0.50 5 UNIT V CC WAVEFORMS (V) max. 1.50 3.15 4.20 V 2.0 4.5 6.0 Figs 6 and 7 0.30 1.35 1.80 0.30 1.35 1.80 V 2.0 4.5 6.0 Figs 6 and 7 0.10 0.25 0.30 0.10 0.25 0.30 V 2.0 4.5 6.0 Figs 6 and 7 Philips Semiconductors Product specification Octal Schmitt trigger buffer/line driver; 3-state; inverting 74HC/HCT7540 DC CHARACTERISTICS FOR 74HCT For the DC characteristics see “74HC/HCT/HCU/HCMOS Logic Family Specifications”. Transfer characteristics are given below (not applicable for OEn inputs). Output capability: bus driver ICC category: MSI Note to HCT types The value of additional quiescent supply current (∆ICC) for a unit load of 1 is given in the family specifications. To determine ∆ICC per input, multiply this value by the unit load coefficient shown in the table below. INPUT UNIT LOAD OE1 OE2 An 1.30 1.30 0.20 AC CHARACTERISTICS FOR 74HCT GND = 0 V; tr = tf = 6 ns; CL = 50 pF Tamb (°C) TEST CONDITIONS 74HCT SYMBOL PARAMETER +25 min −40 to +85 −40 to +125 typ. max. min max. min. max. UNIT V CC WAVEFORMS (V) tPHL/ tPLH propagation delay An to Yn 19 32 40 48 ns 4.5 Fig.8 tPZH/ tPZL 3-state output enable time OEn to Yn 19 32 40 48 ns 4.5 Fig.9 tPHZ/ tPLZ 3-state output disable time OEn to Yn 20 32 40 48 ns 4.5 Fig.9 tTHL/ tTLH output transition time 5 12 15 18 ns 4.5 Fig.8 TRANSFER CHARACTERISTICS FOR 74HCT Voltages are referred to GND (ground = 0 V) Tamb (°C) TEST CONDITIONS 74HCT SYMBOL PARAMETER +25 min typ. max. min max. VT+ positive-going threshold VT− negative-going threshold 0.70 0.80 VH hysteresis (VT+ − VT−) 0.17 0.23 0.17 0.23 December 1990 −40 to +85 2.0 2.1 −40 to +125 min. 2.0 2.1 0.64 0.74 6 max. 2.0 2.1 0.60 0.70 UNIT V CC WAVEFORMS (V) V 4.5 5.5 Figs 6 and 7 V 4.5 5.5 Figs 6 and 7 V 4.5 5.5 Figs 6 and 7 Philips Semiconductors Product specification Octal Schmitt trigger buffer/line driver; 3-state; inverting 74HC/HCT7540 TRANSFER CHARACTERISTIC WAVEFORMS Fig.7 Fig.6 Transfer characteristic. Waveforms showing the definition of VT+, VT− and VH. AC WAVEFORMS (1) HC : VM = 50%; VI = GND to VCC. HCT: VM = 1.3 V; VI = GND to 3 V. Fig.8 Waveforms showing the input (An) to output (Yn) propagation delays and the output transition times. (1) HC : VM = 50%; VI = GND to VCC. HCT: VM = 1.3 V; VI = GND to 3 V. Fig.9 Waveforms showing the 3-state enable and disable times. PACKAGE OUTLINES See “74HC/HCT/HCU/HCMOS Logic Package Outlines”. December 1990 7