INTEGRATED CIRCUITS 74ABT16260/74ABTH16260 12-bit to 24-bit multiplexed D-type latches (3-State) Product specification Supersedes data of 1996 Nov 20 IC23 Data Handbook 1998 Feb 10 Philips Semiconductors Product specification 74ABT16260 74ABTH16260 12-bit to 24-bit multiplexed D-type latches (3-State) FEATURES DESCRIPTION • ESD protection exceeds 2000V per Mil-Std-883C, Method 3015; The 74ABT16260/74ABTH16260 is a 12-bit to 24-bit multiplexed D-type latch used in applications where two separate data paths must be multiplexed onto, or demultiplexed from, a single data path. Typical applications include multiplexing and/or demultiplexing of address and data information in microprocessor or bus-interface applications. This device is alto useful in memory-interleaving applications. exceeds 200V using machine model (C = 200pF, R = 0). • Latch-up performance exceeds 500mA per JEDEC Standard JESD-17. • Distributed VCC and GND pin configuration minimizes high-speed switching noise. • Flow-through architecture optimizes PCB layout. • High-drive outputs (–32mA IOH, 64mA IOL). • 74ABTH16260 incorporates bus-hold inputs which eliminate the Three 12-bit I/O ports (A1–A12, 1B1–1B12, and 2B1–2B12) are available for address and/or data transfer. The output enable (OE1B, OE2B, and OEA) inputs control the bus transceiver functions. The OE1B and OE2B control signals also allow bank control in the A to B direction. need for external pull-up resistors. Address and/or data information can be stored using the internal storage latches. The latch enable (LE1B, LE2B, LEA1B, and LEA2B) inputs are used to control data storage. When the latch enable input is high, the latch is transparent. When the latch enable input goes low, the data present at the inputs is latched and remains latched until the latch enable input is returned high. • Package options: – 56-pin plastic Shrink Small-Outline Package (SSOP) – 56-pin plastic Thin Shrink Small-Outline Package (TSSOP) To ensure the high-impedance state during power-up or power-down, OE should be tied to VCC through a pull-up resistor; the minimum value of the resistor is determined by the current sinking capability of the driver. The 74ABTH incorporates the bus hold feature. The 74ABT does not include bus hold feature. Both parts are available in 56-pin SSOP and TSSOP. QUICK REFERENCE DATA SYMBOL CONDITIONS Tamb = 25°C; GND = 0V PARAMETER tPLH Propagation delay tPHL nAx to nBx CIN Input capacitance TYPICAL UNIT 2.8 CL = 50 pF nBx to nAx 2.5 ns VI = 0 V or VCC 4 pF COUT Output capacitance VI/O = 0 V or 5.0 V 6 pF ICCZ Total supply current Outputs disabled 100 µA ORDERING INFORMATION TEMPERATURE RANGE OUTSIDE NORTH AMERICA NORTH AMERICA DWG NUMBER 56-Pin Plastic SSOP Type III PACKAGES –40°C to +85°C 74ABT16260 DL BT16260 DL SOT371-1 56-Pin Plastic TSSOP Type II –40°C to +85°C 74ABT16260 DGG BT16260 DGG SOT364-1 56-Pin Plastic SSOP Type III –40°C to +85°C 74ABTH16260 DL BH16260 DL SOT371-1 56-Pin Plastic TSSOP Type II –40°C to +85°C 74ABTH16260 DGG BH16260 DGG SOT364-1 PIN DESCRIPTION PIN NUMBER SYMBOL 8, 9, 10, 12, 13, 14, 15, 16, 17, 19, 20, 21 An Data inputs/outputs (A) 23, 24, 26, 31, 33, 34, 36, 37, 38, 40, 41, 42 1Bn Data inputs/outputs (B1) 6, 5, 3, 54, 52, 51, 49, 48, 47, 45, 44, 43 2Bn Data inputs/outputs (B2) 1998 Feb 10 FUNCTION 1, 29, 56 OEA, OE1B, OE2B 2, 27, 30, 55 LE1B, LE2B, LEA1B, LEA2B 2 Output enable input (active low) Latch enable inputs 853-2048-18945 Philips Semiconductors Product specification 74ABT16260 74ABTH16260 12-bit to 24-bit multiplexed D-type latches (3-State) PIN CONFIGURATION FUNCTION TABLES OEA 1 56 OE2B LE1B 2 55 LEA2B 2B3 3 54 2B4 GND 4 53 GND 2B2 5 52 2B5 2B1 6 51 2B6 VCC 7 50 VCC A1 8 49 2B7 A2 9 48 2B8 A3 10 GND 11 B to A (OEB = H) INPUTS 1B 2B SEL LE1B LE2B OEA A H L X X X X X X X X H L X X H H H L L L X H H L X X X X X X X H H L X L L L L L L H H L A0 H L A0 Z 47 2B9 A to B (OEA = H) 46 GND INPUTS OUTPUT A4 12 45 2B10 A5 13 44 2B11 A LEA1B LEA2B OE1B OE2B 1B 2B A6 14 43 2B12 H H H L L H H A7 15 42 1B12 L H H L L L L A8 16 41 1B11 H H L L L H 2B0 A9 17 40 1B10 L H L L L L 2B0 GND 18 39 GND A10 19 38 1B9 H L H L L 1B0 H L L H L L 1B0 L X L L L L 1B0 2B0 A11 20 37 1B8 A12 21 36 1B7 VCC 22 35 VCC X X X H H Z Z 1B1 23 34 1B6 X X X L H Active Z 1B2 24 33 1B5 X X X H L Z Active GND 25 32 GND X X X L L Active Active 1B3 26 31 1B4 LE2B 27 30 LEA1B SEL 28 29 OE1B SA00435 1998 Feb 10 OUTPUT 3 Philips Semiconductors Product specification 12-bit to 24-bit multiplexed D-type latches (3-State) 74ABT16260 74ABTH16260 LOGIC DIAGRAM (POSITIVE LOGIC) LE1B LE2B LEA1B LEA2B OE2B OE1B OEA SEL 2 27 30 55 56 29 1 28 C1 G1 A1 8 1 1D 23 1B1 1 C1 1D 6 2B1 C1 1D C1 1D TO 11 OTHER CHANNELS SA00436 1998 Feb 10 4 Philips Semiconductors Product specification 74ABT16260 74ABTH16260 12-bit to 24-bit multiplexed D-type latches (3-State) ABSOLUTE MAXIMUM RATINGS Over operating free-air temperature range (unless otherwise specified)1 LIMITS SYMBOL PARAMETER CONDITIONS VCC Supply voltage range VI Input voltage range VO Voltage range applied to any output in the high state or power-off state IO Current into any output in the low state IIK Input clamp current IOK Output clamp current see Note 2 Maximum power dissipation at Tamb = 55°C (in still air) Tstg UNIT MIN MAX –0.5 7 V –0.5 7 V –0.5 5.5 V 128 mA VI < 0 –18 mA VO < 0 –50 mA see Note 3 1.4 W +150 °C Storage temperature range –65 NOTES: 1. Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “Recommended Operating Conditions” is not implied. Exposure to absolute maximum rated conditions for extended periods may affect device reliability. 2. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed. 3. The maximum package power dissipation is calculated using a junction temperature of 150°C and a board trace length of 750 mils. RECOMMENDED OPERATING CONDITIONS1 LIMITS SYMBOL PARAMETER MIN MAX 4.5 5.5 VCC Supply voltage VIH High-level input voltage VIL Low-level input voltage VI Input voltage IOH High-level output current IOL Low-level output current ∆t∆/v Input transition rise or fall rate ∆t∆/VCC Power-up ramp rate 200 Tamb Operating free-air temperature –40 2 Outputs enabled NOTE: 1. Unused or floating inputs must be held high or low. 1998 Feb 10 5 V V 0.8 0 UNIT V VCC V –32 mA 64 mA 10 ns/V µs/V +85 °C Philips Semiconductors Product specification 74ABT16260 74ABTH16260 12-bit to 24-bit multiplexed D-type latches (3-State) DC ELECTRICAL CHARACTERISTICS LIMITS SYMBOL PARAMETER Min VIK Input clamp voltage VOH High-level output voltage VOL Low-level output voltage II g current Input leakage VCC = 4.5V; IIK = –18mA Bus Hold current Typ Max –0.8 –1.2 Min UNIT Max –1.2 V VCC = 4.5V; IOH = –3mA; VI = VIL or VIH 2.5 2.9 2.5 V VCC = 5.0V; IOH = –3mA; VI = VIL or VIH 3.0 3.4 3.0 V VCC = 4.5V; IOH = –32mA; VI = VIL or VIH 2.0 VCC = 4.5V; IOL = 64mA; VI = VIL or VIH VCC = 5.5V; VI = VCC or GND Control pins VCC = 5.5V; VI = VCC or GND Data pins VCC = 4.5V; VI = 0.8V IHOLD Tamb = –40°C to +85°C Tamb = +25°C TEST CONDITIONS A or B ports VCC = 4.5V; VI = 2.0V VCC = 5.5V; VI = 0 to 5.5V 2.4 2.0 V 0.42 0.55 0.55 V ±0.01 ±1 ±1 µA ±5 µA ±3 75 75 –75 –75 ±500 ±500 µA Power-off leakage current VCC = 0.0V; VO or VI ≤ 4.5V ±5.0 ±100 ±100 µA Power-up/down 3-State output current VCC = 2.0V; VO = 0.5V; VI = GND or VCC; VOE = VCC ±60 ±200 ±200 µA IOZH 3-State output High current VCC = 5.5V; VO = 2.7V; VI = VIL or VIH 1.0 10 10 µA IOZL 3-State output Low current VCC = 5.5V; VO = 0.5V; VI = VIL or VIH –1.0 –10 –10 µA ICEX Output high leakage current VCC = 5.5V; VO = 5.5V; VI = GND or VCC Output current1 VCC = 5.5V; VO = 2.5V –100 –225 VCC = 5.5V; Outputs High, VI = GND or VCC 0.2 1.5 1.5 VCC = 5.5V; Outputs Low, VI = GND or VCC IOFF IPU/IPD IO ICC ∆ICC Quiescent su supply ly current Additional supply current per input pin2 50 –50 –50 µA mA 8 19 19 VCC = 5.5V; Outputs 3-State; VI = GND or VCC 0.1 1.0 1.0 Outputs enabled, one input at 3.4V, other inputs at VCC or GND; VCC = 5.5V 0.1 1.5 1.5 NOTES: 1. Not more than one output should be tested at a time, and the duration of the test should not exceed one second. 2. This is the increase in supply current for each input that is at the specified TTL voltage level rather than VCC or GND. 3. This is the bus hold minimum overdrive current required to force the input to the opposite logic state. 1998 Feb 10 50 –225 6 mA mA Philips Semiconductors Product specification 74ABT16260 74ABTH16260 12-bit to 24-bit multiplexed D-type latches (3-State) AC ELECTRICAL CHARACTERISTICS Over recommended operating free-air temperature range (unless otherwise noted) PARAMETER SYMBOL tPLH tPHL tPLH tPHL tPLH tPHL tPZH tPZL tPHZ tPLZ VCC = 5V, Tamb = 25°C FROM (INPUT) TO (OUTPUT) A or B B or A Tamb = –40°C to +85°C UNIT MIN TYP MAX MIN MAX 1 2.8 4.8 1 5.6 ns 1 2.5 5 1 5.9 ns 1.1 3.2 4.9 1.1 5.8 ns LE A or B 1.1 3.2 4.9 1.1 5.3 ns SEL (B1) A 1.3 3.2 4.6 1.3 5.3 ns SEL (B2) A 1.1 2.8 4.9 1.1 6 ns SEL (B1) A 1.5 3.0 4.4 1.5 4.4 ns SEL (B2) A 1.6 2.6 5.1 1.6 5.9 ns OE A or B OE A or B 1 2.9 4.7 1 5.7 ns 1.6 2.2 5.1 1.6 5.8 ns 2.2 4.1 5.4 2.2 6.4 ns 1.3 3.2 4.4 1.3 4.8 ns AC SETUP CHARACTERISTICS Over recommended operating free-air temperature range (unless otherwise noted) SYMBOL VCC = 5V, Tamb = 25°C PARAMETER MIN MAX Tamb = –40°C to +85°C MIN MAX UNIT tw Pulse duration, LE1B, LE2B, LEA1B, or LEA2B high 3.3 3.3 ns tsu Setup time, data before LE1B, LE2B, LEA1B, or LEA2B↓ 1.5 1.5 ns th Hold time, data after LE1B, LE2B, LEA1B, or LEA2B↓ 1 1 ns 1998 Feb 10 7 Philips Semiconductors Product specification 74ABT16260 74ABTH16260 12-bit to 24-bit multiplexed D-type latches (3-State) AC WAVEFORMS VM = 1.5V for all waveforms The outputs are measured one at a time with one transition per measurement. 3V VM TIMING INPUT tw 0V 3V INPUT VM tsu VM th 3V 0V DATA INPUT VM VM 0V SA00437 SA00439 Figure 1. Pulse duration Figure 3. Setup and hold times 3V INPUT VM VM tPLH tPHL 3V OUTPUT CONTROL VM VM tPZL tPLZ 0V 0V VOH VM OUTPUT VOL tPHL VM tPZH tPLH VOH VM OUTPUT 3.5V OUTPUT WAVEFORM 1 S1 AT 7V VM VM VOH – 0.3V ≈0V VOL SA00438 SA00440 All input pulses are supplied by generators having the following characteristics: PRR ≤ 10MHz, ZO = 50Ω, tr ≤ 2.5ns, tf ≤ 2.5ns. Figure 2. Propagation delay times; inverting and non-inverting outputs Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. Figure 4. Enable and disable times; low- and high-level enabling TEST LOAD CIRCUIT 7V 500Ω FROM OUTPUT UNDER TEST CL = 50pF (INCLUDES PROBE AND JIG CAPACITANCE) S1 OPEN GND 500Ω Load Circuit for Outputs TEST tPLH/tPHL tPLZ/tPZL tPHZ/tPZH S1 Open 7V Open SA00441 Figure 5. Test load circuit 1998 Feb 10 VOL VOH OUTPUT WAVEFORM 2 S1 AT OPEN VM VOL + 0.3V tPHZ 8 Philips Semiconductors Product specification 12-bit to 24-bit multiplexed D-type latches (3-State) SSOP56: plastic shrink small outline package; 56 leads; body width 7.5 mm 1998 Feb 10 9 74ABT16260 74ABTH16260 SOT371-1 Philips Semiconductors Product specification 12-bit to 24-bit multiplexed D-type latches (3-State) TSSOP56: plastic thin shrink small outline package; 56 leads; body width 6.1mm 1998 Feb 10 10 74ABT16260 74ABTH16260 SOT364-1 Philips Semiconductors Product specification 12-bit to 24-bit multiplexed D-type latches (3-State) NOTES 1998 Feb 10 11 74ABT16260 74ABTH16260 Philips Semiconductors Product specification 12-bit to 24-bit multiplexed D-type latches (3-State) 74ABT16260 74ABTH16260 Data sheet status Data sheet status Product status Definition [1] Objective specification Development This data sheet contains the design target or goal specifications for product development. Specification may change in any manner without notice. Preliminary specification Qualification This data sheet contains preliminary data, and supplementary data will be published at a later date. Philips Semiconductors reserves the right to make chages at any time without notice in order to improve design and supply the best possible product. Product specification Production This data sheet contains final specifications. Philips Semiconductors reserves the right to make changes at any time without notice in order to improve design and supply the best possible product. [1] Please consult the most recently issued datasheet before initiating or completing a design. Definitions Short-form specification — The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook. Limiting values definition — Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information — Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Disclaimers Life support — These products are not designed for use in life support appliances, devices or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application. Right to make changes — Philips Semiconductors reserves the right to make changes, without notice, in the products, including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified. Copyright Philips Electronics North America Corporation 1998 All rights reserved. Printed in U.S.A. Philips Semiconductors 811 East Arques Avenue P.O. Box 3409 Sunnyvale, California 94088–3409 Telephone 800-234-7381 print code Document order number: 1998 Feb 10 12 Date of release: 05-96 9397-750-03339