Philips Semiconductors Low Voltage Products Objective specification 3.3 Volt ABT octal transparent latch (3–State) 74LVT373 • Latch–up protection exceeds 500mA per FEATURES • Designed for use in the 3.3V independently by Enable (E) and Output Enable (OE) control gates. JEDEC JC40.2 Std 17 • ESD protection exceeds 2000 V per MIL high–performance market • Supports mixed–mode signal operation; 5V STD 883 Method 3015 and 200 V per Machine Model input and output voltages with 3.3V VCC • Bus–hold inputs eliminate the need for DESCRIPTION external pull-up resistors to hold unused pins The 74LVT373 device is designed specifically for low–voltage (3.3V) VCC operation, but can provide a TTL interface to a 5V system environment. • Live insertion/extraction permitted • No bus current loading when output is tied to 5V bus The 74LVT373 high-performance BiCMOS device combines zero static and low dynamic power dissipation with high speed and high output drive. • 8–bit transparent latch • 3-State output buffers • Zero-static power dissipation • Pin and function compatibility with ABT • AC and DC performance compatibility with The data on the D inputs are transferred to the latch outputs when the Latch Enable (E) input is High. The latch remains transparent to the data inputs while E is High, and stores the data that is present one setup time before the High-to-Low enable transition. The 3-State output buffers are designed to drive heavily loaded 3-State buses, MOS memories, or MOS microprocessors. The active-Low Output Enable (OE) controls all eight 3-State buffers independent of the latch operation. When OE is Low, the latched or transparent data appears at the outputs. When OE is High, the outputs are in the High-impedance ”OFF” state, which means they will neither drive nor load the bus. The 74LVT373 device is an octal transparent latch coupled to eight 3-State output buffers. The two sections of the device are controlled ABT QUICK REFERENCE DATA SYMBOL CONDITIONS Tamb = 25°C; GND = 0V PARAMETER TYPICAL UNIT 4.2 ns tPLH tPHL Propagation delay Dn to Qn CL = 50pF; VCC = 5V CIN Input capacitance VI = 0V or VCC 4 pF COUT Output capacitance VI = 0V or VCC 7 pF ICCZ Total supply current Outputs disabled; VCC =5.5V 50 µA ORDERING INFORMATION PACKAGES TEMPERATURE RANGE ORDER CODE DRAWING NUMBER 20–Pin Plastic SOL -40°C to +85°C 74LVT373D 0172D 20–Pin Plastic SSOP -40°C to +85°C 74LVT373DB 1640B 20–Pin Plastic TSSOP -40°C to +85°C 74LVT373PW TBD PIN DESCRIPTION PIN NUMBER SYMBOL 1 OE FUNCTION Output enable input (active-Low) 3, 4, 7, 8, 13, 14, 17, 18 D0-D7 Data inputs 2, 5, 6, 9, 12, 15, 16, 19 Q0-Q7 Data outputs July 1993 11 E 10 GND Enable input (active-High) Ground (0V) 20 VCC Positive supply voltage 2 Philips Semiconductors Low Voltage Products Objective specification 3.3 Volt ABT octal transparent latch (3–State) 74LVT373 FUNCTION TABLE INTERNAL OUTPUTS OE INPUTS E Dn REGISTER Q0 – Q7 L L H H L H L H L H Enable and read register L L ↓ ↓ i h L H L H Latch and read register L L X NC NC H H H = h = L = l = NC= X = Z = ↓ = OPERATING MODE Hold L X NC Z Disable outputs H Dn Dn Z High voltage level High voltage level one set-up time prior to the High-to-Low E transition Low voltage level Low voltage level one set-up time prior to the High-to-Low E transition No change Don’t care High impedance “off” state High-to-Low E transition LOGIC DIAGRAM D0 D1 D2 D3 3 4 7 8 D E D Q E D Q E D4 13 D Q D5 14 D E Q D6 E 17 D Q D7 E 18 D Q E D Q E Q 11 E 1 OE July 1993 2 5 6 9 Q0 Q1 Q2 Q3 3 12 Q4 15 Q5 16 Q6 19 Q7 Philips Semiconductors Low Voltage Products Objective specification 3.3 Volt ABT octal transparent latch (3–State) 74LVT373 ABSOLUTE MAXIMUM RATINGS1, 2 SYMBOL VCC IIK PARAMETER CONDITIONS RATING UNIT –0.5 to +4.6 V –18 mA –1.2 to +5.5 V VO < 0 –50 mA output in Off or High state –0.5 to +5.5 V output in Low state 64 mA –65 to 150 °C DC supply voltage DC input diode current VI < 0 voltage3 VI DC input IOK DC output diode current voltage3 VOUT DC output IOUT DC output current Tstg Storage temperature range NOTES: 1. Stresses beyond those listed may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute–maximum–rated conditions for extended periods may affect device reliability. 2. The performance capability of a high–performance integrated circuit in conjunction with its thermal environment can create junction temperatures which are detrimental to reliability. The maximum junction temperature of this integrated circuit should not exceed 150°C. 3. The input and output voltage ratings may be exceeded if the input and output current ratings are observed. RECOMMENDED OPERATING CONDITIONS SYMBOL VCC PARAMETER LIMITS DC supply voltage UNIT Min Max 2.7 3.6 V 0 VCC V VI Input voltage VIH High-level input voltage VIL Input voltage 0.8 V IOH High-level output current –32 mA IOL Low-level output current 64 mA 2.0 V ∆t/∆v Input transition rise or fall rate 0 10 ns/V Tamb Operating free-air temperature range 0 +70 °C July 1993 4 Philips Semiconductors Low Voltage Products Objective specification 3.3 Volt ABT octal transparent latch (3–State) 74LVT373 DC ELECTRICAL CHARACTERISTICS LIMITS SYMBOL PARAMETER TEST CONDITIONS Temp = -40°C to +85°C MIN VIK Input clamp voltage VCC = 2.7V; IIK = –18mA VOL High-level output voltage Low-level output voltage 2.4 VCC = 3.0V; IOH = –32mA 2.0 V VCC = 2.7V; IOL = 100µA 0.2 VCC = 2.7V; IOL = 24mA 0.5 VCC = 3.0V; IOL = 16mA 0.4 VCC = 3.0V; IOL = 32mA 0.5 VCC = 3.0V; IOL = 64mA 0.55 Input leakage current 10 VCC = 3.6V; VI = 5.5V 20 VCC = 3.6V; VI = VCC Data pins4 IHOLD IEX -5 ±100 µA Output off current VCC = 0V; VI or VO = 0 to 4.5V Bus Hold current A VCC = 3V; VI = 0.8V 75 µA or B ports VCC = 3V; VI = 2.0V –75 µA Current into an ouptut in the High state when VO > VCC VO = 5.5V; VCC = 3.0V ICCH ICCL µA 1 VCC = 3.6V; VI = 0 IOFF V ±1 Control pins VCC = 0 or 3.6V; VI = 5.5V II V VCC-0.2 VCC = 2.7V; IOH = –8mA VCC = 3.6V; VI = VCC or GND UNIT MAX –1.2 VCC = 2.7 to 3.6V; IOH = –100µA VOH TYP1 Quiescent supply current ICCZ 100 VCC = 3.6V; Outputs High, VI = GND or VCC, IO = 0 0.13 0.19 VCC = 3.6V; Outputs Low, VI = GND or VCC, IO = 0 3 12 0.13 0.19 VCC = 3.6V; Outputs Disabled; VI = GND or VCC, IO = 0 µA mA Additional supply current per input pin2 VCC = 3V to 3.6V; One input at VCC-0.6V, Other inputs at VCC or GND Power up/down 3-State output current3 VCC ≤ 1.2V; VO = 0.5V to VCC; VI = GND or VCC; OE/OE = X CI Input capacitance VI = 3V or 0 4 pF CO Output capacitance VO = 3V or 0 11 pF ∆ICC IPU/PD 0.2 mA ±100 µA NOTES: 1. All typical values are at VCC = 3.3V and Tamb = 25°C. 2. This is the increase in supply current for each input at the specificed voltage level other than VCC or GND 3. This parameter is valid for any VCC between 0V and 1.3V with a transition time of up to 10msec. From VCC = 1.3V to VCC = 3.3V ± 0.3V a transition time of 100µsec is permitted. X = Don’t care. 4. Unused pins at VCC or GND. July 1993 5 Philips Semiconductors Low Voltage Products Objective specification 3.3 Volt ABT octal transparent latch (3–State) 74LVT373 AC CHARACTERISTICS GND = 0V; tR = tF = 6ns; CL = 50pF; RL = 500Ω, Tamb = –40°C to +85°C. LIMITS SYMBOL PARAMETER VCC = 3.3V ±0.3V WAVEFORM TYP1 MIN VCC = 2.7V MAX UNIT MAX tPLH tPHL Propagation delay An to Yn NO TAG 2.7 2.9 ns tPZH tPZL Output enable time OEn to Yn NO TAG 3.4 3.4 ns tPHZ tPLZ Output disable time OEn to Yn NO TAG 3.7 2.6 ns NOTE: 1. All typical values are at VCC = 3.3V and Tamb = 25°C. AC WAVEFORMS VM = 1.5V, VIN = GND to 3.0V E VM VM tw(H) tPHL VM VM Dn VM tPLH tPHL tPLH Qn Qn VM VM ÉÉÉ ÉÉÉ ÉÉÉ ÉÉÉ ÉÉÉ Waveform 1. Propagation Delay, Enable to Output, and Enable Pulse Width Dn VM ts(H) E VM VM ÉÉÉÉÉÉÉÉÉÉÉ ÉÉÉÉÉÉÉÉÉÉÉ ÉÉÉÉÉÉÉÉÉÉÉ ÉÉÉÉÉÉÉÉÉÉÉ ÉÉÉÉÉÉÉÉÉÉÉ Waveform 2. Propagation Delay for Data to Outputs VM VM VM ts(L) th(H) VM th(L) VM Waveform 3. Data Setup and Hold Times OE VM tPZH Qn OE VM tPHZ VM VM VM tPZL VOH –0.3V Qn tPLZ VM 0V Waveform 4. 3-State Output Enable Time to High Level and Output Disable Time from High Level Waveform 5. 3-State Output Enable Time to Low Level and Output Disable Time from Low Level NOTE: The shaded areas indicate when the input is permitted to change for predictable output performance. July 1993 VOL +0.3V 0V 6 Philips Semiconductors Low Voltage Products Objective specification 3.3 Volt ABT octal transparent latch (3–State) 74LVT373 TEST CIRCUIT AND WAVEFORM VCC 6V VOUT VIN PULSE GENERATOR 10% 0V tTHL (tF) CL tTLH (tR) tTLH (tR) RL tTHL (tF) 90% POSITIVE PULSE Test Circuit for 3-State Outputs AMP (V) 90% VM VM 10% 10% tW SWITCH POSITION TEST SWITCH tPHZ/tPZH GND tPLZ/tPZL 6V tPLH/tPHL open 0V VM = 1.5V Input Pulse Definition INPUT PULSE REQUIREMENTS DEFINITIONS FAMILY RL = Load resistor; see AC CHARACTERISTICS for value. CL = Load capacitance includes jig and probe capacitance; see AC CHARACTERISTICS for value. 74LVT RT = Termination resistance should be equal to ZOUT of pulse generators. July 1993 AMP (V) VM 10% GND D.U.T RT 90% VM OPEN NEGATIVE PULSE RL tW 90% 7 Amplitude Rep. Rate VCC(Min) ≤1MHz tW tR tF 500ns ≤2.5ns ≤2.5ns