INTEGRATED CIRCUITS DATA SHEET For a complete data sheet, please also download: • The IC04 LOCMOS HE4000B Logic Family Specifications HEF, HEC • The IC04 LOCMOS HE4000B Logic Package Outlines/Information HEF, HEC HEF4750V LSI Frequency synthesizer Product specification File under Integrated Circuits, IC04 January 1995 Philips Semiconductors Product specification HEF4750V LSI Frequency synthesizer DESCRIPTION SUPPLY VOLTAGE The HEF4750V frequency synthesizer is one of a pair of LOCMOS devices, primarily intended for use in high-performance frequency synthesizers, e.g. in all communication, instrumentation, television and broadcast applications. A combination of analogue and digital techniques results in an integrated circuit that enables high performance. The complementary device is the universal divider type HEF4751V. Together with a standard prescaler, the two LOCMOS integrated circuits offer low-cost single loop synthesizers with full professional performance. Salient features offered (in combination with HEF4751V) are: • Wide choice of reference frequency using a single crystal. • High-performance phase comparator low phase noise low spurii. • System operation to > 1 GHz. • Typical 15 MHz input at 10 V. • Flexible programming: frequency offsets ROM compatible fractional channel capability. • Programme range 61⁄2 decades, including up to 3 decades of prescaler control. • Division range extension by cascading. • Built-in phase modulator. • Fast lock feature. • Out-of-lock indication. • Low power dissipation and high noise immunity. APPLICATION INFORMATION Some examples of applications for the HEF4750V in combination with the HEF4751V are: • VHF/UHF mobile radios. • HF s.s.b. transceivers. • Airborne and marine communications and navaids. • Broadcast transmitters. • High quality radio and television receivers. • High performance citizens band equipment. • Signal generators. January 1995 2 RATING RECOMMENDED OPERATING −0,5 to +15 9,5 to 10,5 V Philips Semiconductors Product specification HEF4750V LSI Frequency synthesizer PINNING Fig.1 Pinning diagram. HEF4750VD(F): 28-lead DIL; ceramic (cerdip) (SOT135) ( ): Package Designator North America January 1995 3 R phase comparator input, reference V phase comparator input STB strobe input TCA timing capacitor CA pin TCB timing capacitor CB pin TCC timing capacitor CC pin TRA biasing pin (resistor RA) PC1 analogue phase comparator output PC2 digital phase comparator output MOD phase modulation input OL out-of-lock indication OSC reference oscillator/buffer input XTAL reference oscillator/buffer output A0 to A9 programming inputs/programmable divider NS0, NS1 programming inputs, prescaler OUT reference divider output This text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here in _white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here inThis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader. white to force landscape pages to be ... Philips Semiconductors Frequency synthesizer January 1995 4 Block diagram comprising five basic functions: phase comparator 1 (PC1), phase comparator 2 (PC2), phase modulator, reference oscillator and reference divider. These functions are described separately. Product specification Fig.2 HEF4750V LSI N.B. PC1 = analogue output; PC2 = 3-state output. Philips Semiconductors Product specification HEF4750V LSI Frequency synthesizer the ramp. Capacitor CA holds the voltage that the ramp has attained. Via an internal sampling switch this voltage is transferred to CC and in turn buffered and made available at output PC1. FUNCTIONAL DESCRIPTION Phase comparator 1 Phase comparator 1 (PC1) is built around a SAMPLE and HOLD circuit. A negative-going transition at the V-input causes the hold capacitor (CA) to be discharged and after a specified delay, caused by the Phase Modulator by means of an internal V’ pulse, it produces a positive-going ramp. A negative-going transition at the R-input terminates If the ramp terminates before an R-input is present, an internal end of ramp (EOR) signal is produced. These actions are illustrated in Fig.3. Fig.3 Waveforms associated with PC1. The resultant phase characteristic is shown in Fig.4. January 1995 5 Philips Semiconductors Product specification HEF4750V LSI Frequency synthesizer Fig.4 Phase characteristic of PC1. PC1 is designed to have a high gain, typically 3200 V/cycle (at 12,5 kHz). This enables a low noise performance. Phase comparator 2 This digital phase comparator has three stable states: Phase comparator 2 (PC2) has a wide range, which enables faster lock times to be achieved than otherwise would be possible. It has a linear ± 360° phase range, which corresponds to a gain of typically 5 V/cycle. • reset state, • V’ leads R state, • R leads V’ state. Conversion from one state to another takes place according to the state diagram of Fig.5. Fig.5 State diagram of PC2. Output PC2 produces positive or negative-going pulses with variable width; they depend on the phase relationship of R and V’. The average output voltage is a linear function of the phase difference. Output PC2 remains in the high impedance OFF-state in the region in which PC1 operates. The resultant phase characteristic is shown in Fig.6. January 1995 6 Philips Semiconductors Product specification HEF4750V LSI Frequency synthesizer Fig.6 Phase characteristic of PC2. way. If no modulation is required, the MOD-input must be connected to a fixed voltage of a certain positive value up to VDD. Care must be taken that the V’ pulse is never smaller than the minimum value to ensure that the external capacitor of PC1 (CA) can be discharged during that time. Since the V’ pulse width is directly related to the TCB ramp duration, there is a requirement for the minimum value of this ramp duration. Strobe function The strobe function is intended for applications requiring extremely fast lock times. In normal operation the additional strobe input (STB) can be connected to the V-input and the circuit will function as described in the previous sections. In single, phase-locked-loop type frequency synthesizers, the comparison frequency generally used is either the nominal channel spacing or a sub-multiple. PC2 runs at the higher frequency (a higher reference frequency must also be used), whilst strobing takes place on the lower frequency, thereby obtaining a decrease in lock time. In a system using the Universal Divider HEF4751V, the output OFS cycles on the lower frequency, the output OFF cycles on the higher frequency. Reference oscillator The reference oscillator normally operates with an external crystal as shown in Fig.2. The internal circuitry can be used as a buffer amplifier in case an external reference should be required. Reference divider The reference divider consists of a binary divider with a programmable division ratio of 1 to 1024 and a prescaler with selectable division ratios of 1, 2, 10 and 100, according to the following tables: Out-of-lock function There are a number of situations in which the system goes from the locked to the out-of-lock state (OL goes HIGH): 1. When V’ leads R, however out of the range of PC1. Binary divider 2. When R leads V’. 3. When an R-pulse is missing. N (A0 TO A9) DIVISION RATIO 0 1024 0 ≤ N ≤ 1023 N 4. When a V-pulse is missing. 5. When two successive STB-commands occur, the first without corresponding V-signal. Prescaler Phase modulator The phase modulator only uses one external capacitor, CB at pin TCB. A negative-going transition at the V-input causes CB to produce a positive-going linear ramp. When the ramp has reached a value almost equal to the modulation input voltage (at MOD), the ramp terminates, CB discharges and a start signal to the CA-ramp at TCA is produced. A linear phase modulation is reached in this January 1995 7 PROGRAMMING WORD (NS0, NS1) DIVISION RATIO 0 1 1 2 2 10 3 100 Philips Semiconductors Product specification HEF4750V LSI Frequency synthesizer In this way suitable comparison frequencies can be obtained from a range of crystal frequencies. The divider can also be used as a ‘stand alone’ programmable divider by connecting input TRA to VDD, which causes all internal analogue currents to be switched off. Biasing circuitry The biasing circuitry uses an external current source or resistor, which has to be connected between the TRA and VSS pins. This circuitry supplies all analogue parts of the circuit. Consequently the analogue properties of the device, such as gain, charge currents, speed, power dissipation, impedance levels etc., are mainly determined by the value of the input current at TRA. The TRA input must be decoupled to VDD, as shown in Fig.7. The value of CD has to be chosen such that the TRA input is ‘clean’, e.g. 10 nF at RA = 68 kΩ. Fig.7 Decoupling of input TRA. RATINGS Limiting values in accordance with the Absolute Maximum System (IEC 134) −0,5 to + 15 V Supply voltage VDD Voltage on any input VI D.C. current into any input or output ±I max. 10 mA Ptot max. 500 mW P max. −0,5 to VDD + 0,5 V Power dissipation per package for Tamb = 0 to + 85 °C Power dissipation per output for Tamb = 0 to 85 °C 100 mW Storage temperature Tstg −65 to + 150 °C Operating ambient temperature Tamb −40 to + 85 °C January 1995 8 Philips Semiconductors Product specification HEF4750V LSI Frequency synthesizer DC CHARACTERISTICS at VDD = 10 V ± 5%; voltages are referenced to VSS = 0 V, unless otherwise specified; for definitions see note 1. Tamb (°C PARAMETER −40 SYMBOL + 25 + 85 UNIT NOTES MIN. TYP. MAX. MIN. TYP. MAX. MIN. TYP. MAX. Quiescent device current IDD − − 100 − − 100 − − 750 µA 2 ± IIN − − 300 − − 300 − − 1000 nA 3 Input current; logic inputs, MOD Output leakage current at 1⁄2 VDD TCA, hold-state 3,4 ± IZ − − 20 − 0,05 20 − − 60 nA ± IZ − − 20 − 0,05 20 − − 60 nA ± IZ − − 50 − − 50 − − 500 nA TCC, analogue switch OFF PC2, high impedance OFF-state Logic input voltage LOW VIL max. 0,3 VDD V HIGH VIH max. 0,7 VDD V Logic output voltage LOW; at IO < 1 µA VOL HIGH VOH − − 50 − − 50 − − 50 mV 3 mV 3 min. VDD − 50 mV Logic output current LOW; at VOL = 0,5 V 3 outputs OL, PC2, OUT output XTAL IOL 5,5 − − 4,6 − − 3,6 − − mA IOL 2,8 − − 2,4 − − 1,9 − − mA Logic output current HIGH; at VOH = VDD − 0,5 V 3 outputs OL, PC2,OUT −IOH 1,5 − − 1,3 − − 1,0 − − mA output XTAL −IOH 1,4 − − 1,2 − − 0,9 − − mA IO − − − − 2,1 − − − − mA 3,4,5 −IO − − − − 1,9 − − − − mA 3,4,6 Ri − − − − 0,7 − − − − kΩ 3,4 Output TCC sink current Output TCC source current Internal resistance of TCC output swing ≤ 200 mV specified output range: 0,3 VDD to 0,7 VDD January 1995 9 Philips Semiconductors Product specification HEF4750V LSI Frequency synthesizer Tamb (°C PARAMETER −40 SYMBOL + 25 + 85 UNIT NOTES MIN. TYP. MAX. MIN. TYP. MAX. MIN. TYP. MAX. Output TCC voltage with respect to TCA input voltage ∆V − 0 − − 0 − − 0 − V 3,4,7 IO − − − − 1,1 − − − − mA 3,4,8 −IO − − − − 1,0 − − − − mA 3,4,9 Ri − − − − 1,4 − − − − kΩ 3,4 ∆V − 0 − − 0 − − 0 − V 3,4,10 VEOR − 0,9 − − 0,7 − − 0,6 − V 3,4,11 Output PC1 sink current Output PC1 source current Internal resistance of PC1 output swing ≤ 200 mV specified output range: 0,3 VDD to 0,7 VDD Output PC1 voltage with respect to TCC input voltage EOR generation VEOR = VDD − VTCA Source current; HIGH at VOUT = 1⁄2 VDD; output in ramp mode 3,4 TCA IO − − − − 13 − − − − mA TCB IO − − − − 2,5 − − − − mA January 1995 10 Philips Semiconductors Product specification HEF4750V LSI Frequency synthesizer AC CHARACTERISTICS General note The dynamic specifications are given for the circuit built-up with external components as given in Fig.8, under the following conditions; for definitions see note 1; for definitions of times see Fig.19; VDD = 10 V ± 5%; Tamb = 25 °C; input transition times ≤ 20 ns; RA = 68 kΩ ± 30% (see also note 4); CA = 270 pF; CB = 150 pF; CC = 1 nF; CD = 10 nF; unless otherwise specified. SYMBOL MIN. TYP. MAX. UNIT CONDITIONS NOTES Slew rate TCA STCA − 52 − V/µs RA = minimum 12 TCA STCA − 28 − V/µs RA = maximum 12 TCB STCB − 20 − V/µs RA = minimum 12 TCB STCB − 10 − V/µs RA = maximum 12 TCA ITCA − 2 − % 13 TCB ITCB − 2 − % 13 Start of TCA-ramp delay tCBCA − 200 − ns Delay of TCA-hold tRCA − 40 − ns Delay of TCA-discharge tVCA − 60 − ns Start of TCB-ramp delay tVCB − 60 − ns TCB-ramp duration trCB − 250 − ns VMOD = 4 V trCB − 350 − ns VMOD = 6 V trCB − 450 − ns VMOD = 8 V trCB − 150 − ns V : LOW tPWVL − 20 − ns V : HIGH tPWVH − 20 − ns R : LOW tPWRL − 20 − ns R : HIGH tPWRH − 20 − ns STB : LOW tPWSL − 20 − ns STB : HIGH tPWSH − 20 − ns TCA tfCA − 50 − ns TCB tfCB − 50 − ns Prescaler input frequency fPR − 30 − MHz all division ratios Binary divider frequency fDIV − 30 − MHz all division ratios Crystal oscillator frequency fOSC − 10 − MHz with speed-up 1 : 10 IP − 3,6 − mA 15 without speed-up IP − 3,2 − mA 16 Ramp linearity Required TCB min. ramp duration 14 Pulse width Fall time Average power supply current January 1995 locked state 11 Philips Semiconductors Product specification HEF4750V LSI Frequency synthesizer Notes 1. Definitions: RA = external biasing resistor between pins TRA and VSS; 68 kΩ ± 30%. CA = external timing capacitor for time/voltage converter, between pins TCA and VSS. CB = external timing capacitor for phase modulator, between pins TCB and VSS. CC = external hold capacitor between pins TCC and VSS. CD = decoupling capacitor between pins TRA and VDD. Logic inputs: V, R, STB, A0 to A9, NS0, NS1, OSC. Logic outputs: OL, PC2, XTAL, OUT. Analogue signals: TCA, TCB, TCC, TRA, PC1, MOD. 2. TRA at VDD; TCA, TCB, TCC and MOD at VSS; logic inputs at VSS or VDD. 3. All logic inputs at VSS or VDD. 4. RA connected; its value chosen such that ITRA = 100 µA. 5. The analogue switch is in the ON position (see Fig.9). 6. The analogue switch is in the ON position (see Fig.10). 7. See Fig.11. This guarantees the d.c. voltage gain, combined with d.c.-offset. Input condition: 0,3 VDD ≤ VTCA ≤ 0,7 VDD. ∆V = VTCC−VTCA. 8. See Fig.12. 9. See Fig.13. 10. See Fig.14. This guarantees the d.c. voltage gain, combined with d.c.-offset. Input condition: 0,3 VDD ≤ VTCC ≤ 0,7 VDD. ∆V = VPC1−VTCC. 11. Switching level at TCA, generating an EOR-signal, during increasing input voltage. 12. See Fig.15. 13. See Fig.16. Definition of the ramp linearity at full swing. 14. The external components and modulation input voltage must be chosen such that this requirement will be fulfilled, to ensure that CA is sufficiently discharged during that time. 15. See Fig.17. Circuit connections for power supply current specification, with speed-up 1 : 10. V and R are in the range of PC1, such that the output voltage at PC1 is equal to 5 V. fOSC = 5 MHz (external clock) fSTB = 12,5 kHz fV = 125 kHz 16. See Fig.18. Circuit connections for power supply current specification, without speed-up. V and R are in the range of PC1, such that the output voltage at PC1 is equal to 5 V. fOSC = 5 MHz (external clock) fSTB = 12,5 kHz fV = 12,5 kHz January 1995 12 Philips Semiconductors Product specification HEF4750V LSI Frequency synthesizer Fig.8 Test circuit for measuring a.c. characteristics. Fig.9 Equivalent circuit for note 5. Fig.10 Equivalent circuit for note 6. Fig.11 Circuit for note 7. Fig.12 Equivalent circuit for PC1 sink current. January 1995 13 Philips Semiconductors Product specification HEF4750V LSI Frequency synthesizer Fig.13 Equivalent circuit for PC1 source current. Fig.14 Circuit for note 10. Fig.15 Waveform at the output. ∆V Linearity = ---------------------- × 100 %. 1/2 V DD Fig.16 Definition of the ramp linearity at full swing. ∆V is the maximum deviation of the ramp waveform to the straight line, which joins the 30% VDD and 70% VDD points. January 1995 14 Philips Semiconductors Product specification HEF4750V LSI Frequency synthesizer Fig.17 Circuit for note 15. Fig.18 Circuit for note 16. January 1995 15 Philips Semiconductors Product specification HEF4750V LSI Frequency synthesizer (1) Forbidden zone in the locked state for the positive edge of V and R and both edges of STB. Fig.19 Waveforms showing times in the locked state. January 1995 16 Philips Semiconductors Product specification HEF4750V LSI Frequency synthesizer APPLICATION INFORMATION Fig.20 Application of HEF4750V as horizontal sync circuit with Phase-Locked Loop (PLL) and LC oscillator with vari-cap control. January 1995 17 WWW.ALLDATASHEET.COM Copyright © Each Manufacturing Company. All Datasheets cannot be modified without permission. This datasheet has been download from : www.AllDataSheet.com 100% Free DataSheet Search Site. Free Download. No Register. Fast Search System. www.AllDataSheet.com