INTEGRATED CIRCUITS 74LV161 Presettable synchronous 4-bit binary counter; asynchronous reset Product specification Supersedes data of 1997 Feb 12 IC24 Data Handbook 1997 May 15 Philips Semiconductors Product specification Presettable synchronous 4-bit binary counter; asynchronous reset FEATURES 74LV161 DESCRIPTION • Optimized for low voltage applications: 1.0 to 3.6 V • Accepts TTL input levels between VCC = 2.7 V and VCC = 3.6 V • Typical VOLP (output ground bounce) < 0.8 V at VCC = 3.3 V, The 74LV161 is a low-voltage Si-gate CMOS device and is pin and function compatible with 74HC/HCT161. The 74LV161 is a synchronous presettable binary counter which features an internal look-head carry and can be used for high-speed counting. Synchronous operation is provided by having all flip-flops clocked simultaneously on the positive-going edge of the clock (CP). The outputs (Q0 to Q3) of the counters may be preset to a HIGH or LOW level. A LOW level at the parallel enable input (PE) disables the counting action and causes the data at the data inputs (D0 to D3) to be loaded into the counter on the positive-going edge of the clock (providing that the set-up and hold time requirements for PE are met). Preset takes place regardless of the levels at count enable inputs (CEP and CET). A low level at the master reset input (MR) sets all four outputs of the flip-flops (Q0 to Q3) to LOW level regardless of the levels at CP, PE, CET and CEP inputs (thus providing an asynchronous clear function). Tamb = 25°C • Typical VOHV (output VOH undershoot) > 2 V at VCC = 3.3 V, Tamb = 25°C • Asynchronous reset • Synchronous counting and loading • Two count enable inputs for n-bit cascading • Positive-edge triggered clock • Output capability: standard • ICC category: MSI The look-ahead carry simplifies serial cascading of the counters. Both count enable inputs (CEP and CET) must be HIGH to count. The CET input is fed forward to enable the terminal count output (TC). The TC output thus enabled will produce a HIGH output pulse of a duration approximately equal to a HIGH level output of Q0. This pulse can be used to enable the next cascading stage. The maximum clock frequency for the cascaded counters is determined by the CP to TC propagation delay and CEP to CP set-up time, according to the following formula: 1 f max tp (max) (CP to TC) t su(CEP to CP) QUICK REFERENCE DATA GND = 0 V; Tamb = 25°C; tr = tf ≤ 2.5 ns PARAMETER SYMBOL CONDITIONS CL = 15 pF; VCC = 3.3 V tPHL/tPLH Propagation delay CP to Qn CP to TC MR to Qn MR to TC CET to TC fmax Maximum clock frequency CI Input capacitance CPD Power dissipation capacitance per gate TYPICAL 15 18 15 17 9 VI = GND to VCC1 UNIT ns 77 MHz 3.5 pF 25 pF NOTES: 1. CPD is used to determine the dynamic power dissipation (PD in µW) PD = CPD VCC2 fi (CL VCC2 fo) where: fi = input frequency in MHz; CL = output load capacity in pF; fo = output frequency in MHz; VCC = supply voltage in V; (CL VCC2 fo) = sum of the outputs. ORDERING INFORMATION PACKAGES TEMPERATURE RANGE OUTSIDE NORTH AMERICA NORTH AMERICA PKG. DWG. # 16-Pin Plastic DIL –40°C to +125°C 74LV161 N 74LV161 N SOT38-4 16-Pin Plastic SO –40°C to +125°C 74LV161 D 74LV161 D SOT109-1 16-Pin Plastic SSOP Type II –40°C to +125°C 74LV161 DB 74LV161 DB SOT338-1 16-Pin Plastic TSSOP Type I –40°C to +125°C 74LV161 PW 74LV161PW DH SOT403-1 1997 May 15 2 853–1917 18039 Philips Semiconductors Product specification Presettable synchronous 4-bit binary counter; asynchronous reset PIN CONFIGURATION 74LV161 LOGIC SYMBOL 15 MR 1 16 V CC CP 2 15 TC 3 D0 D0 3 14 Q0 4 D1 4 13 Q1 D2 5 12 Q2 D3 6 11 Q3 CEP 7 10 CET GND 8 9 TC Q0 14 D1 Q1 13 5 D2 Q2 12 6 D3 Q3 11 9 PE PE CEP CET CP MR SV00569 7 10 2 1 SV00570 PIN DESCRIPTION PIN NUMBER SYMBOL FUNCTION FUNCTIONAL DIAGRAM 1 MR Asynchronous master reset (active LOW) 2 CP Clock input (LOW-to-HIGH, edge-triggered) 3, 4, 5, 6 D0 to D3 Data inputs 7 CEP Count enable inputs 8 GND Ground (0 V) 9 PE Parallel enable input (active LOW) 10 CET Count enable carry input 14, 13, 12, 11 Q0 to Q3 Flip-flop outputs 15 TC Terminal count output 16 VCC Positive supply voltage 3 4 D0 D1 D2 5 6 D3 9 PE PARALLEL LOAD CIRCUITRY 10 CET 2 CP 15 BINARY COUNTER 1 MR 1 9 7 10 2 CTR4 R M1 G3 G4 C2/1,3,4+ 3 14 1, 2D 4 13 5 12 6 11 4CT = 15 Q0 Q1 Q2 Q3 14 13 11 12 SV00572 LOGIC SYMBOL (IEEE/IEC) 15 SV00571 1997 May 15 TC 7 CEP 3 Philips Semiconductors Product specification Presettable synchronous 4-bit binary counter; asynchronous reset 74LV161 FUNCTION TABLE INPUTS OPERATING MODES OUTPUTS MR CP CEP CET PE Dn Qn TC Reset (clear) Parallel load Count Hold (do nothing) L X X X X X L L H ↑ X X I I L L H ↑ X X I h H * H ↑ h h h X Count * H X I X h X qn * H X X I h X qn L NOTES: * = The TC output is HIGH when CET is HIGH and the counter is at terminal count (HHHH) H = HIGH voltage level h = HIGH voltage level one set-up time prior to the LOW-to-HIGH clock transition L = LOW voltage level I = LOW voltage level level one set-up time prior to the LOW-to-HIGH clock transition q = lower case letters indicate the state of the referenced output one set-up time prior to the LOW-to-HIGH clock transition X = don’t care ↑ = LOW-to-HIGH clock transition STATE DIAGRAM 0 TYPICAL TIMING SEQUENCE 1 2 3 4 MR PE 15 5 D0 D1 14 6 13 7 D2 D3 CP CEP 12 11 10 9 8 CET SV00573 Q0 Q1 Q2 Q3 TC 12 reset 13 preset 14 15 0 count 1 2 inhibit Typical timing sequence: reset outputs to zero; preset to binary twelve; count to thirteen, fourteen, fifteen, zero, on and two; inhibit. 1997 May 15 4 SV00574 Philips Semiconductors Product specification Presettable synchronous 4-bit binary counter; asynchronous reset 74LV161 LOGIC DIAGRAM D0 D2 D1 D3 CET CEP PE CP FF0 Q D FF1 Q D FF2 Q D FF3 Q D CP CP CP CP RD Q RD Q RD Q RD Q MR Q0 1997 May 15 Q1 5 Q2 Q3 TC SV00575 Philips Semiconductors Product specification Presettable synchronous 4-bit binary counter; asynchronous reset 74LV161 ABSOLUTE MAXIMUM RATINGS1, 2 In accordance with the Absolute Maximum Rating System (IEC 134). Voltages are referenced to GND (ground = 0 V). PARAMETER SYMBOL CONDITIONS RATING UNIT VCC DC supply voltage –0.5 to +4.6 V IIK DC input diode current VI < –0.5 or VI > VCC + 0.5V 20 mA IOK DC output diode current VO < –0.5 or VO > VCC + 0.5V 50 mA IO DC output source or sink current – standard outputs – bus driver outputs –0.5V < VO < VCC + 0.5V 25 35 mA 50 70 mA –65 to +150 °C IGND, ICC Tstg PTOT DC VCC or GND current for types with – standard outputs – bus driver outputs Storage temperature range Power dissipation per package – plastic DIL – plastic mini-pack (SO) – plastic shrink mini-pack (SSOP and TSSOP) for temperature range: –40 to +125°C above +70°C derate linearly with 12 mW/K above +70°C derate linearly with 8 mW/K above +60°C derate linearly with 5.5 mW/K 750 500 400 mW NOTES: 1. Stresses beyond those listed may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. 2. The input and output voltage ratings may be exceeded if the input and output current ratings are observed. RECOMMENDED OPERATING CONDITIONS SYMBOL VCC PARAMETER CONDITIONS MIN TYP See Note 1 1.0 0 0 DC supply voltage VI Input voltage VO Output voltage Tamb Operating ambient temperature range in free air tr, tf Input rise and fall times except for Schmitt-trigger inputs See DC and AC characteristics per device –40 –40 VCC = 1.0V to 2.0V VCC = 2.0V to 2.7V VCC = 2.7V to 3.6V – – – MAX UNIT 3.3 3.6 V – VCC V – VCC V +85 +125 °C 500 200 100 ns/V – – – NOTE: 1. The LV is guaranteed to function down to VCC = 1.0V (input levels GND or VCC); DC characteristics are guaranteed from VCC = 1.2V to VCC = 3.6V. 1997 May 15 6 Philips Semiconductors Product specification Presettable synchronous 4-bit binary counter; asynchronous reset 74LV161 DC ELECTRICAL CHARACTERISTICS Over recommended operating conditions. Voltages are referenced to GND (ground = 0 V). LIMITS SYMBOL PARAMETER -40°C to +85°C TEST CONDITIONS MIN HIGH level l l Input I t voltage VIH LOW level l l Input I t voltage VIL TYP1 MIN 0.9 0.9 VCC = 2.0 V 1.4 1.4 VCC = 2.7 to 3.6 V 2.0 UNIT MAX V 2.0 VCC = 1.2 V 0.3 0.3 VCC = 2.0 V 0.6 0.6 0.8 0.8 VCC = 1.2 V; VI = VIH or VIL; –IO = 100µA HIGH level output voltage; all outputs MAX VCC = 1.2 V VCC = 2.7 to 3.6 V VOH O -40°C to +125°C V 1.2 VCC = 2.0 V; VI = VIH or VIL; –IO = 100µA 1.8 2.0 1.8 VCC = 2.7 V; VI = VIH or VIL; –IO = 100µA 2.5 2.7 2.5 VCC = 3.0 V; VI = VIH or VIL; –IO = 100µA 2.8 3.0 2.8 V VOH HIGH level output voltage; STANDARD outputs VCC = 3.0 V; VI = VIH or VIL; –IO = 6mA 2.40 2.82 2.20 V VOH HIGH level output voltage; BUS driver outputs VCC = 3.0 V; VI = VIH or VIL; –IO = 8mA 2.40 2.82 2.20 V VCC = 1.2 V; VI = VIH or VIL; IO = 100µA 0 VCC = 2.0 V; VI = VIH or VIL; IO = 100µA 0 0.2 0.2 VCC = 2.7 V; VI = VIH or VIL; IO = 100µA 0 0.2 0.2 VCC = 3.0 V; VI = VIH or VIL; IO = 100µA 0 0.2 0.2 VOL O LOW level output voltage; all outputs VOL LOW level output voltage; STANDARD outputs VCC = 3.0 V; VI = VIH or VIL; IO = 6mA 0.25 0.40 0.50 V VOL LOW level output voltage; BUS driver outputs VCC = 3.0 V; VI = VIH or VIL; IO = 8mA 0.20 0.40 0.50 V Input leakage current VCC = 3.6 V; VI = VCC or GND 1.0 1.0 µA 3-State output OFF-state current VCC = 3.6 V; VI = VIH or VIL; VO = VCC or GND 5 10 µA Quiescent supply current; SSI VCC = 3.6V; VI = VCC or GND; IO = 0 20.0 40 Quiescent supply current; flip-flops VCC = 3.6V; VI = VCC or GND; IO = 0 20.0 80 Quiescent supply current; MSI VCC = 3.6 V; VI = VCC or GND; IO = 0 20.0 160 Quiescent supply current; LSI VCC = 3.6 V; VI = VCC or GND; IO = 0 500 1000 Additional quiescent supply current per input VCC = 2.7 V to 3.6 V; VI = VCC – 0.6 V 500 850 II IOZ ICC ∆ICC µA µA NOTE: 1. All typical values are measured at Tamb = 25°C. 1997 May 15 V 7 µA Philips Semiconductors Product specification Presettable synchronous 4-bit binary counter; asynchronous reset 74LV161 AC CHARACTERISTICS GND = 0V; tr = tf ≤ 2.5ns; CL = 50pF; RL = 1KΩ SYMBOL PARAMETER WAVEFORM VCC(V) tPHL/tPLH tPHL/tPLH tPHL/tPLH tPHL/tPLH tPHL/tPLH tw tw Propagation g delay y CP to Qn Propagation g delay y CP to TC Propagation g delay y MR to Qn Propagation g delay y MR to TC Propagation g delay y CET to TC Clock pulse width HIGH or LOW Master reset width; LOW Figures 1 1, 6 Figures 1 1, 6 Figures 2 2, 6 Figures 2 2, 6 Figures 1 1, 6 Figures 2, 6 Figures 2, 6 LIMITS CONDITION –40 to +85 °C MIN Removal time MR to CP Figures 2 2, 6 Set-up time Dn to CP Figures 4 4, 6 Set-up time PE to CP Figures 4 4, 6 32 61 75 24 45 55 3.0 to 3.6 182 36 44 1.2 115 2.0 39 75 90 2.7 29 55 66 3.0 to 3.6 222 44 53 1.2 95 2.0 32 61 75 2.7 24 45 55 3.0 to 3.6 182 36 44 1.2 105 2.0 36 68 82 2.7 26 50 60 3.0 to 3.6 202 40 48 1.2 55 2.0 19 36 44 2.7 14 26 33 3.0 to 3.6 102 21 2.0 34 1997 May 15 Set-up time CEP, CET to CP Figures 5 5, 6 ns ns ns ns ns 26 10 41 2.7 25 8 30 3.0 to 3.6 20 62 24 2.0 34 14 41 2.7 25 10 30 3.0 to 3.6 20 82 24 ns ns 25 2.0 22 9 26 2.7 16 6 19 3.0 to 3.6 13 52 15 ns 25 2.0 22 9 26 2.7 16 6 19 3.0 to 3.6 13 52 15 ns 30 2.0 22 10 26 2.7 16 8 19 3.0 to 3.6 13 62 15 ns 30 2.0 22 10 26 2.7 16 8 19 3.0 to 3.6 13 62 15 8 UNIT MAX 2.7 1.2 tsu MIN 2.0 1.2 tsu MAX 95 1.2 tsu –40 to +125 °C 1.2 1.2 trem TYP1 ns Philips Semiconductors Product specification Presettable synchronous 4-bit binary counter; asynchronous reset 74LV161 AC ELECTRICAL CHARACTERISTICS (Continued) SYMBOL PARAMETER WAVEFORM LIMITS CONDITION VCC(V) –40 to +85 °C MIN 1.2 Hold time Dn, PE PE, CEP, CEP CET to CP th Maximum clock ulse frequency pulse fmax TYP1 –40 to +125 °C MAX MIN –35 2.0 0 –12 0 2.7 0 –9 0 3.0 to 3.6 0 –72 0 2.0 14 40 12 2.7 19 58 16 3.0 to 3.6 24 70 20 Figures 4 – 6 Figures 1, 6 UNIT MAX ns MHz NOTES: 1. Unless otherwise stated, all typical values are measured at Tamb = 25°C 2. Typical values are measured at VCC = 3.3 V. AC WAVEFORMS VM = 1.5 V at VCC ≥ 2.7 V; VM = 0.5 × VCC at VCC < 2.7 V; VOL and VOH are the typical output voltage drop that occur with the output load. 1/fmax VI VI CP INPUT VM CET INPUT VM GND tPLH GND tW tPLH tPHL VOH tPHL TC OUTPUT VOH Qn, TC OUTPUT VM VOL VM SV00578 VOL SV00576 Figure 3. Input (CET) to output (TC) propagation delays. Figure 1. Clock (CP) to outputs (Qn, TC) propagation delays, the clock pulse width and the maximum clock frequency. VI VM PE INPUT VI GND MR INPUT tsu VM VI GND tsu th th tW CP INPUT trem VM VI GND tsu VM CP INPUT VI GND Dn INPUT tPHL VOH Qn , TC OUTPUT th tsu th VM GND The shaded areas indicate when the input is permitted to change for predictable output performance. VM VOL SV00577 Figure 4. Set-up and hold times for input (Dn) and parallel enable input (PE). Figure 2. Master reset (MR) pulse width, the master reset to output (Qn, TC) propagation delays and the master reset to clock (CP) removal times. 1997 May 15 9 SV00579 Philips Semiconductors Product specification Presettable synchronous 4-bit binary counter; asynchronous reset 74LV161 VI CEP, CET VM INPUT GND tsu tsu th th VI CP INPUT VM GND The shaded areas indicate when the input is permitted to change for predictable output performance. SV00580 Figure 5. CEP and CET set-up and hold times. TEST CIRCUIT S1 VCC RL VO VI PULSE GENERATOR 2 x VCC Open GND D.U.T. RT CL RL Test Circuit for switching times DEFINITIONS SWITCH POSITION TEST tPLH/tPHL S1 VCC VI RL = Load resistor; see AC CHARACTERISTICS for value. CL = Load capacitance includes jig and probe capacitance: See AC CHARACTERISTICS for value. Open < 2.7V VCC tPLZ/tPZL 2 x VCC 2.7–3.6V 2.7V tPHZ/tPZH GND RT = Termination resistance should be equal to ZOUT of pulse generators. SV00776 Figure 6. Load circuitry for switching times. 1997 May 15 10 Philips Semiconductors Product specification Presettable synchronous 4-bit binary counter; asynchronous reset DIP16: plastic dual in-line package; 16 leads (300 mil) 1997 May 15 11 74LV161 SOT38-4 Philips Semiconductors Product specification Presettable synchronous 4-bit binary counter; asynchronous reset SO16: plastic small outline package; 16 leads; body width 3.9 mm 1997 May 15 12 74LV161 SOT109-1 Philips Semiconductors Product specification Presettable synchronous 4-bit binary counter; asynchronous reset SSOP16: plastic shrink small outline package; 16 leads; body width 5.3 mm 1997 May 15 13 74LV161 SOT338-1 Philips Semiconductors Product specification Presettable synchronous 4-bit binary counter; asynchronous reset TSSOP16: plastic thin shrink small outline package; 16 leads; body width 4.4 mm 1997 May 15 14 74LV161 SOT403-1 Philips Semiconductors Product specification Presettable synchronous 4-bit binary counter; asynchronous reset NOTES 1997 May 15 15 74LV161 Philips Semiconductors Product specification Presettable synchronous 4-bit binary counter; asynchronous reset 74LV161 DEFINITIONS Data Sheet Identification Product Status Definition Objective Specification Formative or in Design This data sheet contains the design target or goal specifications for product development. Specifications may change in any manner without notice. Preliminary Specification Preproduction Product This data sheet contains preliminary data, and supplementary data will be published at a later date. Philips Semiconductors reserves the right to make changes at any time without notice in order to improve design and supply the best possible product. Product Specification Full Production This data sheet contains Final Specifications. Philips Semiconductors reserves the right to make changes at any time without notice, in order to improve design and supply the best possible product. Philips Semiconductors and Philips Electronics North America Corporation reserve the right to make changes, without notice, in the products, including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified. Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. LIFE SUPPORT APPLICATIONS Philips Semiconductors and Philips Electronics North America Corporation Products are not designed for use in life support appliances, devices, or systems where malfunction of a Philips Semiconductors and Philips Electronics North America Corporation Product can reasonably be expected to result in a personal injury. Philips Semiconductors and Philips Electronics North America Corporation customers using or selling Philips Semiconductors and Philips Electronics North America Corporation Products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors and Philips Electronics North America Corporation for any damages resulting from such improper use or sale. Copyright Philips Electronics North America Corporation 1997 All rights reserved. Printed in U.S.A. Philips Semiconductors 811 East Arques Avenue P.O. Box 3409 Sunnyvale, California 94088–3409 Telephone 800-234-7381 1997 May 15 16