Security & Chip Card ICs SLE 4436/36E Intelligent 221–Bit EEPROM Counter for > 20000 Units with Security Logic and High Security Authentication Short Product Information 07.99 6/((6KRUW3URGXFW,QIRUPDWLRQ 5HYLVLRQ+LVWRU\ &XUUHQW9HUVLRQ Previous Releases: 01.96 Page Ref.: SPI_SLE4436_0799.doc Subjects (changes since last revision) Layout change ,PSRUWDQW: Further information is confidential and on request. Please contact: Infineon Technologies AG in Munich, Germany, Security & Chip Card ICs, Fax +49 89 234-28925 E-Mail: Security-andChipcard-ICs@infineoncom 3XEOLVKHGE\,QILQHRQ7HFKQRORJLHV$*&&$SSOLFDWLRQV*URXS 6W0DUWLQ6WUDVVH'0QFKHQ ,QILQHRQ7HFKQRORJLHV$* $OO5LJKWV5HVHUYHG $WWHQWLRQSOHDVH The information herein is given to describe certain components and shall not be considered as warranted characteristics. Terms of delivery and rights to technical change reserved. We hereby disclaim any and all warranties, including but not limited to warranties of non-infringement, regarding circuits, descriptions and charts stated herein. Infineon Technologies is an approved CECC manufacturer. ,QIRUPDWLRQ For further information on technology, delivery terms and conditions and prices please contact your nearest Infineon Technologies Office in Germany or our Infineon Technologies Representatives world-wide (see address list). :DUQLQJV Due to technical requirements components may contain dangerous substances. For information on the types in question please contact your nearest Infineon Technologies Office. Infineon Technologies Components may only be used in life-support devices or systems with the express written approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure of that life-support device or system, or to affect the safety or effectiveness of that device or system. Life support devices or systems are intended to be implanted in the human body, or to support and/or maintain and sustain and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may be endangered. 6/(( ,QWHOOLJHQW±%LW((3520&RXQWHU IRU!8QLWVZLWK6HFXULW\/RJLF DQG+LJK6HFXULW\$XWKHQWLFDWLRQ )HDWXUHV • ELW((3520DQGELWPDVNSURJUDPPDEOH520 104 bit user memory fully compatible with SLE 4406/06E – 64 bit Identification Area consisting of • 16 bit Manufacturer code (mask-programmable ROM) • SLE 4436: 0 8 bit Manufacturer data, card issuer dependent (ROM) 40 bit for personalization data of card issuer (PROM) • SLE 4436E: 48 bit for personalization data of card issuer (PROM) – 40 bit Counter Area including 1 bit for personalization (PROM/EEPROM) 133 bit additional memory for advanced features – 4 bit Counter Backup (anti-tearing flags) – 1 bit initiation flag for Authentication Key 2 – 16 bit Data Area 1 for free user access – 48 bit Authentication Key 1 – either 48 bit Data Area 2 for user defined data or 48 bit Authentication Key 2 – 16 bit Data Area 3 for free user access • &RXQWHUZLWKXSWRFRXQWXQLWVIXOO\FRPSDWLEOHZLWK6/(( – Five stage abacus counter – Due to testing purposes a maximum of 21064 count units is guaranteed • &RXQWHUWHDULQJSURWHFWLRQ – Backup feature activated at choice • +LJKVHFXULW\DXWKHQWLFDWLRQXQLW – Random number as challenge – Individual secret Authentication Key 1 – Optional individual secret Authentication Key 2 – Calculation of up to 16 bit response – Calculation of a 16 bit response within 30 ms at a clock frequency of 100 kHz • 7UDQVSRUW&RGHSURWHFWLRQIRUGHOLYHU\ • ((3520VHFXULW\FHOOVLQVHQVLWLYHDUHDV • &KLSFLUFXLWU\DQGFKLSOD\RXWRSWLPLVHGIRUKLJKVHFXULW\DJDLQVWSK\VLFDODQGHOHFWULFDO VLJQDODQDO\VLV 6KRUW3URGXFW,QIRUPDWLRQ 3/7 6/(( )HDWXUHV(cont’d) • $PELHQWWHPSHUDWXUH±…& • 6XSSO\YROWDJH9 • 6XSSO\FXUUHQWP$ • ((3520SURJUDPPLQJWLPHPV • (6'SURWHFWLRQW\SLFDO9 • (QGXUDQFHPLQLPXPZULWHHUDVHF\FOHVELW • 'DWDUHWHQWLRQIRUPLQLPXPRI\HDUV • &RQWDFW FRQILJXUDWLRQ DQG $QVZHUWR5HVHW V\QFKURQRXV WUDQVPLVVLRQ LQ DFFRUGDQFH WRVWDQGDUG,62,(& 7DEOH 2UGHULQJ,QIRUPDWLRQ 7\SH 3DFNDJH SLE 4436 M3 M3 SLE 4436 C C SLE 4436E M3 M3 SLE 4436E C C 1) 2) $FFHVVRIUGE\WH Data of 3rd byte are programmed by Infineon exclusively Data of 3rd byte are programmed by the card manufacturer at personalisation Values are temperature dependent Available as a wire-bonded module (M3) for embedding in plastic cards or as a die (C) for customer packaging 6KRUW3URGXFW,QIRUPDWLRQ 4/7 6/(( 3LQ'HVFULSWLRQ )LJXUH VCC C1 C5 GND RST C2 C6 N.C. CLK C3 C7 I/O 3LQ&RQILJXUDWLRQ:LUHERQGHG0RGXOHWRSYLHZ CLK VDD 6/(( RST GND I/O )LJXUH 3DG&RQILJXUDWLRQ'LH 7DEOH 3LQ'HILQLWLRQVDQG)XQFWLRQV &DUG&RQWDFW 6\PERO )XQFWLRQ C1 VCC Supply voltage C2 RST Control input (Reset Signal) C3 CLK Clock input C5 GND Ground C6 N.C. Not connected C7 I/O Bi-directional data line (open drain) 6KRUW3URGXFW,QIRUPDWLRQ 5/7 6/(( *HQHUDO'HVFULSWLRQ SLE 4436/36E is designed for applications in prepaid telephone cards. The chip consists of an EEPROM memory of 221 bit, a ROM of 16 bits, a control/security unit and a special computing unit for chip authentication. The shaded blocks in the block diagram (Figure 3) contain the enhanced features of SLE 4436/36E compared to SLE 4406/06E. 3URJUDPPLQJ8QLW $XWKHQWLFDWLRQ 8QLW 0HPRU\8QLW Data Areas Counter $GGUHVV 8QLW Authentication Key 1 Backup Unit 6/( 6/(( Identification Area Identification Area 40 bit blockable PROM 48 bit blockable PROM optional Authentication Key 2 8 bit Manufacturer Data 16 bit Manufacturer Code 16 bit Manufacturer Code &RQWURO8QLW6HFXULW\,QWHUIDFH &/. ,2 567 *1' 9&& /HJHQG Shaded blocks - Enhanced features of SLE 4436/36E compared to SLE 4406/06E Blocks marked by cross hatch - Defined by chip manufacturer )LJXUH %ORFN'LDJUDP • 0HPRU\8QLW Counter, Identification Data (e.g. serial number, expiry date) and Data Areas. • $GGUHVV8QLW Setting of the address counter is synchronously with the CLK. • 3URJUDPPLQJ8QLW The programming voltage for the EEPROM/PROM is generated internally. 6KRUW3URGXFW,QIRUPDWLRQ 6/7 6/(( • %DFNXS8QLW An associated backup bit indicates an interrupt caused by e.g. tearing a card out of a reader without mechanical locking device during a reloading cycle of a devaluated counter stage. • $XWKHQWLFDWLRQ8QLW The secret algorithm offers a challenge & response procedure for individual card authentication; the optional activation of cipher block chaining allows the certification of a counter decreasing procedure. • 6HFXULW\,QWHUIDFH Ensures a minimum and a maximum frequency and proper logical voltage levels. 6KRUW3URGXFW,QIRUPDWLRQ 7/7