PD - 93989 IRFE9210 200V, P-CHANNEL REPETITIVE AVALANCHE AND dv/dt RATED HEXFET TRANSISTORS SURFACE MOUNT (LCC-18) Product Summary Part Number IRFE9210 BVDSS -200V RDS(on) 3.0Ω ID -1.3A The leadless chip carrier (LCC) package represents the logical next step in the continual evolution of surface mount technology. Desinged to be a close replacement for the TO-39 package, the LCC will give designers the extra flexibility they need to increase circuit board density. International Rectifier has engineered the LCC package to meet the specific needs of the power market by increasing the size of the bottom source pad, thereby enhancing the thermal and electrical performance. The lid of the package is grounded to the source to reduce RF interference. LCC-18 Features: ! ! ! ! ! ! ! ! Surface Mount Small Footprint Alternative to TO-39 Package Hermetically Sealed Dynamic dv/dt Rating Avalanche Energy Rating Simple Drive Requirements Light Weight Absolute Maximum Ratings Parameter ID @ VGS = -10V, TC = 25°C ID @ VGS = -10V, TC = 100°C I DM PD @ TC = 25°C VGS EAS IAR EAR dv/dt TJ T STG Units Continuous Drain Current Continuous Drain Current Pulsed Drain Current ➀ Max. Power Dissipation Linear Derating Factor Gate-to-Source Voltage Single Pulse Avalanche Energy ➁ Avalanche Current ➀ Repetitive Avalanche Energy ➀ Peak Diode Recovery dv/dt ➂ Operating Junction Storage Temperature Range -1.3 -0.84 -5.2 11 0.09 ±20 72 -5.0 -55 to 150 Pckg. Mounting Surface Temp. Weight 300 (for 5 S) 0.42(typical) A W W/°C V mJ A mJ V/ns o C g For footnotes refer to the last page www.irf.com 1 10/25/00 IRFE9210 Electrical Characteristics Parameter Min Drain-to-Source Breakdown Voltage -200 Typ Max Units — — V — -0.22 — V/°C — — -2.0 0.7 — — — — — — — — 3.0 3.45 - 4.0 — -25 -250 Ω VGS(th) gfs IDSS Temperature Coefficient of Breakdown Voltage Static Drain-to-Source On-State Resistance Gate Threshold Voltage Forward Transconductance Zero Gate Voltage Drain Current I GSS I GSS Qg Qgs Qgd td(on) tr td(off) tf LS + LD Gate-to-Source Leakage Forward Gate-to-Source Leakage Reverse Total Gate Charge Gate-to-Source Charge Gate-to-Drain (‘Miller’) Charge Turn-On Delay Time Rise Time Turn-Off Delay Time Fall Time Total Inductance — — — — — — — — — — — — — — — — — — — 6.1 -100 100 8.9 2.1 3.9 15 25 40 15 — Ciss Coss Crss Input Capacitance Output Capacitance Reverse Transfer Capacitance — — — 170 54 17 — — RDS(on) Test Conditions VGS = 0V, ID = -1.0mA Reference to 25°C, ID = -1.0mA nC VGS = -10V, ID = -0.84A➃ VGS = -10V, ID = -1.3A ➃ VDS = VGS, ID = -250µA VDS > -15V, IDS = -0.84A➃ VDS= -160V, VGS= 0V VDS =-160V VGS = 0V, TJ = 125°C VGS =-20V VGS =20V VGS =-10V, ID= -1.3A VDS =-100V ns VDD =-100V, ID = -1.3A, RG =7.5Ω V S( ) Ω BVDSS ∆BV DSS/∆TJ @ Tj = 25°C (Unless Otherwise Specified) µA nA nH pF Measured from the center of drain pad to center of source pad VGS = 0V, VDS = -25V f = 1.0MHz Source-Drain Diode Ratings and Characteristics Parameter Min Typ Max Units IS ISM Continuous Source Current (Body Diode) Pulse Source Current (Body Diode) ➀ — — — — -1.3 -5.2 A VSD t rr QRR Diode Forward Voltage Reverse Recovery Time Reverse Recovery Charge — — — — — — -5.8 300 3.0 V nS µc t on Forward Turn-On Time Test Conditions Tj = 25°C, IS = -1.3A, VGS = 0V ➃ Tj = 25°C, IF = -1.3A, di/dt ≤-100A/µs VDD ≤ -50V ➃ Intrinsic turn-on time is negligible. Turn-on speed is substantially controlled by LS + LD. Thermal Resistance Parameter RthJC RthJ-PCB Junction to Case Junction to PC Board Min Typ Max Units — — — — 11 °C/W 27" " " Test Conditions Soldered to a copper clad PC board For footnotes refer to the last page 2 www.irf.com IRFE9210 Fig 1. Typical Output Characteristics Fig 3. Typical Transfer Characteristics www.irf.com Fig 2. Typical Output Characteristics Fig 4. Normalized On-Resistance Vs. Temperature 3 IRFE9210 13 a& b 4 Fig 5. Typical Capacitance Vs. Drain-to-Source Voltage Fig 6. Typical Gate Charge Vs. Gate-to-Source Voltage Fig 7. Typical Source-Drain Diode Forward Voltage Fig 8. Maximum Safe Operating Area www.irf.com IRFE9210 V DS VGS RD D.U.T. RG + V DD -12V 10V 10V Pulse Width ≤ 1 µs Duty Factor ≤ 0.1 % Fig 10a. Switching Time Test Circuit td(on) tr t d(off) tf VGS 10% 90% Fig 9. Maximum Drain Current Vs. Case Temperature VDS Fig 10b. Switching Time Waveforms Fig 11. www.irf.com Maximum Effective Transient Thermal Impedance, Junction-to-Case 5 IRFE9210 L VDS D.U.T RG IAS 0V -20V -12V tp VDD A DRIVER 0.01Ω 15V Fig 12a. Unclamped Inductive Test Circuit I AS Fig 12c. Maximum Avalanche Energy Vs. Drain Current tp V(BR)DSS Fig 12b. Unclamped Inductive Waveforms Current Regulator Same Type as D.U.T. 50KΩ QG -12V 12V .2µF .3µF -10V QGS QGD D.U.T. +VDS VGS VG -3mA Charge Fig 13a. Basic Gate Charge Waveform 6 IG ID Current Sampling Resistors Fig 13b. Gate Charge Test Circuit www.irf.com IRFE9210 Foot Notes: ➀ Repetitive Rating; Pulse width limited by maximum junction temperature. ➁ VDD = -50V, starting TJ = 25°C, Peak IL = -1.3A, ➂ ISD ≤ -1.3A, di/dt ≤ -70A/µs, VDD≤ -200V, TJ ≤ 150°C Suggested RG =7.5 Ω ➃ Pulse width ≤ 300 µs; Duty Cycle ≤ 2% Case Outline and Dimensions — LCC-18 IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105 IR EUROPEAN REGIONAL CENTRE: 439/445 Godstone Rd, Whyteleafe, Surrey CR3 OBL, UK Tel: ++ 44 (0)20 8645 8000 IR CANADA: 15 Lincoln Court, Brampton, Ontario L6T3Z2, Tel: (905) 453 2200 IR GERMANY: Saalburgstrasse 157, 61350 Bad Homburg Tel: ++ 49 (0) 6172 96590 IR ITALY: Via Liguria 49, 10071 Borgaro, Torino Tel: ++ 39 011 451 0111 IR JAPAN: K&H Bldg., 2F, 30-4 Nishi-Ikebukuro 3-Chome, Toshima-Ku, Tokyo 171 Tel: 81 (0)3 3983 0086 IR SOUTHEAST ASIA: 1 Kim Seng Promenade, Great World City West Tower, 13-11, Singapore 237994 Tel: ++ 65 (0)838 4630 IR TAIWAN:16 Fl. Suite D. 207, Sec. 2, Tun Haw South Road, Taipei, 10673 Tel: 886-(0)2 2377 9936 Data and specifications subject to change without notice. 10/00 www.irf.com 7