INTEGRATED CIRCUITS DATA SHEET 74AHC164; 74AHCT164 8-bit serial-in/parallel-out shift register Product specification File under Integrated Circuits, IC06 2000 Aug 15 Philips Semiconductors Product specification 8-bit serial-in/parallel-out shift register 74AHC164; 74AHCT164 FEATURES DESCRIPTION • ESD protection: HBM EIA/JESD22-A114-A exceeds 2000 V MM EIA/JESD22-A115-A exceeds 200 V CDM EIA/JESD22-C101 exceeds 1000 V The 74AHC/AHCT164 shift registers are high-speed silicon-gate CMOS devices and are pin compatible with Low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard No. 7A. • Balanced propagation delays The 74AHC/AHCT164 input signals are 8-bit serial through one of two inputs (Dsa or Dsb); either input can be used as an active HIGH enable for data entry through the other input. Both inputs must be connected together or an unused input must be tied HIGH. • All inputs have Schmitt-trigger actions • Inputs accept voltages higher than VCC • For AHC only: operates with CMOS input levels • For AHCT only: operates with TTL input levels Data shifts one place to the right on each LOW-to-HIGH transition of the clock (CP) input and enters into Q0, which is a logical AND of the two data inputs (Dsa, Dsb) that existed one set-up time prior to the rising clock edge. • Specified from −40 to +85 °C and from −40 to +125 °C. A LOW level on the master reset (MR) input overrides all other inputs and clears the register asynchronously, forcing all outputs LOW. QUICK REFERENCE DATA GND = 0 V; Tamb = 25 °C; tr = tf ≤ 3.0 ns. TYPICAL SYMBOL PARAMETER CONDITIONS UNIT AHC tPHL/tPLH propagation delay AHCT CL = 15 pF; VCC = 5 V CP to Qn MR to Qn 4.5 3.4 ns 4.0 3.5 ns CI input capacitance VI = VCC or GND 3 3 pF fmax maximum clock frequency CL = 15 pF; VCC = 5 V 175 175 MHz CPD power dissipation capacitance CL = 50 pF; f = 1 MHz; notes 1 and 2 48 51 pF Notes 1. CPD is used to determine the dynamic power dissipation (PD in µW). PD = CPD × VCC2 × fi + ∑ (CL × VCC2 × fo) where: fi = input frequency in MHz; fo = output frequency in MHz; ∑ (CL × VCC2 × fo) = sum of outputs; CL = output load capacitance in pF; VCC = supply voltage in Volts. 2. The condition is VI = GND to VCC. 2000 Aug 15 2 Philips Semiconductors Product specification 8-bit serial-in/parallel-out shift register 74AHC164; 74AHCT164 FUNCTION TABLE See note 1. INPUTS OUTPUTS OPERATING MODES MR CP Dsa Dsb Q0 Q1-Q7 reset (clear) L X X X L L-L shift H ↑ l l L q0-q6 H ↑ l h L q0-q6 H ↑ h l L q0-q6 H ↑ h h H q0-q6 Note 1. H = HIGH voltage level; h = HIGH voltage level one set-up time prior to the LOW-to-HIGH clock transition; L = LOW voltage level; l = LOW voltage level one set-up time prior to the LOW-to-HIGH clock transition; ↑ = LOW-to-HIGH transition; X = don’t care; q = lower case letter indicates the state of the referenced input one set-up time prior to the LOW-to-HIGH transition. ORDERING INFORMATION PACKAGES TYPE NUMBER TEMPERATURE RANGE PINS PACKAGE MATERIAL CODE −40 to +125 °C 14 SO plastic SOT108-1 74AHC164PW 14 TSSOP plastic SOT402-1 74AHCT164D 14 SO plastic SOT108-1 74AHCT164PW 14 TSSOP plastic SOT402-1 74AHC164D 2000 Aug 15 3 Philips Semiconductors Product specification 8-bit serial-in/parallel-out shift register 74AHC164; 74AHCT164 PINNING PIN SYMBOL DESCRIPTION 1, 2 Dsa, Dsb data input 3, 4, 5, 6, 10, 11, 12, 13 Q0 to Q7 outputs 7 GND ground (0 V) 8 CP clock input (LOW-to-HIGH, edge-triggered) 9 MR master reset input (active LOW) 14 VCC DC supply voltage handbook, halfpage handbook, halfpage 14 VCC Dsa 1 Dsb 2 13 Q7 Q0 3 12 Q6 Q1 4 Q2 5 10 Q4 Q3 6 9 164 Dsa 2 7 Q1 Q2 Dsb Q3 11 Q5 8 GND Q0 1 8 CP Q4 Q5 MR 9 CP MR Q6 Q7 4 5 6 10 11 12 13 MNA597 MNA596 Fig.1 Pin configuration. 2000 Aug 15 3 Fig.2 Logic symbol. 4 Philips Semiconductors Product specification 8-bit serial-in/parallel-out shift register handbook, halfpage 74AHC164; 74AHCT164 SRG8 8 C1/ 9 R handbook, halfpage 1 2 & 1 Dsa 4 2 Dsb 5 8 CP 6 9 MR 3 1D 8-BIT SERIAL-IN/PARALLEL-OUT SHIFT REGISTER 10 Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 11 3 MNA598 4 5 6 10 11 12 13 D Q 12 13 MNA599 Fig.3 IEC logic symbol. Fig.4 Functional diagram. Dsa D Dsb Q D CP FF1 RD Q D CP FF2 RD Q D CP FF3 RD Q D CP FF4 RD Q D CP FF5 RD Q D CP FF6 RD Q CP FF7 RD CP FF8 RD CP MR Q0 Q1 Q2 Q3 Fig.5 Logic diagram. 2000 Aug 15 5 Q4 Q5 Q6 MNA600 Q7 Philips Semiconductors Product specification 8-bit serial-in/parallel-out shift register 74AHC164; 74AHCT164 RECOMMENDED OPERATING CONDITIONS 74AHC SYMBOL PARAMETER 74AHCT CONDITIONS UNIT MIN. TYP. MAX. MIN. TYP. MAX. 4.5 5.0 5.5 V VCC DC supply voltage 2.0 5.0 5.5 VI input voltage 0 − 5.5 0 − 5.5 V VO output voltage 0 − VCC 0 − VCC V Tamb operating ambient temperature −40 +25 +85 −40 +25 +85 °C −40 +25 +125 −40 +25 +125 °C tr, tf input rise and fall ratios (∆t/∆V) see DC and AC characteristics per device VCC = 3.3 ±0.3 V − − 100 − − − ns/V VCC = 5 ±0.5 V − − 20 − − 20 ns/V LIMITING VALUES In accordance with the Absolute Maximum Rating System (IEC 60134); voltages are referenced to GND (ground = 0 V). SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT VCC DC supply voltage −0.5 +7.0 V VI input voltage −0.5 +7.0 V IIK DC input diode current VI < −0.5 V; note 1 − −20 mA IOK DC output clamping diode current −0.5 > VO > VCC + 0.5 V; note 1 − ±20 mA IO DC output sink current −0.5 < VO < VCC + 0.5 V − ±25 mA ICC DC VCC or GND current − ±75 mA Tstg storage temperature PD power dissipation per package for temperature range: −40 to +125 °C; note 2 −65 +150 °C − 500 Notes 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed. 2. For SO packages: above 70 °C the value of PD derates linearly by 8 mW/K. For TSSOP packages: above 60 °C the value of PD derates linearly by 5.5 mW/K. 2000 Aug 15 6 mW Philips Semiconductors Product specification 8-bit serial-in/parallel-out shift register 74AHC164; 74AHCT164 DC CHARACTERISTICS 74AHC family With regard to recommended operating conditions; voltages are referenced to GND (ground = 0 V). Tamb (°C) TEST CONDITIONS SYMBOL OTHER VIH VIL VOH VOL −40 to +125 UNIT TYP. MAX. MIN. MAX. MIN. MAX. 2.0 1.5 − − 1.5 − 1.5 − V 3.0 2.1 − − 2.1 − 2.1 − V 5.5 3.85 − − 3.85 − 3.85 − V 2.0 − − 0.5 − 0.5 − 0.5 V 3.0 − − 0.9 − 0.9 − 0.9 V 5.5 − − 1.65 − 1.65 − 1.65 V 2.0 1.9 2.0 − 1.9 − 1.9 − V 3.0 2.9 3.0 − 2.9 − 2.9 − V 4.5 4.4 4.5 − 4.4 − 4.4 − V VI = VIH or VIL; IO = −4.0 mA 3.0 2.58 − − 2.48 − 2.40 − V VI = VIH or VIL; IO = −8.0 mA 4.5 3.94 − − 3.8 − 3.70 − V VI = VIH or VIL; IO = 50 µA 2.0 − 0 0.1 − 0.1 − 0.1 V 3.0 − 0 0.1 − 0.1 − 0.1 V 4.5 − 0 0.1 − 0.1 − 0.1 V VI = VIH or VIL; IO = 4.0 mA 3.0 − − 0.36 − 0.44 − 0.55 V VI = VIH or VIL; IO = 8.0 mA 4.5 − − 0.36 − 0.44 − 0.55 V − 1.0 − 2.0 µA ±2.5 − ±10.0 µA LOW-level input voltage LOW-level output voltage VCC (V) MIN. HIGH-level input voltage HIGH-level output voltage −40 to +85 25 PARAMETER VI = VIH or VIL; IO = −50 µA II input leakage current VI = VCC or GND 5.5 − − 0.1 IOZ 3-state output OFF-state current VI = VIH or VIL; 5.5 VO = VCC or GND − − ±0.25 − ICC quiescent supply current VI = VCC or GND; IO = 0 5.5 − − 4.0 − 40 − 80 µA CI input capacitance − − 3 10 − 10 − 10 pF 2000 Aug 15 7 Philips Semiconductors Product specification 8-bit serial-in/parallel-out shift register 74AHC164; 74AHCT164 74AHCT family With regard to recommended operating conditions; voltages are referenced to GND (ground = 0 V). TEST CONDITIONS SYMBOL Tamb (°C) PARAMETER −40 to +85 25 OTHER VCC (V) −40 to +125 UNIT MIN. TYP. MAX. MIN. MAX. MIN. MAX. VIH HIGH-level input voltage 4.5 to 5.5 2.0 − − 2.0 − 2.0 − V VIL LOW-level input voltage 4.5 to 5.5 − − 0.8 − 0.8 − 0.8 V VOH HIGH-level output voltage VI = VIH or VIL; IO = −50 µA 4.5 4.4 4.5 − 4.4 − 4.4 − V VI = VIH or VIL; IO = −8.0 mA 4.5 3.94 − − 3.8 − 3.70 − V VI = VIH or VIL; IO = 50 µA 4.5 − 0 0.1 − 0.1 − 0.1 V VI = VIH or VIL; IO = 8.0 mA 4.5 − − 0.36 − 0.44 − 0.55 V − 1.0 − 2.0 µA ±2.5 − ±10.0 µA VOL LOW-level output voltage II input leakage current VI = VIH or VIL 5.5 − − 0.1 IOZ 3-state output OFF-state current VI = VIH or VIL; 5.5 VO = VCC or GND per input pin; other inputs at VCC or GND; IO = 0 − − ±0.25 − ICC quiescent supply current VI = VCC or GND; 5.5 IO = 0 − − 4.0 − 40 − 80 µA ∆ICC additional quiescent supply current per input pin VI = VCC − 2.1 V other inputs at VCC or GND; IO = 0 4.5 to 5.5 − − 1.35 − 1.5 − 1.5 mA CI input capacitance − 3 10 − 10 − 10 pF 2000 Aug 15 − 8 Philips Semiconductors Product specification 8-bit serial-in/parallel-out shift register 74AHC164; 74AHCT164 AC CHARACTERISTICS Type 74AHC164 GND = 0 V; tr = tf ≤ 3.0 ns. Tamb (°C) TEST CONDITIONS SYMBOL −40 to +85 25 PARAMETER WAVEFORMS CL −40 to +125 UNIT MIN. TYP. MAX. MIN. MAX. MIN. MAX. VCC = 3.0 to 3.6 V; typical values at VCC = 3.3 V tPHL/tPLH propagation delay CP to Qn see Figs 6 and 9 15 pF − 6.5 12.8 1.0 15.0 1.0 16.0 ns tPHL propagation delay MR to Qn see Figs 7 and 9 − 5.3 12.8 1.0 15.0 1.0 16.0 ns fmax maximum clock pulse frequency see Figs 6 and 9 80 125 − 65 − 50 − MHz tPHL/tPLH propagation delay CP to Qn see Figs 6 and 9 50 pF − 9.3 16.3 1.0 18.5 1.0 20.5 ns tPHL propagation delay MR to Qn see Figs 7 and 9 − 7.6 16.3 1.0 18.5 1.0 20.5 ns tW clock pulse width HIGH see Figs 6 and 9 or LOW 5.0 − − 5.0 − 5.0 − ns master reset pulse width LOW see Figs 7 and 9 5.0 − − 5.0 − 5.0 − ns tsu set-up time Dsa, Dsb to CP see Figs 8 and 9 5.0 − − 6.0 − 6.0 − ns th hold time Dsa, Dsb to CP see Figs 8 and 9 1.5 − − 1.5 − 1.5 − ns trem removal time MR to CP see Figs 7 and 9 2.5 − − 2.5 − 2.5 − ns fmax maximum clock pulse frequency 50 75 − 45 − 35 − MHz 2000 Aug 15 see Figs 6 and 9 9 Philips Semiconductors Product specification 8-bit serial-in/parallel-out shift register 74AHC164; 74AHCT164 TEST CONDITIONS SYMBOL Tamb (°C) PARAMETER −40 to +85 25 WAVEFORMS CL −40 to +125 UNIT MIN. TYP. MAX. MIN. MAX. MIN. MAX. VCC = 4.5 to 5.5 V; typical values at VCC = 5.0 V tPHL/tPLH propagation delay CP to Qn see Figs 6 and 9 15 pF − 4.5 9.0 1.0 10.5 1.0 11.5 ns tPHL propagation delay MR to Qn see Figs 7 and 9 − 4.0 8.6 1.0 10.0 1.0 11.0 ns fmax maximum clock pulse frequency see Figs 6 and 9 125 175 − 105 − 85 − MHz tPHL/tPLH propagation delay CP to Qn see Figs 6 and 9 50 pF − 6.4 11.0 1.0 12.5 1.0 14.0 ns tPHL propagation delay MR to Qn see Figs 7 and 9 − 5.8 10.6 1.0 12.0 1.0 13.5 ns tW clock pulse width HIGH see Figs 6 and 9 or LOW 5.0 − − 5.0 − 5.0 − ns master reset pulse width LOW see Figs 7 and 9 5.0 − − 5.0 − 5.0 − ns tsu set-up time Dsa, Dsb to CP see Figs 8 and 9 4.5 − − 4.5 − 4.5 − ns th hold time Dsa, Dsb to CP see Figs 8 and 9 2.0 − − 2.0 − 2.0 − ns trem removal time MR to CP see Figs 7 and 9 2.5 − − 2.5 − 2.5 − ns fmax maximum clock pulse frequency 85 115 − 75 − 65 − MHz 2000 Aug 15 see Figs 6 and 9 10 Philips Semiconductors Product specification 8-bit serial-in/parallel-out shift register 74AHC164; 74AHCT164 Type 74AHCT164 GND = 0 V; tr = tf ≤ 3.0 ns. TEST CONDITIONS SYMBOL Tamb (°C) −40 to +85 25 PARAMETER WAVEFORMS CL −40 to +125 UNIT MIN. TYP. MAX. MIN. MAX. MIN. MAX. VCC = 4.5 to 5.5 V; typical values at VCC = 5.0 V tPHL/tPLH propagation delay CP to Qn see Figs 6 and 9 15 pF − 3.4 9.0 1.0 10.5 1.0 11.5 ns tPHL propagation delay MR to Qn see Figs 7 and 9 − 3.5 8.6 1.0 10.0 1.0 11.0 ns fmax maximum clock pulse see Figs 6 and 9 frequency 125 175 − 105 − 85 − MHz tPHL/tPLH propagation delay CP to Qn see Figs 6 and 9 50 pF − 4.9 11.0 1.0 12.5 1.0 14.0 ns tPHL propagation delay MR to Qn see Figs 7 and 9 − 5.0 10.6 1.0 12.0 1.0 13.5 ns tW clock pulse width HIGH or LOW see Figs 6 and 9 5.0 − − 5.0 − 5.0 − ns master reset pulse width LOW see Figs 7 and 9 5.0 − − 5.0 − 5.0 − ns tsu set-up time Dsa, Dsb to CP see Figs 8 and 9 4.5 − − 4.5 − 4.5 − ns th hold time Dsa, Dsb to CP see Figs 8 and 9 2.0 − − 2.0 − 2.0 − ns trem removal time MR to CP see Figs 7 and 9 2.5 − − 2.5 − 2.5 − ns fmax maximum clock pulse see Figs 6 and 9 frequency 85 115 − 75 − 65 − MHz 2000 Aug 15 11 Philips Semiconductors Product specification 8-bit serial-in/parallel-out shift register 74AHC164; 74AHCT164 AC WAVEFORMS 1/f max handbook, full pagewidth Vi VM(1) CP input GND tW t PHL t PLH VOH VM(2) Qn output VOL FAMILY VI INPUT REQUIREMENTS MNA601 VM(1) INPUT VM(2) OUTPUT AHC GND to VCC 50% VCC 50% VCC AHCT GND to 3.0 V 1.5 V Fig.6 50% VCC The clock (CP) to output (Qn) propagation delays, the shift clock pulse width (tW) and maximum shift clock frequency (fmax). Vi handbook, full pagewidth VM(1) MR input GND tW t rem Vi VM(1) CP input GND t PHL VOH VM(2) Qn output VOL FAMILY VI INPUT REQUIREMENTS VM(1) INPUT MNA603 VM(2) OUTPUT AHC GND to VCC 50% VCC 50% VCC AHCT GND to 3.0 V 1.5 V Fig.7 50% VCC The master reset (MR) pulse width, the master reset to output (Qn), propagation delays and the master reset clock (CP) removal time (trem). 2000 Aug 15 12 Philips Semiconductors Product specification 8-bit serial-in/parallel-out shift register 74AHC164; 74AHCT164 Vi handbook, full pagewidth VM(1) CP input GND t su t su th th Vi VM(1) Dn input GND VOH VM(2) Qn output VOL MNA602 FAMILY VI INPUT REQUIREMENTS VM(1) INPUT VM(2) OUTPUT AHC GND to VCC 50% VCC 50% VCC AHCT GND to 3.0 V 1.5 V The shaded areas indicate when the input is permitted to change for predictable output performance. 50% VCC Fig.8 The data set-up (tsu) and hold (th) times for the (Dn) input. S1 handbook, full pagewidth VCC PULSE GENERATOR VI 1000 Ω VO VCC open GND D.U.T. CL RT MNA219 TEST S1 tPLH/tPHL open tPLZ/tPZL VCC tPHZ/tPZH GND Definitions for test circuit. CL = load capacitance including jig and probe capacitance (see Chapter “AC characteristics”). RT = termination resistance should be equal to the output impedance Zo of the pulse generator. Fig.9 Load circuit for switching times. 2000 Aug 15 13 Philips Semiconductors Product specification 8-bit serial-in/parallel-out shift register 74AHC164; 74AHCT164 PACKAGE OUTLINES SO14: plastic small outline package; 14 leads; body width 3.9 mm SOT108-1 D E A X c y HE v M A Z 8 14 Q A2 A (A 3) A1 pin 1 index θ Lp 1 L 7 e 0 detail X w M bp 2.5 5 mm scale DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (1) e HE L Lp Q v w y Z (1) mm 1.75 0.25 0.10 1.45 1.25 0.25 0.49 0.36 0.25 0.19 8.75 8.55 4.0 3.8 1.27 6.2 5.8 1.05 1.0 0.4 0.7 0.6 0.25 0.25 0.1 0.7 0.3 0.010 0.057 0.004 0.049 0.01 0.019 0.0100 0.35 0.014 0.0075 0.34 0.16 0.15 0.050 0.028 0.024 0.01 0.01 0.004 0.028 0.012 inches 0.069 0.244 0.039 0.041 0.228 0.016 θ Note 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. REFERENCES OUTLINE VERSION IEC JEDEC SOT108-1 076E06 MS-012 2000 Aug 15 EIAJ EUROPEAN PROJECTION ISSUE DATE 97-05-22 99-12-27 14 o 8 0o Philips Semiconductors Product specification 8-bit serial-in/parallel-out shift register 74AHC164; 74AHCT164 TSSOP14: plastic thin shrink small outline package; 14 leads; body width 4.4 mm SOT402-1 E D A X c y HE v M A Z 8 14 Q (A 3) A2 A A1 pin 1 index θ Lp L 1 7 detail X w M bp e 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (2) e HE L Lp Q v w y Z (1) θ mm 1.10 0.15 0.05 0.95 0.80 0.25 0.30 0.19 0.2 0.1 5.1 4.9 4.5 4.3 0.65 6.6 6.2 1.0 0.75 0.50 0.4 0.3 0.2 0.13 0.1 0.72 0.38 8 0o Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT402-1 2000 Aug 15 REFERENCES IEC JEDEC EIAJ EUROPEAN PROJECTION ISSUE DATE 95-04-04 99-12-27 MO-153 15 o Philips Semiconductors Product specification 8-bit serial-in/parallel-out shift register SOLDERING 74AHC164; 74AHCT164 If wave soldering is used the following conditions must be observed for optimal results: Introduction to soldering surface mount packages • Use a double-wave soldering method comprising a turbulent wave with high upward pressure followed by a smooth laminar wave. This text gives a very brief insight to a complex technology. A more in-depth account of soldering ICs can be found in our “Data Handbook IC26; Integrated Circuit Packages” (document order number 9398 652 90011). • For packages with leads on two sides and a pitch (e): – larger than or equal to 1.27 mm, the footprint longitudinal axis is preferred to be parallel to the transport direction of the printed-circuit board; There is no soldering method that is ideal for all surface mount IC packages. Wave soldering is not always suitable for surface mount ICs, or for printed-circuit boards with high population densities. In these situations reflow soldering is often used. – smaller than 1.27 mm, the footprint longitudinal axis must be parallel to the transport direction of the printed-circuit board. Reflow soldering The footprint must incorporate solder thieves at the downstream end. Reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. • For packages with leads on four sides, the footprint must be placed at a 45° angle to the transport direction of the printed-circuit board. The footprint must incorporate solder thieves downstream and at the side corners. Several methods exist for reflowing; for example, infrared/convection heating in a conveyor type oven. Throughput times (preheating, soldering and cooling) vary between 100 and 200 seconds depending on heating method. During placement and before soldering, the package must be fixed with a droplet of adhesive. The adhesive can be applied by screen printing, pin transfer or syringe dispensing. The package can be soldered after the adhesive is cured. Typical reflow peak temperatures range from 215 to 250 °C. The top-surface temperature of the packages should preferable be kept below 230 °C. Typical dwell time is 4 seconds at 250 °C. A mildly-activated flux will eliminate the need for removal of corrosive residues in most applications. Wave soldering Manual soldering Conventional single wave soldering is not recommended for surface mount devices (SMDs) or printed-circuit boards with a high component density, as solder bridging and non-wetting can present major problems. Fix the component by first soldering two diagonally-opposite end leads. Use a low voltage (24 V or less) soldering iron applied to the flat part of the lead. Contact time must be limited to 10 seconds at up to 300 °C. To overcome these problems the double-wave soldering method was specifically developed. When using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 °C. 2000 Aug 15 16 Philips Semiconductors Product specification 8-bit serial-in/parallel-out shift register 74AHC164; 74AHCT164 Suitability of surface mount IC packages for wave and reflow soldering methods SOLDERING METHOD PACKAGE REFLOW(1) WAVE BGA, LFBGA, SQFP, TFBGA not suitable suitable(2) HLQFP, HSQFP, HSOP, HTQFP, HTSSOP, SMS not PLCC(3), SO, SOJ suitable LQFP, QFP, TQFP SSOP, TSSOP, VSO suitable suitable suitable not recommended(3)(4) suitable not recommended(5) suitable Notes 1. All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the maximum temperature (with respect to time) and body size of the package, there is a risk that internal or external package cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). For details, refer to the Drypack information in the “Data Handbook IC26; Integrated Circuit Packages; Section: Packing Methods”. 2. These packages are not suitable for wave soldering as a solder joint between the printed-circuit board and heatsink (at bottom version) can not be achieved, and as solder may stick to the heatsink (on top version). 3. If wave soldering is considered, then the package must be placed at a 45° angle to the solder wave direction. The package footprint must incorporate solder thieves downstream and at the side corners. 4. Wave soldering is only suitable for LQFP, TQFP and QFP packages with a pitch (e) equal to or larger than 0.8 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm. 5. Wave soldering is only suitable for SSOP and TSSOP packages with a pitch (e) equal to or larger than 0.65 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm. 2000 Aug 15 17 Philips Semiconductors Product specification 8-bit serial-in/parallel-out shift register 74AHC164; 74AHCT164 DATA SHEET STATUS DATA SHEET STATUS PRODUCT STATUS DEFINITIONS (1) Objective specification Development This data sheet contains the design target or goal specifications for product development. Specification may change in any manner without notice. Preliminary specification Qualification This data sheet contains preliminary data, and supplementary data will be published at a later date. Philips Semiconductors reserves the right to make changes at any time without notice in order to improve design and supply the best possible product. Product specification Production This data sheet contains final specifications. Philips Semiconductors reserves the right to make changes at any time without notice in order to improve design and supply the best possible product. Note 1. Please consult the most recently issued data sheet before initiating or completing a design. DEFINITIONS DISCLAIMERS Short-form specification The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook. Life support applications These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application. Limiting values definition Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 60134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Right to make changes Philips Semiconductors reserves the right to make changes, without notice, in the products, including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no licence or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified. Application information Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification. 2000 Aug 15 18 Philips Semiconductors Product specification 8-bit serial-in/parallel-out shift register NOTES 2000 Aug 15 19 74AHC164; 74AHCT164 Philips Semiconductors – a worldwide company Argentina: see South America Australia: 3 Figtree Drive, HOMEBUSH, NSW 2140, Tel. +61 2 9704 8141, Fax. +61 2 9704 8139 Austria: Computerstr. 6, A-1101 WIEN, P.O. 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The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights. Printed in The Netherlands 613507/01/pp20 Date of release: 2000 Aug 15 Document order number: 9397 750 07332