PHILIPS PZ3064

INTEGRATED CIRCUITS
PZ3064
64 macrocell CPLD
Product specification
IC27 Data Handbook
1997 Mar 05
Philips Semiconductors
Product specification
64 macrocell CPLD
PZ3064
FEATURES
DESCRIPTION
• Industry’s first TotalCMOS PLD – both CMOS design and
The PZ3064 CPLD (Complex Programmable Logic Device) is the
second in a family of Fast Zero Power (FZP) CPLDs from Philips
Semiconductors. These devices combine high speed and zero
power in a 64 macrocell CPLD. With the FZP design technique,
the PZ3064 offers true pin-to-pin speeds of 10ns, while
simultaneously delivering power that is less than 50µA at standby
without the need for ‘turbo bits’ or other power down schemes. By
replacing conventional sense amplifier methods for implementing
product terms (a technique that has been used in PLDs since the
bipolar era) with a cascaded chain of pure CMOS gates, the
dynamic power is also substantially lower than any competing CPLD
– 70% lower at 50MHz. These devices are the first TotalCMOS
PLDs, as they use both a CMOS process technology and the
patented full CMOS FZP design technique. For 5V applications,
Philips also offers the high speed PZ5064 CPLD that offers these
features in a full 5V implementation.
process technologies
• Fast Zero Power (FZP) design technique provides ultra-low
power and very high speed
• High speed pin-to-pin delays of 10ns
• Ultra-low static power of less than 50µA
• Dynamic power that is 70% lower at 50MHz than competing
devices
• 100% routable with 100% utilization while all pins and all
macrocells are fixed
• Deterministic timing model that is extremely simple to use
• 4 clocks with programmable polarity at every macrocell
• Support for complex asynchronous clocking
• Innovative XPLA architecture combines high speed with
The Philips FZP CPLDs introduce the new patent-pending XPLA
(eXtended Programmable Logic Array) architecture. The XPLA
architecture combines the best features of both PLA and PAL type
structures to deliver high speed and flexible logic allocation that
results in superior ability to make design changes with fixed pinouts.
The XPLA structure in each logic block provides a fast 10ns PAL
path with 5 dedicated product terms per output. This PAL path is
joined by an additional PLA structure that deploys a pool of 32
product terms to a fully programmable OR array that can allocate
the PLA product terms to any output in the logic block. This
combination allows logic to be allocated efficiently throughout the
logic block and supports as many as 37 product terms on an output.
The speed with which logic is allocated from the PLA array to an
output is only 2.5ns, regardless of the number of PLA product terms
used, which results in worst case tPD’s of only 12.5ns from any pin
to any other pin. In addition, logic that is common to multiple outputs
can be placed on a single PLA product term and shared across
multiple outputs via the OR array, effectively increasing design
density.
extreme flexibility
• 1000 erase/program cycles guaranteed
• 20 years data retention guaranteed
• Logic expandable to 37 product terms
• PCI compliant
• Advanced 0.5µ E2CMOS process
• Security bit prevents unauthorized access
• Design entry and verification using industry standard and Philips
CAE tools
• Reprogrammable using industry standard device programmers
• Innovative Control Term structure provides either sum terms or
product terms in each logic block for:
– Programmable 3-State buffer
The PZ3064 CPLDs are supported by industry standard CAE tools
(Cadence, Mentor, Synopsys, Synario, Viewlogic, MINC), using text
(Abel, VHDL, Verilog) and/or schematic entry. Design verification
uses industry standard simulators for functional and timing
simulation. Development is supported on personal computer, Sparc,
and HP platforms. Device fitting uses either Minc or Philips
Semiconductors-developed tools.
– Asynchronous macrocell register preset/reset
• Programmable global 3-State pin facilitates ‘bed of nails’ testing
without using logic resources
• Available in PLCC, TQFP, and PQFP packages
• Available in both Commercial and Industrial grades
The PZ3064 CPLD is reprogrammable using industry standard
device programmers from vendors such as Data I/O, BP
Microsystems, SMS, and others.
Table 1. PZ3064 Features
PZ3064
Usable gates
2000
Maximum inputs
68
Maximum I/Os
64
Number of macrocells
64
Propagation delay (ns)
10
Packages
44-pin PLCC, 44-pin TQFP,
68-pin PLCC, 84-pin PLCC,
100-pin PQFP
PAL is a registered trademark of Advanced Micro Devices, Inc.
1997 Mar 05
82
853–1891 17824
Philips Semiconductors
Product specification
64 macrocell CPLD
PZ3064
ORDERING INFORMATION
ORDER CODE
DESCRIPTION
DESCRIPTION
DRAWING NUMBER
PZ3064-10A44
44-pin PLCC, 10ns tPD
Commercial temp range, 3.3 volt power supply, ± 10%
SOT187-2
PZ3064-12A44
44-pin PLCC, 12ns tPD
Commercial temp range, 3.3 volt power supply, ± 10%
SOT187-2
PZ3064I12A44
44-pin PLCC, 12ns tPD
Industrial temp range, 3.3 volt power supply, ± 10%
SOT187-2
PZ3064I15A44
44-pin PLCC, 15ns tPD
Industrial temp range, 3.3 volt power supply, ± 10%
SOT187-2
PZ3064-10BC
44-pin TQFP, 10ns tPD
Commercial temp range, 3.3 volt power supply, ± 10%
SOT376-1
PZ3064-12BC
44-pin TQFP, 12ns tPD
Commercial temp range, 3.3 volt power supply, ± 10%
SOT376-1
PZ3064I12BC
44-pin TQFP, 12ns tPD
Industrial temp range, 3.3 volt power supply, ± 10%
SOT376-1
PZ3064I15BC
44-pin TQFP, 15ns tPD
Industrial temp range, 3.3 volt power supply, ± 10%
SOT376-1
PZ3064-10A68
68-pin PLCC, 10ns tPD
Commercial temp range, 3.3 volt power supply, ± 10%
SOT188-3
PZ3064-12A68
68-pin PLCC, 12ns tPD
Commercial temp range, 3.3 volt power supply, ± 10%
SOT188-3
PZ3064I12A68
68-pin PLCC, 12ns tPD
Industrial temp range, 3.3 volt power supply, ± 10%
SOT188-3
PZ3064I15A68
68-pin PLCC, 15ns tPD
Industrial temp range, 3.3 volt power supply, ± 10%
SOT188-3
PZ3064-10A84
84-pin PLCC, 10ns tPD
Commercial temp range, 3.3 volt power supply, ± 10%
SOT189-3
PZ3064-12A84
84-pin PLCC, 12ns tPD
Commercial temp range, 3.3 volt power supply, ± 10%
SOT189-3
PZ3064I12A84
84-pin PLCC, 12ns tPD
Industrial temp range, 3.3 volt power supply, ± 10%
SOT189-3
PZ3064I15A84
84-pin PLCC, 15ns tPD
Industrial temp range, 3.3 volt power supply, ± 10%
SOT189-3
PZ3064-10BB1
100-pin PQFP, 10ns tPD
Commercial temp range, 3.3 volt power supply, ± 10%
SOT382-1
PZ3064-12BB1
100-pin PQFP, 12ns tPD
Commercial temp range, 3.3 volt power supply, ± 10%
SOT382-1
PZ3064I12BB1
100-pin PQFP, 12ns tPD
Industrial temp range, 3.3 volt power supply, ± 10%
SOT382-1
PZ3064I15BB1
100-pin PQFP, 15ns tPD
Industrial temp range, 3.3 volt power supply, ± 10%
SOT382-1
XPLA ARCHITECTURE
Logic Block Architecture
Figure 1 shows a high level block diagram of a 64 macrocell device
implementing the XPLA architecture. The XPLA architecture
consists of logic blocks that are interconnected by a Zero-power
Interconnect Array (ZIA). The ZIA is a virtual crosspoint switch. Each
logic block is essentially a 36V16 device with 36 inputs from the ZIA
and 16 macrocells. Each logic block also provides 32 ZIA feedback
paths from the macrocells and I/O pins.
Figure 2 illustrates the logic block architecture. Each logic block
contains control terms, a PAL array, a PLA array, and 16 macrocells.
the 6 control terms can individually be configured as either SUM or
PRODUCT terms, and are used to control the preset/reset and
output enables of the 16 macrocells’ flip-flops. The PAL array
consists of a programmable AND array with a fixed OR array, while
the PLA array consists of a programmable AND array with a
programmable OR array. The PAL array provides a high speed path
through the array, while the PLA array provides increased product
term density.
From this point of view, this architecture looks like many other CPLD
architectures. What makes the CoolRunner family unique is what
is inside each logic block and the design technique used to
implement these logic blocks. The contents of the logic block will be
described next.
1997 Mar 05
Each macrocell has 5 dedicated product terms from the PAL array.
The pin-to-pin tPD of the PZ3064 device through the PAL array is
10ns. If a macrocell needs more than 5 product terms, it simply gets
the additional product terms from the PLA array. The PLA array
consists of 32 product terms, which are available for use by all 16
macrocells. The additional propagation delay incurred by a
macrocell using 1 or all 32 PLA product terms is just 2.5ns. So the
total pin-to-pin tPD for the PZ3064 using 6 to 37 product terms is
12.5ns (10ns for the PAL + 2.5ns for the PLA).
83
Philips Semiconductors
Product specification
64 macrocell CPLD
PZ3064
MC0
MC1
I/O
MC0
LOGIC
BLOCK
36
36
16
16
LOGIC
BLOCK
MC15
MC1
I/O
MC15
16
16
ZIA
MC0
MC1
I/O
MC0
LOGIC
BLOCK
36
36
LOGIC
BLOCK
MC15
MC1
I/O
MC15
16
16
16
16
SP00439
Figure 1. Philips XPLA CPLD Architecture
36 ZIA INPUTS
6
CONTROL
TO 16 MACROCELLS
5
PAL
ARRAY
PLA
ARRAY
(32)
SP00435
Figure 2. Philips Logic Block Architecture
1997 Mar 05
84
Philips Semiconductors
Product specification
64 macrocell CPLD
PZ3064
to control the Output Enable of the macrocell’s output buffers. The
reason there are as many control terms dedicated for the Output
Enable of the macrocell is to insure that all CoolRunner devices
are PCI compliant. The macrocell’s output buffers can also be
always enabled or disabled. All CoolRunner devices also provide a
Global Tri-State (GTS) pin, which, when pulled Low, will 3-State all
the outputs of the device. This pin is provided to support “In-Circuit
Testing” or “Bed-of-Nails Testing”.
Macrocell Architecture
Figure 3 shows the architecture of the macrocell used in the
CoolRunner family. The macrocell consists of a flip-flop that can be
configured as either a D or T type. A D-type flip-flop is generally
more useful for implementing state machines and data buffering. A
T-type flip-flop is generally more useful in implementing counters. All
CoolRunner family members provide both synchronous and
asynchronous clocking and provide the ability to clock off either the
falling or rising edges of these clocks. These devices are designed
such that the skew between the rising and falling edges of a clock
are minimized for clocking integrity. There are 4 clocks available on
the PZ3064 device. Clock 0 (CLK0) is designated as the
“synchronous” clock and must be driven by an external source.
Clock 1 (CLK1), Clock 2 (CLK2), and Clock 3 (CLK3) can either be
used as a synchronous clock (driven by an external source) or as an
asynchronous clock (driven by a macrocell equation).
There are two feedback paths to the ZIA: one from the macrocell,
and one from the I/O pin. The ZIA feedback path before the output
buffer is the macrocell feedback path, while the ZIA feedback path
after the output buffer is the I/O pin ZIA path. When the macrocell is
used as an output, the output buffer is enabled, and the macrocell
feedback path can be used to feedback the logic implemented in the
macrocell. When the I/O pin is used as an input, the output buffer
will be 3-Stated and the input signal will be fed into the ZIA via the
I/O feedback path, and the logic implemented in the buried
macrocell can be fed back to the ZIA via the macrocell feedback
path. It should be noted that unused inputs or I/Os should be
properly terminated.
Two of the control terms (CT0 and CT1) are used to control the
Preset/Reset of the macrocell’s flip-flop. The Preset/Reset feature
for each macrocell can also be disabled. Note that the Power-on
Reset leaves all macrocells in the “zero” state when power is
properly applied. The other 4 control terms (CT2–CT5) can be used
TO ZIA
D/T
Q
INIT
(P or R)
GTS
CLK0
CLK0
GND
CT0
CLK1
CLK1
CT1
CLK2
CLK2
GND
CLK3
CLK3
CT2
CT3
CT4
CT5
VCC
GND
SP00457
Figure 3. PZ3064 Macrocell Architecture
1997 Mar 05
85
Philips Semiconductors
Product specification
64 macrocell CPLD
PZ3064
5 product terms or less, the tPD = 10ns, the tSU_PAL = 6ns, and the
tCO = 7ns. If an output is using 6 to 37 product terms, an additional
2ns must be added to the tPD and tSU timing parameters to account
for the time to propagate through the PLA array.
Simple Timing Model
Figure 4 shows the CoolRunner Timing Model. The CoolRunner
timing model looks very much like a 22V10 timing model in that
there are three main timing parameters, including tPD, tSU, and tCO.
In other competing architectures, the user may be able to fit the
design into the CPLD, but is not sure whether system timing
requirements can be met until after the design has been fit into the
device. This is because the timing models of competing
architectures are very complex and include such things as timing
dependencies on the number of parallel expanders borrowed,
sharable expanders, varying number of X and Y routing channels
used, etc. In the XPLA architecture, the user knows up front
whether the design will meet system timing requirements. This is
due to the simplicity of the timing model. For example, in the
PZ3064 device, the user knows up front that if a given output uses
TotalCMOS Design Technique
for Fast Zero Power
Philips is the first to offer a TotalCMOS CPLD, both in process
technology and design technique. Philips employs a cascade of
CMOS gates to implement its Sum of Products instead of the
traditional sense amp approach. This CMOS gate implementation
allows Philips to offer CPLDs which are both high performance and
low power, breaking the paradigm that to have low power, you must
have low performance. Refer to Figure 5 and Table 2 showing the IDD
vs. Frequency of our PZ3064 TotalCMOS CPLD.
tPD_PAL = COMBINATORIAL PAL ONLY
tPD_PLA = COMBINATORIAL PAL + PLA
INPUT PIN
REGISTERED
tSU_PAL = PAL ONLY
tSU_PLA = PAL + PLA
INPUT PIN
D
Q
OUTPUT PIN
REGISTERED
tCO
OUTPUT PIN
CLOCK
SP00441
Figure 4. CoolRunner Timing Model
100
80
IDD
(mA)
TYPICAL
60
40
20
0
0
20
40
60
80
100
FREQUENCY (MHz)
SP00460A
Figure 5. IDD vs. Frequency @ VDD = 3.3V, 25°C
Table 2. IDD vs. Frequency
VDD = 3.3V
FREQUENCY (MHz)
0
20
40
60
80
100
Typical IDD ( mA)
0.04
13
26
40
50
63
1997 Mar 05
86
Philips Semiconductors
Product specification
64 macrocell CPLD
PZ3064
ABSOLUTE MAXIMUM RATINGS4
MIN.
MAX.
UNIT
VDD
Supply voltage
PARAMETER
–0.5
7.0
V
VI
Input voltage
–1.2
VDD+0.5
V
VOUT
Output voltage
–0.5
VDD+0.5
V
IIN
Input current
–30
30
mA
IOUT
Output current
–100
100
mA
TJ
Maximum junction temperature
–40
150
°C
Tstr
Storage temperature
–65
150
°C
SYMBOL
NOTES:
4. Stresses above those listed may cause malfunction or permanent damage to the device. This is a stress rating only. Functional operation at
these or any other condition above those indicated in the operational and programming specification is not implied.
OPERATING RANGE
1997 Mar 05
PRODUCT GRADE
TEMPERATURE
VOLTAGE
Commercial
0 to +70°C
3.3 ±10% V
Industrial
–40 to +85°C
3.3 ±10% V
87
Philips Semiconductors
Product specification
64 macrocell CPLD
PZ3064
DC ELECTRICAL CHARACTERISTICS FOR COMMERCIAL GRADE DEVICES
Commercial: 0°C ≤ Tamb ≤ +70°C; 3.0V ≤ VDD ≤ 3.6V
SYMBOL
PARAMETER
TEST CONDITIONS
MIN.
MAX.
UNIT
0.8
V
VIL
Input voltage low
VDD = 3.0V
VIH
Input voltage high
VDD = 3.6V
VI
Input clamp voltage
VDD = 3.0V, IIN = –18mA
–1.2
V
VOL
Output voltage low
VDD = 3.0V, IOL = 8mA
0.5
V
VOH
Output voltage high
VDD = 3.0V, IOH = –8mA
2.4
II
Input leakage current
VIN = 0 to VDD
–10
10
µA
IOZ
3-Stated output leakage current
VIN = 0 to VDD
–10
10
µA
IDDQ
Standby current
50
µA
IDDD1
Dynamic current
VDD = 3.6V, Tamb = 0°C @ 1MHz
1
mA
VDD = 3.6V, Tamb = 0°C @ 50MHz
40
mA
IOS
Short circuit output current
–5
–100
mA
CIN
Input pin capacitance
Tamb = 25°C, f = 1MHz
8
pF
CCLK
Clock input capacitance
Tamb = 25°C, f = 1MHz
5
12
pF
CI/O
I/O pin capacitance
Tamb = 25°C, f = 1MHz
10
pF
2.0
V
V
VDD = 3.6V, Tamb = 0°C
1 pin at a time for no longer than 1 second
NOTE:
1. This parameter measured with a 16-bit, loadable up/down counter loaded into every logic block, with all outputs enabled and unloaded.
Inputs are tied to VDD or ground. This parameter guaranteed by design and characterization, not testing.
AC ELECTRICAL CHARACTERISTICS1 FOR COMMERCIAL GRADE DEVICES
Commercial: 0°C ≤ Tamb ≤ +70°C; 3.0V ≤ VDD ≤ 3.6V
SYMBOL
–10
PARAMETER
MIN.
–12
MAX.
MIN.
MAX.
UNIT
tPD_PAL
Propagation delay time, input (or feedback node) to output through PAL
2
10
2
12
ns
tPD_PLA
Propagation delay time, input (or feedback node) to output through PAL & PLA
3
12.5
3
14.5
ns
tCO
Clock to out delay time
2
7
2
8
ns
tSU_PAL
Setup time (from input or feedback node) through PAL
tSU_PLA
Setup time (from input or feedback node) through PAL + PLA
tH
Hold time
tCH
Clock High time
4
5
ns
tCL
Clock Low time
4
5
ns
tR
Input Rise time
20
20
tF
Input Fall time
20
20
fMAX1
Maximum FF toggle rate2
fMAX2
Maximum internal frequency2
fMAX3
Maximum external frequency2
tBUF
Output buffer delay time
1.5
1.5
ns
tPDF_PAL
Input (or feedback node) to internal feedback node delay time through PAL
8.5
10.5
ns
tPDF_PLA
Input (or feedback node) to internal feedback node delay time through PAL+PLA
11
13
ns
tCF
Clock to internal feedback node delay time
5.5
6.5
ns
tINIT
Delay from valid VDD to valid reset
50
50
µs
tER
Input to output disable3
12.5
14
ns
tEA
Input to output valid
12.5
14
ns
tRP
Input to register preset
15
16
ns
tRR
Input to register reset
15
16
ns
7
ns
8
9.5
ns
0
(1/tCH + tCL)
0
ns
ns
ns
125
100
MHz
(1/tSUPAL + tCF)
91
74
MHz
(1/tSUPAL + tCO)
80
67
NOTES:
1. Specifications measured with one output switching. See Figure 6 and Table 3 for derating.
2. This parameter guaranteed by design and characterization, not by test.
3. Output CL = 5pF.
1997 Mar 05
5.5
88
MHz
Philips Semiconductors
Product specification
64 macrocell CPLD
PZ3064
DC ELECTRICAL CHARACTERISTICS FOR INDUSTRIAL GRADE DEVICES
Industrial:
–40°C ≤ Tamb ≤ +85°C; 3.0V ≤ VDD ≤ 3.6V
SYMBOL
PARAMETER
TEST CONDITIONS
MIN.
MAX.
UNIT
0.8
V
VIL
Input voltage low
VDD = 3.0V
VIH
Input voltage high
VDD = 3.6V
VI
Input clamp voltage
VDD = 3.0V, IIN = –18mA
–1.2
V
VOL
Output voltage low
VDD = 3.0V, IOL = 8mA
0.5
V
VOH
Output voltage high
VDD = 3.0V, IOH = –8mA
2.4
II
Input leakage current
VIN = 0 to VDD
–10
10
µA
IOZ
3-Stated output leakage current
VIN = 0 to VDD
–10
10
µA
IDDQ
Standby current
50
µA
IDDD1
Dynamic current
VDD = 3.6V, Tamb = –40°C @ 1MHz
1
mA
VDD = 3.6V, Tamb = –40°C @ 50MHz
40
mA
IOS
Short circuit output current
–5
–130
mA
CIN
Input pin capacitance
Tamb = 25°C, f = 1MHz
8
pF
CCLK
Clock input capacitance
Tamb = 25°C, f = 1MHz
5
12
pF
CI/O
I/O pin capacitance
Tamb = 25°C, f = 1MHz
10
pF
2.0
V
V
VDD = 3.6V, Tamb = –40°C
1 pin at a time for no longer than 1 second
NOTE:
1. This parameter measured with a 16–bit, loadable up/down counter loaded into every logic block, with all outputs enabled and unloaded.
Inputs are tied to VDD or ground. This parameter guaranteed by design and characterization, not testing.
AC ELECTRICAL CHARACTERISTICS1 FOR INDUSTRIAL GRADE DEVICES
Industrial:
–40°C ≤ Tamb ≤ +85°C; 3.0V ≤ VDD ≤ 3.6V
SYMBOL
I12
PARAMETER
MIN.
I15
MAX.
MIN.
MAX.
UNIT
tPD_PAL
Propagation delay time, input (or feedback node) to output through PAL
2
12
2
15
ns
tPD_PLA
Propagation delay time, input (or feedback node) to output through PAL & PLA
3
14.5
3
17.5
ns
tCO
Clock to out delay time
2
8
2
9
ns
tSU_PAL
Setup time (from input or feedback node) through PAL
7
8
ns
tSU_PLA
Setup time (from input or feedback node) through PAL + PLA
9.5
10.5
ns
tH
Hold time
tCH
Clock High time
5
5
ns
tCL
Clock Low time
5
5
ns
tR
Input Rise time
20
20
tF
Input Fall time
20
20
fMAX1
Maximum FF toggle rate2
fMAX2
Maximum internal frequency2
fMAX3
Maximum external frequency2
tBUF
Output buffer delay time
1.5
1.5
ns
tPDF_PAL
Input (or feedback node) to internal feedback node delay time through PAL
10.5
13.5
ns
tPDF_PLA
Input (or feedback node) to internal feedback node delay time through PAL+PLA
13
16
ns
tCF
Clock to internal feedback node delay time
6.5
7.5
ns
tINIT
Delay from valid VDD to valid reset
50
50
µs
tER
Input to output disable3
14
15
ns
tEA
Input to output valid
14
15
ns
tRP
Input to register preset
16
17
ns
tRR
Input to register reset
16
17
ns
0
(1/tCH + tCL)
ns
ns
ns
100
100
MHz
(1/tSUPAL + tCF)
74
65
MHz
(1/tSUPAL + tCO)
67
58
NOTES:
1. Specifications measured with one output switching. See Figure 6 and Table 3 for derating.
2. This parameter guaranteed by design and characterization, not by test.
3. Output CL = 5pF.
1997 Mar 05
0
89
MHz
Philips Semiconductors
Product specification
64 macrocell CPLD
PZ3064
SWITCHING CHARACTERISTICS
The test load circuit and load values for the AC Electrical Characteristics are illustrated below.
VDD
S1
COMPONENT
VALUES
R1
390Ω
R2
390Ω
C1
35pF
MEASUREMENT
S1
S2
tPZH
Open
Closed
tPZL
Closed
Open
tP
Closed
Closed
R1
VIN
VOUT
R2
C1
S2
NOTE: For tPHZ and tPLZ C = 5pF
SP00461A
VOLTAGE WAVEFORM
10.00
VDD = 3.3V, 25°C
+3.0V
9.80
90%
9.60
10%
0V
9.40
tR
tPD_PAL
(ns)
tF
1.5ns
9.20
9.00
1.5ns
MEASUREMENTS:
All circuit delays are measured at the +1.5V level of
inputs and outputs, unless otherwise specified.
8.80
Input Pulses
8.60
8.40
8.20
8.00
1
2
4
8
12
16
NUMBER OF OUTPUTS SWITCHING
SP00462
Figure 6. tPD_PAL vs. Outputs Switching
Table 3. tPD_PAL vs. Number of Outputs Switching
VDD = 3.3V
NUMBER OF
OUTPUTS
1
2
4
8
12
16
Typical (ns)
8.0
8.4
8.8
9.2
9.6
10.0
1997 Mar 05
90
SP00368
Philips Semiconductors
Product specification
64 macrocell CPLD
PZ3064
PIN DESCRIPTIONS
PZ3064 – 44-Pin Plastic Leaded Chip Carrier
6
1
PZ3064 – 68-Pin Plastic Leaded Chip Carrier
40
7
9
39
60
LCC
17
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
*
Function
IN1
IN3
VDD
I/O-A0/CK3
I/O-A2
I/O-A5
I/O-A8 (TDI)
I/O-A11
I/O-A12
GND
I/O-A13
I/O-A15
I/O-B15 (TMS)*
I/O-B13
VDD
26
29
Pin
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
28
Function
I/O-C13
I/O-C15 (TCK)
I/O-D15
I/O-D13
VDD
I/O-D12
I/O-D11
I/O-D8 (TDO)
I/O-D7
I/O-D2
I/O-D0
GND
IN0-CK0
IN2-gtsn
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
THE TEST MODE SELECT (TMS) FUNCTION IS
INACTIVE ON NON-ISR ARCHITECTURES.
SP00452A
PZ3064 – 44-Pin Thin Quad Flat Package
*
33
23
11
*
Function
I/O-A8
I/O-A11
I/O-A12
GND
I/O-A13
I/O-A15
I/O-B15 (TMS)*
I/O-B13
VDD
I/O-B10
I/O-B8
I/O-B4
I/O-B3
I/O-B2
I/O-B0/CK2
Pin
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
22
Function
GND
VDD
I/O-C0/CK1
I/O-C2
I/O-C3
I/O-C4
I/O-C7
I/O-C8
GND
I/O-C13
I/O-C15 (TCK)
I/O-D15
I/O-D13
VDD
I/O-D12
Pin
31
32
33
34
35
36
37
38
39
40
41
42
43
44
Function
I/O-D11
I/O-D8 (TDO)
I/O-D7
I/O-D2
I/O-D0
GND
IN0/CK0
IN2-gtsn
IN1
IN3
VDD
I/O-A0/CK3
I/O-A2
I/O-A5
THE TEST MODE SELECT (TMS) FUNCTION IS
INACTIVE ON NON-ISR ARCHITECTURES.
SP00453
1997 Mar 05
Pin
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
Function
I/O-B10
I/O-B8
GND
I/O-B7
I/O-B5
I/O-B4
I/O-B3
VDD
I/O-B2
I/O-B0/CK2
GND
VDD
I/O-C0/CK1
I/O-C2
GND
I/O-C3
I/O-C4
I/O-C5
I/O-C7
VDD
I/O-C8
I/O-C10
I/O-C11
Pin
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
Function
I/O-C12
GND
I/O-D13
I/O-C15 (TCK)
I/O-D15
I/O-D13
VDD
I/O-D12
I/O-D11
I/O-D9
I/O-D8 (TDO)
GND
I/O-D7
I/O-D6
I/O-D4
I/O-D3
VDD
I/O-D2
I/O-D0
GND
IN0/CK0
IN2-gtsn
THE TEST MODE SELECT (TMS) FUNCTION IS
INACTIVE ON NON-ISR ARCHITECTURES.
SP00454
QFP
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
Function
IN1
IN3
VDD
I/O-A0/CK3
I/O-A2
GND
I/O-A3
I/O-A4
I/O-A5
I/O-A7
VDD
I/O-A8 (TDI)
I/O-A10
I/O-A11
I/O-A12
GND
I/O-A13
I/O-A15
I/O-B15 (TMS)*
I/O-B13
VDD
I/O-B12
I/O-B11
43
34
1
12
44
27
Pin
31
32
33
34
35
36
37
38
39
40
41
42
43
44
Function
I/O-B10
I/O-B8
I/O-B4
I/O-B3
I/O-B2
I/O-B0/CK2
GND
VDD
I/O-C0/CK1
I/O-C2
I/O-C3
I/O-C4
I/O-C7
I/O-C8
GND
44
61
10
LCC
18
1
91
Philips Semiconductors
Product specification
64 macrocell CPLD
PZ3064
PZ3064 – 84-Pin Plastic Leaded Chip Carrier
11
1
PZ3064 – 100-Pin Plastic Quad Flat Package
100
75
12
1
74
80
QFP
LCC
32
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
*
Function
IN1
IN3
VDD
I/O-A0/CK3
I/O-A1
I/O-A2
GND
I/O-A3
I/O-A4
I/O-A5
I/O-A6
I/O-A7
VCC
I/O-A8 (TDI)
I/O-A9
I/O-A10
I/O-A11
I/O-A12
GND
I/O-A13
I/O-A14
I/O-B15
I/O-B15 (TMS)*
I/O-B14
I/O-B13
VDD
I/O-B12
I/O-B11
Pin
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
31
53
Function
I/O-B10
I/O-B9
I/O-B8
GND
I/O-B7
I/O-B6
I/O-B5
I/O-B4
I/O-B3
VDD
I/O-B2
I/O-B1
I/O-B0/CK2
GND
VDD
I/O-C0/CK1
I/O-C1
I/O-C2
GND
I/O-C3
I/O-C4
I/O-C5
I/O-C6
I/O-C7
VDD
I/O-C8
I/O-C9
I/O-C10
51
30
54
33
81
Pin
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
Function
I/O-C11
I/O-C12
GND
I/O-C13
I/O-C14
I/O-C15 (TCK)
I/O-D15
I/O-D14
I/O-D13
VDD
I/O-D12
I/O-D11
I/O-D10
I/O-D9
I/O-D8 (TDO)
GND
I/O-D7
I/O-D6
I/O-D5
I/O-D4
I/O-D3
VDD
I/O-D2
I/O-D1
I/O-D0
GND
IN0/CK0
IN2-gtsn
THE TEST MODE SELECT (TMS) FUNCTION IS
INACTIVE ON NON-ISR ARCHITECTURES.
SP00455
*
Function
NC
NC
I/O-A6
I/O-A7
VDD
I/O-A8 (TDI)
NC
I/O-A9
NC
I/O-A10
I/O-A11
I/O-A12
GND
I/O-A13
I/O-A14
I/O-A15
I/O-B15 (TMS)*
I/O-B14
I/O-B13
VDD
I/O-B12
I/O-B11
I/O-B10
NC
I/O-B9
NC
I/O-B8
GND
NC
NC
I/O-B7
I/O-B6
I/O-B5
I/O-B4
Pin
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
50
Function
I/O-B3
VDD
I/O-B2
I/O-B1
I/O-B0/CK2
GND
VDD
I/O-C0/CK1
I/O-C1
I/O-C2
GND
I/O-C3
I/O-C4
I/O-C5
I/O-C6
I/O-C7
NC
NC
VDD
I/O-C8
NC
I/O-C9
NC
I/O-C10
I/O-C11
I/O-C12
GND
I/O-C13
I/O-C14
I/O-C15 (TCK)
I/O-D15
I/O-D14
I/O-D13
VDD
Pin
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
Function
I/O-D12
I/O-D11
I/O-D10
NC
I/O-D9
NC
I/O-D8 (TDO)
GND
I/O-D7
I/O-D6
NC
NC
I/O-D5
I/O-D4
I/O-D3
VDD
I/O-D2
I/O-D1
I/O-D0
GND
IN0/CK0
IN2-gtsn
IN1
IN3
VDD
I/O-A0/CK3
I/O-A1
I/O-A2
GND
I/O-A3
I/O-A4
I/O-A5
THE TEST MODE SELECT (TMS) FUNCTION IS
INACTIVE ON NON-ISR ARCHITECTURES.
SP00456
1997 Mar 05
92
Philips Semiconductors
Product specification
64 macrocell CPLD
PZ3064
Package Thermal Characteristics
Philips Semiconductors uses the Temperature Sensitive Parameter
(TSP) method to test thermal resistance. This method meets
Mil-Std-883C Method 1012.1 and is described in Philips 1995 IC
Package Databook. Thermal resistance varies slightly as a function
of input power. As input power increases, thermal resistance
changes approximately 5% for a 100% change in power.
PERCENTAGE
REDUCTION IN
ΘJA (%)
10
20
Figure 7 is a derating curve for the change in ΘJA with airflow based
on wind tunnel measurements. It should be noted that the wind flow
dynamics are more complex and turbulent in actual applications
than in a wind tunnel. Also, the test boards used in the wind tunnel
contribute significantly to forced convection heat transfer, and may
not be similar to the actual circuit board, especially in size.
44-pin PLCC
44.8°C/W
44-pin TQFP
60.8°C/W
68-pin PLCC
44.9°C/W
84-pin PLCC
34.7°C/W
100-pin PQFP
44.5°C/W
1997 Mar 05
30
40
PLCC/
QFP
50
ΘJA
Package
0
0
1
2
3
4
5
AIR FLOW (m/s)
SP00419A
Figure 7. Average Effect of Airflow on ΘJA
93
Philips Semiconductors
Product specification
64 macrocell CPLD
PZ3064
PLCC44: plastic leaded chip carrier; 44 leads
1997 Mar 05
SOT187-2
94
Philips Semiconductors
Product specification
64 macrocell CPLD
PZ3064
TQFP44: plastic thin quad flat package; 44 leads; body 10 x 10 x 1.0 mm
1997 Mar 05
95
SOT376-1
Philips Semiconductors
Product specification
64 macrocell CPLD
PZ3064
PLCC68: plastic leaded chip carrier; 68 leads; pedestal
1997 Mar 05
96
SOT188-3
Philips Semiconductors
Product specification
64 macrocell CPLD
PZ3064
PLCC84: plastic leaded chip carrier; 84 leads; pedestal
1997 Mar 05
97
SOT189-3
Philips Semiconductors
Product specification
64 macrocell CPLD
PZ3064
QFP100: plastic quad flat package; 100 leads (lead length 1.6 mm); body 14 x 20 x 2.8 mm
1997 Mar 05
98
SOT382-1
Philips Semiconductors
Product specification
64 macrocell CPLD
PZ3064
NOTES
1997 Mar 05
99
Philips Semiconductors
Product specification
64 macrocell CPLD
PZ3064
DEFINITIONS
Data Sheet Identification
Product Status
Definition
Objective Specification
Formative or in Design
This data sheet contains the design target or goal specifications for product development. Specifications
may change in any manner without notice.
Preliminary Specification
Preproduction Product
This data sheet contains preliminary data, and supplementary data will be published at a later date. Philips
Semiconductors reserves the right to make changes at any time without notice in order to improve design
and supply the best possible product.
Product Specification
Full Production
This data sheet contains Final Specifications. Philips Semiconductors reserves the right to make changes
at any time without notice, in order to improve design and supply the best possible product.
Philips Semiconductors and Philips Electronics North America Corporation reserve the right to make changes, without notice, in the products,
including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. Philips
Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright,
or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask
work right infringement, unless otherwise specified. Applications that are described herein for any of these products are for illustrative purposes
only. Philips Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing
or modification.
LIFE SUPPORT APPLICATIONS
Philips Semiconductors and Philips Electronics North America Corporation Products are not designed for use in life support appliances, devices,
or systems where malfunction of a Philips Semiconductors and Philips Electronics North America Corporation Product can reasonably be expected
to result in a personal injury. Philips Semiconductors and Philips Electronics North America Corporation customers using or selling Philips
Semiconductors and Philips Electronics North America Corporation Products for use in such applications do so at their own risk and agree to fully
indemnify Philips Semiconductors and Philips Electronics North America Corporation for any damages resulting from such improper use or sale.
 Copyright Philips Electronics North America Corporation 1997
All rights reserved. Printed in U.S.A.
Philips Semiconductors
811 East Arques Avenue
P.O. Box 3409
Sunnyvale, California 94088–3409
Telephone 800-234-7381
1997 Mar 05
100