PHILIPS SSTUP32866EC/G

SSTUP32866
1.8 V 25-bit 1 : 1 or 14-bit 1 : 2 configurable registered buffer
with parity and programmable output for DDR2-800 RDIMMs
Rev. 02 — 14 September 2006
Product data sheet
1. General description
The SSTUP32866 is a 1.8 V configurable register specifically designed for use on DDR2
memory modules requiring a parity checking function. It is defined in accordance with the
JEDEC standard for the SSTUA32866 and SSTUB32866 registered buffers. The register
is configurable (using configuration pins C0 and C1) to two topologies: 25-bit 1 : 1 or
14-bit 1 : 2, and in the latter configuration can be designated as Register A or Register B
on the DIMM. It offers added features over the JEDEC standard register in that it can be
configured for high or normal output drive strength, as well as for operation to 667 MT/s or
800 MT/s, simply by tying two input pins HIGH or LOW as needed.
The SSTUP32866 accepts a parity bit from the memory controller on its parity bit
(PAR_IN) input, compares it with the data received on the DIMM-independent D-inputs
and indicates whether a parity error has occurred on its open-drain QERR pin
(active LOW). The convention is even parity, that is, valid parity is defined as an even
number of ones across the DIMM-independent data inputs combined with the parity input
bit.
The SSTUP32866 is packaged in a 96-ball, 6 × 16 grid, 0.8 mm ball pitch LFBGA
package (13.5 mm × 5.5 mm).
2. Features
n Configurable register supporting DDR2 up to 667 MT/s or 800 MT/s Registered DIMM
applications
n Configurable to 25-bit 1 : 1 mode or 14-bit 1 : 2 mode
n Programmable for normal or high output drive
n Controlled multi-impedance output drivers enable optimal signal integrity and speed
n Programmable for 667 MT/s or 800 MT/s speed
n Excellent propagation delay performance
n Supports up to 450 MHz clock frequency of operation
n Optimized pinout for high-density DDR2 module design
n Chip-selects minimize power consumption by gating data outputs from changing state
n Supports SSTL_18 data inputs
n Checks parity on the DIMM-independent data inputs
n Partial parity output and input allows cascading of two SSTUP32866s for correct parity
error processing
n Differential clock (CK and CK) inputs
n Supports LVCMOS switching levels on the control and RESET inputs
n Single 1.8 V supply operation (1.7 V to 2.0 V)
SSTUP32866
Philips Semiconductors
1.8 V DDR2-667/800 programmable registered buffer with parity
n Available in 96-ball, 13.5 mm × 5.5 mm, 0.8 mm ball pitch LFBGA package
3. Applications
n 667 MT/s to 800 MT/s DDR2 registered DIMMs desiring parity checking functionality
4. Ordering information
Table 1.
Ordering information
Type number
Solder process
Package
Name
Description
Version
SSTUP32866EC/G
Pb-free (SnAgCu solder LFBGA96 plastic low profile fine-pitch ball grid array package; SOT536-1
ball compound)
96 balls; body 13.5 × 5.5 × 1.05 mm
SSTUP32866EC/S
Pb-free (SnAgCu solder LFBGA96 plastic low profile fine-pitch ball grid array package; SOT536-1
ball compound)
96 balls; body 13.5 × 5.5 × 1.05 mm
4.1 Ordering options
Table 2.
Ordering options
Type number
Temperature range
SSTUP32866EC/G
Tamb = 0 °C to +70 °C
SSTUP32866EC/S
Tamb = 0 °C to +85 °C
SSTUP32866_2
Product data sheet
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Rev. 02 — 14 September 2006
2 of 31
SSTUP32866
Philips Semiconductors
1.8 V DDR2-667/800 programmable registered buffer with parity
5. Functional diagram
RESET
CK
CK
SSTUP32866
VREF
DCKE
DODT
DCS
1D
C1
QCKEA
R
QCKEB(1)
1D
C1
R
QODTA
1D
C1
R
QCSA
1D
C1
R
Q2A
QODTB(1)
QCSB(1)
CSR
D2
0
1
to 10 other channels
(D3, D5, D6, D8 to D14)
Q2B(1)
002aab869
(1) Disabled in 1 : 1 configuration.
Fig 1. Functional diagram of SSTUP32866; 1 : 2 Register A configuration with C0 = 0 and
C1 = 1 (positive logic)
SSTUP32866_2
Product data sheet
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Rev. 02 — 14 September 2006
3 of 31
SSTUP32866
Philips Semiconductors
1.8 V DDR2-667/800 programmable registered buffer with parity
RESET
CK
CK
LPS0
(internal node)
D2, D3, D5, D6,
D8 to D14
VREF
11
CE
11
D2, D3, D5, D6,
11 D8 to D14
D
CLK
11
R
D2, D3, D5, D6,
D8 to D14
11
Q2A, Q3A,
Q5A, Q6A,
Q8A to Q14A
Q2B, Q3B,
Q5B, Q6B,
Q8B to Q14B
PARITY
CHECK
C1
1
0
1
D
CLK
R
PPO
D
CLK
R
CE
0
D
CLK
R
PAR_IN
QERR
C0
CLK
2-BIT
COUNTER
R
LPS1
(internal node)
0
D
CLK
R
1
002aaa650
Fig 2. Parity logic diagram for 1 : 2 Register A configuration (positive logic); C0 = 0, C1 = 1
SSTUP32866_2
Product data sheet
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Rev. 02 — 14 September 2006
4 of 31
SSTUP32866
Philips Semiconductors
1.8 V DDR2-667/800 programmable registered buffer with parity
6. Pinning information
6.1 Pinning
SSTUP32866EC/G
ball A1 SSTUP32866EC/S
index area
1 2 3 4 5 6
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
002aab870
Transparent top view
Fig 3. Pin configuration for LFBGA96
1
2
3
4
5
6
A
DCKE
PPO
VREF
VDD
QCKE
DNU
B
D2
D15
GND
GND
Q2
Q15
C
D3
D16
VDD
VDD
Q3
Q16
D
DODT
QERR
GND
GND
QODT
DNU
E
D5
D17
VDD
VDD
Q5
Q17
F
D6
D18
GND
GND
Q6
Q18
G
PAR_IN
RESET
VDD
VDD
C1
C0
H
CK
DCS
GND
GND
QCS
DNU
J
CK
CSR
VDD
VDD
SELAB
SELDR
K
D8
D19
GND
GND
Q8
Q19
L
D9
D20
VDD
VDD
Q9
Q20
M
D10
D21
GND
GND
Q10
Q21
N
D11
D22
VDD
VDD
Q11
Q22
P
D12
D23
GND
GND
Q12
Q23
R
D13
D24
VDD
VDD
Q13
Q24
T
D14
D25
VREF
VDD
Q14
Q25
002aab871
Fig 4. Ball mapping, 1 : 1 register (C0 = 0, C1 = 0)
SSTUP32866_2
Product data sheet
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Rev. 02 — 14 September 2006
5 of 31
SSTUP32866
Philips Semiconductors
1.8 V DDR2-667/800 programmable registered buffer with parity
1
2
3
4
5
6
A
DCKE
PPO
VREF
VDD
QCKEA
QCKEB
B
D2
DNU
GND
GND
Q2A
Q2B
C
D3
DNU
VDD
VDD
Q3A
Q3B
D
DODT
QERR
GND
GND
QODTA
QODTB
E
D5
n.c.
VDD
VDD
Q5A
Q5B
F
D6
n.c.
GND
GND
Q6A
Q6B
G
PAR_IN
RESET
VDD
VDD
C1
C0
H
CK
DCS
GND
GND
QCSA
QCSB
J
CK
CSR
VDD
VDD
SELAB
SELDR
K
D8
DNU
GND
GND
Q8A
Q8B
L
D9
DNU
VDD
VDD
Q9A
Q9B
M
D10
DNU
GND
GND
Q10A
Q10B
N
D11
DNU
VDD
VDD
Q11A
Q11B
P
D12
DNU
GND
GND
Q12A
Q12B
R
D13
DNU
VDD
VDD
Q13A
Q13B
T
D14
DNU
VREF
VDD
Q14A
Q14B
002aab872
Fig 5. Ball mapping, 1 : 2 Register A (C0 = 0, C1 = 1)
1
2
3
4
5
6
A
D1
PPO
VREF
VDD
Q1A
Q1B
B
D2
DNU
GND
GND
Q2A
Q2B
C
D3
DNU
VDD
VDD
Q3A
Q3B
D
D4
QERR
GND
GND
Q4A
Q4B
E
D5
DNU
VDD
VDD
Q5A
Q5B
F
D6
DNU
GND
GND
Q6A
Q6B
G
PAR_IN
RESET
VDD
VDD
C1
C0
H
CK
DCS
GND
GND
QCSA
QCSB
J
CK
CSR
VDD
VDD
SELAB
SELDR
K
D8
DNU
GND
GND
Q8A
Q8B
L
D9
DNU
VDD
VDD
Q9A
Q9B
M
D10
DNU
GND
GND
Q10A
Q10B
N
DODT
DNU
VDD
VDD
QODTA
QODTB
P
D12
DNU
GND
GND
Q12A
Q12B
R
D13
DNU
VDD
VDD
Q13A
Q13B
T
DCKE
DNU
VREF
VDD
QCKEA
QCKEB
002aab873
Fig 6. Ball mapping, 1 : 2 Register B (C0 = 1, C1 = 1)
SSTUP32866_2
Product data sheet
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Rev. 02 — 14 September 2006
6 of 31
SSTUP32866
Philips Semiconductors
1.8 V DDR2-667/800 programmable registered buffer with parity
6.2 Pin description
Table 3.
Pin description
Symbol
Pin
Type
Description
GND
B3, B4, D3, D4,
F3, F4, H3, H4,
K3, K4, M3, M4,
P3, P4
ground input
ground
VDD
A4, C3, C4, E3,
E4, G3, G4, J3,
J4, L3, L4, N3,
N4, R3, R4, T4
1.8 V nominal
power supply voltage
VREF
A3, T3
0.9 V nominal
input reference voltage
CK
H1
differential input
positive master clock input
CK
J1
differential input
negative master clock input
C0
G6
LVCMOS inputs
C1
G5
Configuration control inputs; Register A
or Register B and 1 : 1 mode or
1 : 2 mode select.
SELDR
J6
LVCMOS input
Selects output drive strength: HIGH for
normal drive, LOW for high drive. This pin
will default HIGH if left open-circuit
(built-in weak pull-up resistor).
SELAB
J5
LVCMOS input
Selects speed grade: HIGH for
DDR2-667, LOW for DDR2-800. This pin
will default HIGH if left open-circuit
(built-in weak pull-up resistor).
RESET
G2
LVCMOS input
Asynchronous reset input (active LOW).
Resets registers and disables VREF data
and clock.
CSR
J2
SSTL_18 input
DCS
H2
Chip select inputs (active LOW). Disables
D1 to D25[1] outputs switching when both
inputs are HIGH.
D1 to D25
[2]
SSTL_18 input
Data input. Clocked in on the crossing of
the rising edge of CK and the falling edge
of CK.
DODT
[2]
SSTL_18 input
The outputs of this register bit will not be
suspended by the DCS and CSR control.
DCKE
[2]
SSTL_18 input
The outputs of this register bit will not be
suspended by the DCS and CSR control.
PAR_IN
G1
SSTL_18 input
Parity input. Arrives one clock cycle after
the corresponding data input.
Q1 to Q25,
Q2A to Q14A,
Q1B to Q14B
[2]
1.8 V CMOS
outputs
Data outputs that are suspended by the
DCS and CSR control[3].
PPO
A2
1.8 V CMOS
output
Partial parity out. Indicates odd parity of
inputs D1 to D25[1].
QCS, QCSA,
QCSB
[2]
1.8 V CMOS
output
Data output that will not be suspended by
the DCS and CSR control.
QODT, QODTA,
QODTB
[2]
1.8 V CMOS
output
Data output that will not be suspended by
the DCS and CSR control.
SSTUP32866_2
Product data sheet
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Rev. 02 — 14 September 2006
7 of 31
SSTUP32866
Philips Semiconductors
1.8 V DDR2-667/800 programmable registered buffer with parity
Table 3.
Pin description …continued
Symbol
Pin
Type
Description
QCKE, QCKEA,
QCKEB
[2]
1.8 V CMOS
output
Data output that will not be suspended by
the DCS and CSR control.
QERR
D2
open-drain
output
Output error bit (active LOW). Generated
one clock cycle after the corresponding
data output
DNU
[2]
-
Do not use. Inputs are in
standby-equivalent mode and outputs
are driven LOW.
[1]
Data inputs = D2, D3, D5, D6, D8 to D25 when C0 = 0 and C1 = 0.
Data inputs = D2, D3, D5, D6, D8 to D14 when C0 = 0 and C1 = 1.
Data inputs = D1 to D6, D8 to D10, D12, D13 when C0 = 1 and C1 = 1.
[2]
Depends on configuration. See Figure 4, Figure 5, and Figure 6 for ball number.
[3]
Data outputs = Q2, Q3, Q5, Q6, Q8 to Q25 when C0 = 0 and C1 = 0.
Data outputs = Q2, Q3, Q5, Q6, Q8 to Q14 when C0 = 0 and C1 = 1.
Data outputs = Q1 to Q6, Q8 to Q10, Q12, Q13 when C0 = 1 and C1 = 1.
7. Functional description
The SSTUP32866 is a 25-bit 1 : 1 or 14-bit 1 : 2 configurable registered buffer with parity,
designed for 1.7 V to 2.0 V VDD operation. Additionally, the SSTUP32866 can be
programmed to deliver either normal or high output drive, and either 600 MT/s or
800 MT/s speeds.
Two programming pins, SELAB and SELDR, allow the user to respectively select speed
and drive strength options by tying these pins either LOW or HIGH on the DIMM. The truth
table for these options is shown in Table 6.
All clock and data inputs are compatible with the JEDEC standard for SSTL_18. The
control and reset (RESET) inputs are LVCMOS. All data outputs are 1.8 V CMOS drivers
that have been optimized to drive the DDR2 DIMM load, and meet SSTL_18
specifications. The error (QERR) output is 1.8 V open-drain driver.
The SSTUP32866 operates from a differential clock (CK and CK). Data are registered at
the crossing of CK going HIGH, and CK going LOW.
The C0 input controls the pinout configuration for the 1 : 2 pinout from A configuration
(when LOW) to B configuration (when HIGH). The C1 input controls the pinout
configuration from 25-bit 1 : 1 (when LOW) to 14-bit 1 : 2 (when HIGH).
The SSTUP32866 accepts a parity bit from the memory controller on its parity bit
(PAR_IN) input, compares it with the data received on the DIMM-independent D-inputs
and indicates whether a parity error has occurred on its open-drain QERR pin
(active LOW). The convention is even parity, that is, valid parity is defined as an even
number of ones across the DIMM-independent data inputs combined with the parity input
bit.
When used as a single device, the C0 and C1 inputs are tied LOW. In this configuration,
parity is checked on the PAR_IN input which arrives one cycle after the input data to which
it applies. The Partial-Parity-Out (PPO) and QERR signals are produced three cycles after
the corresponding data inputs.
SSTUP32866_2
Product data sheet
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Rev. 02 — 14 September 2006
8 of 31
SSTUP32866
Philips Semiconductors
1.8 V DDR2-667/800 programmable registered buffer with parity
When used in pairs, the C0 input of the first register is tied LOW and the C0 input of the
second register is tied HIGH. The C1 input of both registers are tied HIGH. Parity, which
arrives one cycle after the data input to which it applies, is checked on the PAR_IN input of
the first device. The PPO and QERR signals are produced on the second device three
clock cycles after the corresponding data inputs. The PPO output of the first register is
cascaded to the PAR_IN of the second register. The QERR output of the first register is
left floating and the valid error information is latched on the QERR output of the second
register.
If an error occurs and the QERR output is driven LOW, it stays latched LOW for two clock
cycles or until RESET is driven LOW. The DIMM-dependent signals (DCKE, DCS, DODT,
and CSR) are not included in the parity check computation.
The device supports low-power standby operation. When RESET is LOW, the differential
input receivers are disabled, and undriven (floating) data, clock and reference voltage
(VREF) inputs are allowed. In addition, when RESET is LOW all registers are reset, and
all outputs are forced LOW. The LVCMOS RESET input must always be held at a valid
logic HIGH or LOW level.
The device also supports low-power active operation by monitoring both system chip
select (DCS and CSR) inputs and will gate the Qn and PPO outputs from changing states
when both DCS and CSR inputs are HIGH. If either DCS or CSR input is LOW, the Qn
and PPO outputs will function normally. The RESET input has priority over the DCS and
CSR control and when driven LOW will force the Qn and PPO outputs LOW, and the
QERR output HIGH. If the DCS control functionality is not desired, then the CSR input can
be hard-wired to ground, in which case, the setup time requirement for DCS would be the
same as for the other Dn data inputs. To control the low-power mode with DCS only, then
the CSR input should be pulled up to VDD through a pull-up resistor.
To ensure defined outputs from the register before a stable clock has been supplied,
RESET must be held in the LOW state during power-up.
In the DDR2 RDIMM application, RESET is specified to be completely asynchronous with
respect to CK and CK. Therefore, no timing relationship can be guaranteed between the
two. When entering reset, the register will be cleared and the Qn outputs will be driven
LOW quickly, relative to the time to disable the differential input receivers. However, when
coming out of reset, the register will become active quickly, relative to the time to enable
the differential input receivers. As long as the data inputs are LOW, and the clock is stable
during the time from the LOW-to-HIGH transition of RESET until the input receivers are
fully enabled, the design of the SSTUP32866 must ensure that the outputs will remain
LOW, thus ensuring no glitches on the output.
SSTUP32866_2
Product data sheet
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Rev. 02 — 14 September 2006
9 of 31
SSTUP32866
Philips Semiconductors
1.8 V DDR2-667/800 programmable registered buffer with parity
7.1 Function table
Table 4.
Function table (each flip-flop)
L = LOW voltage level; H = HIGH voltage level; X = don’t care; ↑ = LOW-to-HIGH transition; ↓ = HIGH-to-LOW transition.
Outputs[1]
Inputs
RESET
DCS
CSR
CK
CK
Dn, DODTn,
DCKEn
Qn
QCS
QODT,
QCKE
H
L
L
↑
↓
L
L
L
L
H
L
L
↑
↓
H
H
L
H
H
L
L
L or H
L or H
X
Q0
Q0
Q0
H
L
H
↑
↓
L
L
L
L
H
L
H
↑
↓
H
H
L
H
H
L
H
L or H
L or H
X
Q0
Q0
Q0
H
H
L
↑
↓
L
L
H
L
H
H
L
↑
↓
H
H
H
H
H
H
L
L or H
L or H
X
Q0
Q0
Q0
H
H
H
↑
↓
L
Q0
H
L
H
H
H
↑
↓
H
Q0
H
H
[1]
H
H
H
L or H
L or H
X
Q0
Q0
Q0
L
X or floating
X or floating
X or floating
X or floating
X or floating
L
L
L
Q0 is the previous state of the associated output.
Table 5.
Parity and standby function table
L = LOW voltage level; H = HIGH voltage level; X = don’t care; ↑ = LOW-to-HIGH transition; ↓ = HIGH-to-LOW transition.
Outputs[1]
Inputs
RESET
DCS
CSR
CK
CK
∑ of inputs = H
(D1 to D25)
PAR_IN[2]
PPO[3]
QERR[4]
H
L
X
↑
↓
even
L
L
H
H
L
X
↑
↓
odd
L
H
L
H
L
X
↑
↓
even
H
H
L
H
L
X
↑
↓
odd
H
L
H
H
H
L
↑
↓
even
L
L
H
H
H
L
↑
↓
odd
L
H
L
H
H
L
↑
↓
even
H
H
L
H
H
L
↑
↓
odd
H
L
H
H
H
H
↑
↓
X
X
PPO0
QERR0
H
X
X
L or H
L or H
X
X
PPO0
QERR0
X or floating
X or floating
L
H
L
X or floating X or floating X or floating X or floating
[1]
PPO0 is the previous state of output PPO; QERR0 is the previous state of output QERR.
[2]
Data inputs = D2, D3, D5, D6, D8 to D25 when C0 = 0 and C1 = 0.
Data inputs = D2, D3, D5, D6, D8 to D14 when C0 = 0 and C1 = 1.
Data inputs = D1 to D6, D8 to D10, D12, D13 when C0 = 1 and C1 = 1.
[3]
PAR_IN arrives one clock cycle (C0 = 0), or two clock cycles (C0 = 1), after the data to which it applies.
[4]
This condition assumes QERR is HIGH at the crossing of CK going HIGH and CK going LOW. If QERR is LOW, it stays latched LOW for
two clock cycles or until RESET is driven LOW.
SSTUP32866_2
Product data sheet
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Rev. 02 — 14 September 2006
10 of 31
SSTUP32866
Philips Semiconductors
1.8 V DDR2-667/800 programmable registered buffer with parity
Table 6.
Speed and drive programmability
Inputs
Mode
SELDR
SELAB
L
L
DDR2-800; high output drive
L
H
DDR2-667; high output drive
H
L
DDR2-800; normal output drive
H
H
DDR2-667; normal output drive
8. Limiting values
Table 7.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol
Parameter
VDD
VI
Conditions
Min
Max
Unit
supply voltage
−0.5
+2.5
V
input voltage
receiver
−0.5[1]
+2.5[2]
VDD +
V
VO
output voltage
driver
−0.5[1]
IIK
input clamping current
VI < 0 V or VI > VDD
-
−50
mA
IOK
output clamping current
VO < 0 V or VO > VDD
-
±50
mA
IO
output current
continuous; 0 V < VO < VDD
-
±50
mA
ICCC
continuous current through each
VDD or GND pin
-
±100
mA
Tstg
storage temperature
−65
+150
°C
Vesd
electrostatic discharge voltage
Human Body Model (HBM); 1.5 kΩ;
100 pF
2
-
kV
Machine Model (MM); 0 Ω; 200 pF
200
-
V
0.5[2]
[1]
The input and output negative voltage ratings may be exceeded if the input and output clamping current ratings are observed.
[2]
This value is limited to 2.5 V maximum.
SSTUP32866_2
Product data sheet
V
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Rev. 02 — 14 September 2006
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SSTUP32866
Philips Semiconductors
1.8 V DDR2-667/800 programmable registered buffer with parity
9. Recommended operating conditions
Table 8.
Recommended operating conditions
Symbol
Parameter
VDD
Conditions
Min
Typ
Max
Unit
supply voltage
1.7
-
2.0
V
Vref
reference voltage
0.49 × VDD
0.50 × VDD
0.51 × VDD
V
VT
termination voltage
Vref − 0.040
Vref
Vref + 0.040
V
VI
input voltage
0
-
VDD
V
VIH(AC)
AC HIGH-level input voltage
data (Dn), CSR, and
PAR_IN inputs
Vref + 0.250
-
-
V
VIL(AC)
AC LOW-level input voltage
data (Dn), CSR, and
PAR_IN inputs
-
-
Vref − 0.250
V
VIH(DC)
DC HIGH-level input voltage
data (Dn), CSR, and
PAR_IN inputs
Vref + 0.125
-
-
V
VIL(DC)
DC LOW-level input voltage
data (Dn), CSR, and
PAR_IN inputs
-
-
Vref − 0.125
V
VIH
HIGH-level input voltage
RESET, Cn, SELAB,
SELDR
[1]
0.65 × VDD
-
-
V
VIL
LOW-level input voltage
RESET, Cn, SELAB,
SELDR
[1]
-
-
0.35 × VDD
V
VICR
common mode input voltage
range
CK, CK
[2]
0.675
-
1.125
V
VID
differential input voltage
CK, CK
[2]
600
-
-
mV
IOH
HIGH-level output current
SELDR either HIGH or
LOW
-
-
−8
mA
IOL
LOW-level output current
SELDR either HIGH or
LOW
-
-
8
mA
Tamb
ambient temperature
operating in free air
SSTUP32866EC/G
0
-
70
°C
SSTUP32866EC/S
0
-
85
°C
[1]
The RESET and Cn inputs of the device must be held at valid levels (not floating) to ensure proper device operation.
[2]
The differential inputs must not be floating, unless RESET is LOW.
SSTUP32866_2
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SSTUP32866
Philips Semiconductors
1.8 V DDR2-667/800 programmable registered buffer with parity
10. Characteristics
Table 9.
Characteristics
At recommended operating conditions (see Table 8); unless otherwise specified.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
VOH
HIGH-level output voltage
IOH = −6 mA; VDD = 1.7 V
1.2
-
-
V
VOL
LOW-level output voltage
IOL = 6 mA; VDD = 1.7 V
-
-
0.5
V
II
input current
all inputs; VI = VDD or GND;
VDD = 2.0 V
-
-
±5
µA
IDD
supply current
static Standby mode; RESET = GND;
IO = 0 mA; VDD = 2.0 V
-
-
100
µA
static Operating mode;
RESET = VDD; IO = 0 mA;
VDD = 2.0 V; VI = VIH(AC) or VIL(AC)
-
-
40
mA
clock only; RESET = VDD;
VI = VIH(AC) or VIL(AC); CK and CK
switching at 50 % duty cycle;
IO = 0 mA; VDD = 1.8 V
-
16
-
µA
per each data input, 1 : 1 mode;
RESET = VDD; VI = VIH(AC) or VIL(AC);
CK and CK switching at 50 % duty
cycle; one data input switching at half
clock frequency, 50 % duty cycle;
IO = 0 mA; VDD = 1.8 V
-
11
-
µA
per each data input, 1 : 2 mode;
RESET = VDD; VI = VIH(AC) or VIL(AC);
CK and CK switching at 50 % duty
cycle; one data input switching at half
clock frequency, 50 % duty cycle;
IO = 0 mA; VDD = 1.8 V
-
19
-
µA
data and CSR inputs;
VI = Vref ± 250 mV; VDD = 1.8 V
2.5
-
3.5
pF
CK and CK inputs; VICR = 0.9 V;
Vi(p-p) = 600 mV; VDD = 1.8 V
2
-
3
pF
RESET input; VI = VDD or GND;
VDD = 1.8 V
3
-
4
pF
-
15
-
Ω
-
53
-
Ω
-
7
-
Ω
-
53
-
Ω
IDDD
dynamic operating current per MHz
input capacitance
Ci
output impedance
Zo
normal drive; instantaneous
[1]
normal drive; steady-state
high drive; instantaneous
high drive; steady-state
[1]
[1]
Instantaneous is defined as within < 2 ns following the output data transition edge.
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SSTUP32866
Philips Semiconductors
1.8 V DDR2-667/800 programmable registered buffer with parity
Table 10. Timing requirements
At recommended operating conditions (see Table 8), unless otherwise specified. See Section 11.1.
Symbol
Parameter
fclock
clock frequency
tW
pulse width
Min
Typ
Max
Unit
-
-
450
MHz
1
-
-
ns
differential inputs active time
[1][2]
-
-
10
ns
tINACT
differential inputs inactive time
[1][3]
-
-
15
ns
tsu
setup time
DCS before CK↑, CK↓, CSR HIGH; CSR
before CK↑, CK↓, DCS HIGH
0.6
-
-
ns
DCS before CK↑, CK↓, CSR LOW
0.5
-
-
ns
DODT, DCKE and data (Dn) before CK↑,
CK↓
0.5
-
-
ns
PAR_IN before CK↑, CK↓
0.5
-
-
ns
DCS, DODT, DCKE and data (Dn) after
CK↑, CK↓
0.4
-
-
ns
PAR_IN after CK↑, CK↓
0.4
-
-
ns
tACT
hold time
th
Conditions
CK, CK HIGH or LOW
[1]
This parameter is not necessarily production tested.
[2]
VREF must be held at a valid input voltage level and data inputs must be held LOW for a minimum time of tACT(max) after RESET is taken
HIGH.
[3]
VREF, data and clock inputs must be held at valid levels (not floating) a minimum time of tINACT(max) after RESET is taken LOW.
Table 11. Switching characteristics (667 mode, SELAB = HIGH)
At recommended operating conditions (see Table 8), unless otherwise specified. See Section 11.1.
Symbol
Parameter
Min
Typ
Max
Unit
fmax
maximum input clock frequency
tPDM
peak propagation delay
single bit switching;
from CK↑ and CK↓ to Qn
450
-
-
MHz
1.2
-
1.8
ns
tPD
propagation delay
from CK↑ and CK↓ to PPO
0.5
-
1.8
ns
tLH
tHL
LOW-to-HIGH delay
from CK↑ and CK↓ to QERR
1.2
-
3
ns
HIGH-to-LOW delay
from CK↑ and CK↓ to QERR
1
-
2.4
ns
-
-
2.0
ns
tPDMSS
simultaneous switching peak
propagation delay
tPHL
HIGH-to-LOW propagation delay
Conditions
from CK↑ and CK↓ to Qn
LOW-to-HIGH propagation delay
tPLH
[1]
Includes 350 ps of test load transmission line delay.
[2]
This parameter is not necessarily production tested.
[1][2]
from RESET↓ to Qn↓
-
-
3
ns
from RESET↓ to PPO↓
-
-
3
ns
from RESET↓ to QERR↑
-
-
3
ns
SSTUP32866_2
Product data sheet
[1]
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SSTUP32866
Philips Semiconductors
1.8 V DDR2-667/800 programmable registered buffer with parity
Table 12. Switching characteristics (800 mode, SELAB = LOW)
At recommended operating conditions (see Table 8), unless otherwise specified. See Section 11.1.
Symbol
Parameter
Min
Typ
Max
Unit
fmax
maximum input clock frequency
tPDM
peak propagation delay
single bit switching;
from CK↑ and CK↓ to Qn
450
-
-
MHz
1.1
-
1.5
ns
tPD
propagation delay
from CK↑ and CK↓ to PPO
0.5
-
1.7
ns
tLH
tHL
LOW-to-HIGH delay
from CK↑ and CK↓ to QERR
1.2
-
3
ns
HIGH-to-LOW delay
from CK↑ and CK↓ to QERR
1
-
2.4
ns
-
-
1.6
ns
tPDMSS
simultaneous switching peak
propagation delay
tPHL
HIGH-to-LOW propagation delay
Conditions
from CK↑ and CK↓ to Qn
LOW-to-HIGH propagation delay
tPLH
[1]
Includes 350 ps of test load transmission line delay.
[2]
This parameter is not necessarily production tested.
[1]
[1][2]
from RESET↓ to Qn↓
-
-
3
ns
from RESET↓ to PPO↓
-
-
3
ns
from RESET↓ to QERR↑
-
-
3
ns
Table 13. Data output edge rates
At recommended operating conditions (see Table 8), unless otherwise specified. See Section 11.2.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
dV/dt_r
rising edge slew rate
from 20 % to 80 %
1
-
4
V/ns
dV/dt_f
falling edge slew rate
from 80 % to 20 %
1
-
4
V/ns
dV/dt_∆
absolute difference between dV/dt_r from 20 % or 80 %
and dV/dt_f
to 80 % or 20 %
-
-
1
V/ns
SSTUP32866_2
Product data sheet
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SSTUP32866
Philips Semiconductors
1.8 V DDR2-667/800 programmable registered buffer with parity
10.1 Timing diagrams
RESET
DCS
CSR
m
m+1
m+2
m+3
m+4
CK
CK
tsu
th
D1
to
D25
tPD
CK to Q
Q1
to
Q25
tsu
th
PAR_IN
tPD
CK to PPO
PPO
tPD
tPD
CK to QERR
CK to QERR
QERR
002aaa655
Fig 7. Timing diagram for SSTUP32866 used as a single device; C0 = 0, C1 = 0
SSTUP32866_2
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SSTUP32866
Philips Semiconductors
1.8 V DDR2-667/800 programmable registered buffer with parity
RESET
DCS
CSR
m
m+1
m+2
m+3
m+4
CK
CK
tsu
th
D1
to
D14
tPD
CK to Q
Q1
to
Q14
tsu
th
PAR_IN
tPD
CK to PPO
PPO
tPD
tPD
CK to QERR
CK to QERR
QERR
(not used)
002aaa656
Fig 8. Timing diagram for the first SSTUP32866 (1 : 2 Register A configuration) device used in pair; C0 = 0,
C1 = 1
SSTUP32866_2
Product data sheet
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SSTUP32866
Philips Semiconductors
1.8 V DDR2-667/800 programmable registered buffer with parity
RESET
DCS
CSR
m
m+1
m+2
m+3
m+4
CK
CK
tsu
th
D1
to
D14
tPD
CK to Q
Q1
to
Q14
tsu
th
PAR_IN(1)
tPD
CK to PPO
PPO
(not used)
tPD
tPD
CK to QERR
CK to QERR
QERR
002aaa657
(1) PAR_IN is driven from PPO of the first SSTUP32866 device.
Fig 9. Timing diagram for the second SSTUP32866 (1 : 2 Register B configuration) device used in pair;
C0 = 1, C1 = 1
SSTUP32866_2
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SSTUP32866
Philips Semiconductors
1.8 V DDR2-667/800 programmable registered buffer with parity
11. Test information
11.1 Parameter measurement information for data output load circuit
VDD = 1.8 V ± 0.1 V.
All input pulses are supplied by generators having the following characteristics:
PRR ≤ 10 MHz; Z0 = 50 Ω; input slew rate = 1 V/ns ± 20 %, unless otherwise specified.
The outputs are measured one at a time with one transition per measurement.
VDD
DUT
CK
CK
CK inputs
RL = 1000 Ω
delay = 350 ps
Zo = 50 Ω
50 Ω
OUT
CL = 30 pF(1)
RL = 1000 Ω
test point
RL = 100 Ω
test point
002aaa371
(1) CL includes probe and jig capacitance.
Fig 10. Load circuit, data output measurements
LVCMOS
VDD
0.5VDD
0.5VDD
RESET
0V
tINACT
IDD(1)
tACT
90 %
10 %
002aaa372
(1) IDD tested with clock and data inputs held at VDD or GND, and IO = 0 mA.
Fig 11. Voltage and current waveforms; inputs active and inactive times
tW
VIH
input
VICR
VICR
VID
VIL
002aaa373
VID = 600 mV.
VIH = Vref + 250 mV (AC voltage levels) for differential inputs. VIH = VDD for LVCMOS inputs.
VIL = Vref − 250 mV (AC voltage levels) for differential inputs. VIL = GND for LVCMOS inputs.
Fig 12. Voltage waveforms; pulse duration
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SSTUP32866
Philips Semiconductors
1.8 V DDR2-667/800 programmable registered buffer with parity
CK
VICR
VID
CK
tsu
th
VIH
input
Vref
Vref
VIL
002aaa374
VID = 600 mV.
Vref = 0.5VDD.
VIH = Vref + 250 mV (AC voltage levels) for differential inputs. VIH = VDD for LVCMOS inputs.
VIL = Vref − 250 mV (AC voltage levels) for differential inputs. VIL = GND for LVCMOS inputs.
Fig 13. Voltage waveforms; setup and hold times
CK
VICR
VICR
tPLH
tPHL
Vi(p-p)
CK
VOH
VT
output
VOL
002aaa375
tPLH and tPHL are the same as tPD.
Fig 14. Voltage waveforms; propagation delay times (clock to output)
LVCMOS
VIH
RESET
0.5VDD
VIL
tPHL
VOH
output
VT
VOL
002aaa376
tPLH and tPHL are the same as tPD.
VIH = Vref + 250 mV (AC voltage levels) for differential inputs. VIH = VDD for LVCMOS inputs.
VIL = Vref − 250 mV (AC voltage levels) for differential inputs. VIL = GND for LVCMOS inputs.
Fig 15. Voltage waveforms; propagation delay times (reset to output)
SSTUP32866_2
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SSTUP32866
Philips Semiconductors
1.8 V DDR2-667/800 programmable registered buffer with parity
11.2 Data output slew rate measurement information
VDD = 1.8 V ± 0.1 V.
All input pulses are supplied by generators having the following characteristics:
PRR ≤ 10 MHz; Z0 = 50 Ω; input slew rate = 1 V/ns ± 20 %, unless otherwise specified.
VDD
DUT
RL = 50 Ω
OUT
test point
CL = 10
pF(1)
002aaa377
(1) CL includes probe and jig capacitance.
Fig 16. Load circuit, HIGH-to-LOW slew measurement
output
VOH
80 %
dv_f
20 %
dt_f
002aaa378
VOL
Fig 17. Voltage waveforms, HIGH-to-LOW slew rate measurement
DUT
OUT
test point
CL = 10 pF(1)
RL = 50 Ω
002aaa379
(1) CL includes probe and jig capacitance.
Fig 18. Load circuit, LOW-to-HIGH slew measurement
dt_r
VOH
80 %
dv_r
20 %
output
002aaa380
VOL
Fig 19. Voltage waveforms, LOW-to-HIGH slew rate measurement
SSTUP32866_2
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SSTUP32866
Philips Semiconductors
1.8 V DDR2-667/800 programmable registered buffer with parity
11.3 Error output load circuit and voltage measurement information
VDD = 1.8 V ± 0.1 V.
All input pulses are supplied by generators having the following characteristics:
PRR ≤ 10 MHz; Z0 = 50 Ω; input slew rate = 1 V/ns ± 20 %, unless otherwise specified.
VDD
DUT
RL = 1 kΩ
OUT
test point
CL = 10 pF(1)
002aaa500
(1) CL includes probe and jig capacitance.
Fig 20. Load circuit, error output measurements
LVCMOS
RESET
VDD
0.5VDD
0V
tPLH
VOH
0.15 V
output
waveform 2
0V
002aaa501
Fig 21. Voltage waveforms, open-drain output LOW-to-HIGH transition time with respect to
RESET input
timing
inputs
VICR
Vi(p-p)
VICR
tHL
VDD
output
waveform 1
0.5VDD
002aaa502
VOL
Fig 22. Voltage waveforms, open-drain output HIGH-to-LOW transition time with respect
to clock inputs
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SSTUP32866
Philips Semiconductors
1.8 V DDR2-667/800 programmable registered buffer with parity
timing
inputs
VICR
Vi(p-p)
VICR
tLH
VOH
output
waveform 2
0.15 V
002aaa503
0V
Fig 23. Voltage waveforms, open-drain output LOW-to-HIGH transition time with respect to
clock inputs
11.4 Partial parity out load circuit and voltage measurement information
VDD = 1.8 V ± 0.1 V.
All input pulses are supplied by generators having the following characteristics:
PRR ≤ 10 MHz; Z0 = 50 Ω; input slew rate = 1 V/ns ± 20 %, unless otherwise specified.
DUT
OUT
test point
CL = 5
pF(1)
RL = 1 kΩ
002aaa654
(1) CL includes probe and jig capacitance.
Fig 24. Partial parity out load circuit
CK
VICR
VICR
tPLH
tPHL
Vi(p-p)
CK
VOH
output
VT
VOL
002aaa375
VT = 0.5VDD.
tPLH and tPHL are the same as tPD.
Vi(p-p) = 600 mV.
Fig 25. Partial parity out voltage waveforms; propagation delay times with respect to clock
inputs
SSTUP32866_2
Product data sheet
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SSTUP32866
Philips Semiconductors
1.8 V DDR2-667/800 programmable registered buffer with parity
LVCMOS
VIH
RESET
0.5VDD
VIL
tPHL
VOH
output
VT
VOL
002aaa376
VT = 0.5VDD.
tPLH and tPHL are the same as tPD.
VIH = Vref + 250 mV (AC voltage levels) for differential inputs. VIH = VDD for LVCMOS inputs.
VIL = Vref − 250 mV (AC voltage levels) for differential inputs. VIL = GND for LVCMOS inputs.
Fig 26. Partial parity out voltage waveforms; propagation delay times with respect to
RESET input
SSTUP32866_2
Product data sheet
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SSTUP32866
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1.8 V DDR2-667/800 programmable registered buffer with parity
12. Package outline
LFBGA96: plastic low profile fine-pitch ball grid array package; 96 balls; body 13.5 x 5.5 x 1.05 mm SOT536-1
A
B
D
ball A1
index area
A
A2
E
A1
detail X
e1
C
1/2 e
∅v M C A B
e
T
R
P
N
M
L
K
J
H
G
F
E
D
C
B
A
ball A1
index area
y1 C
y
∅w M C
b
e
e2
1/2 e
1 2 3 4 5 6
X
0
5
10 mm
scale
DIMENSIONS (mm are the original dimensions)
UNIT
A
max.
A1
A2
b
D
E
e
e1
e2
v
w
y
y1
mm
1.5
0.41
0.31
1.2
0.9
0.51
0.41
5.6
5.4
13.6
13.4
0.8
4
12
0.15
0.1
0.1
0.2
OUTLINE
VERSION
REFERENCES
IEC
JEDEC
JEITA
EUROPEAN
PROJECTION
ISSUE DATE
00-03-04
03-02-05
SOT536-1
Fig 27. Package outline SOT536-1 (LFBGA96)
SSTUP32866_2
Product data sheet
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Philips Semiconductors
1.8 V DDR2-667/800 programmable registered buffer with parity
13. Soldering
13.1 Introduction to soldering surface mount packages
There is no soldering method that is ideal for all surface mount IC packages. Wave
soldering can still be used for certain surface mount ICs, but it is not suitable for fine pitch
SMDs. In these situations reflow soldering is recommended.
13.2 Reflow soldering
Reflow soldering requires solder paste (a suspension of fine solder particles, flux and
binding agent) to be applied to the printed-circuit board by screen printing, stencilling or
pressure-syringe dispensing before package placement. Driven by legislation and
environmental forces the worldwide use of lead-free solder pastes is increasing.
Several methods exist for reflowing; for example, convection or convection/infrared
heating in a conveyor type oven. Throughput times (preheating, soldering and cooling)
vary between 100 seconds and 200 seconds depending on heating method.
Typical reflow temperatures range from 215 °C to 260 °C depending on solder paste
material. The peak top-surface temperature of the packages should be kept below:
Table 14.
SnPb eutectic process - package peak reflow temperatures (from J-STD-020C
July 2004)
Package thickness
Volume mm3 < 350
Volume mm3 ≥ 350
< 2.5 mm
240 °C + 0/−5 °C
225 °C + 0/−5 °C
≥ 2.5 mm
225 °C + 0/−5 °C
225 °C + 0/−5 °C
Table 15.
Pb-free process - package peak reflow temperatures (from J-STD-020C July
2004)
Package thickness
Volume mm3 < 350
Volume mm3 350 to
2000
Volume mm3 > 2000
< 1.6 mm
260 °C + 0 °C
260 °C + 0 °C
260 °C + 0 °C
1.6 mm to 2.5 mm
260 °C + 0 °C
250 °C + 0 °C
245 °C + 0 °C
≥ 2.5 mm
250 °C + 0 °C
245 °C + 0 °C
245 °C + 0 °C
Moisture sensitivity precautions, as indicated on packing, must be respected at all times.
13.3 Wave soldering
Conventional single wave soldering is not recommended for surface mount devices
(SMDs) or printed-circuit boards with a high component density, as solder bridging and
non-wetting can present major problems.
To overcome these problems the double-wave soldering method was specifically
developed.
If wave soldering is used the following conditions must be observed for optimal results:
• Use a double-wave soldering method comprising a turbulent wave with high upward
pressure followed by a smooth laminar wave.
• For packages with leads on two sides and a pitch (e):
SSTUP32866_2
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Philips Semiconductors
1.8 V DDR2-667/800 programmable registered buffer with parity
– larger than or equal to 1.27 mm, the footprint longitudinal axis is preferred to be
parallel to the transport direction of the printed-circuit board;
– smaller than 1.27 mm, the footprint longitudinal axis must be parallel to the
transport direction of the printed-circuit board.
The footprint must incorporate solder thieves at the downstream end.
• For packages with leads on four sides, the footprint must be placed at a 45° angle to
the transport direction of the printed-circuit board. The footprint must incorporate
solder thieves downstream and at the side corners.
During placement and before soldering, the package must be fixed with a droplet of
adhesive. The adhesive can be applied by screen printing, pin transfer or syringe
dispensing. The package can be soldered after the adhesive is cured.
Typical dwell time of the leads in the wave ranges from 3 seconds to 4 seconds at 250 °C
or 265 °C, depending on solder material applied, SnPb or Pb-free respectively.
A mildly-activated flux will eliminate the need for removal of corrosive residues in most
applications.
13.4 Manual soldering
Fix the component by first soldering two diagonally-opposite end leads. Use a low voltage
(24 V or less) soldering iron applied to the flat part of the lead. Contact time must be
limited to 10 seconds at up to 300 °C.
When using a dedicated tool, all other leads can be soldered in one operation within
2 seconds to 5 seconds between 270 °C and 320 °C.
13.5 Package related soldering information
Table 16.
Suitability of surface mount IC packages for wave and reflow soldering methods
Package[1]
Soldering method
Wave
Reflow[2]
BGA, HTSSON..T[3], LBGA, LFBGA, SQFP,
SSOP..T[3], TFBGA, VFBGA, XSON
not suitable
suitable
DHVQFN, HBCC, HBGA, HLQFP, HSO, HSOP,
HSQFP, HSSON, HTQFP, HTSSOP, HVQFN,
HVSON, SMS
not suitable[4]
suitable
PLCC[5], SO, SOJ
suitable
suitable
not
recommended[5][6]
suitable
SSOP, TSSOP, VSO, VSSOP
not
recommended[7]
suitable
CWQCCN..L[8],
not suitable
LQFP, QFP, TQFP
PMFP[9],
WQCCN..L[8]
[1]
For more detailed information on the BGA packages refer to the (LF)BGA Application Note (AN01026);
order a copy from your Philips Semiconductors sales office.
[2]
All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the
maximum temperature (with respect to time) and body size of the package, there is a risk that internal or
external package cracks may occur due to vaporization of the moisture in them (the so called popcorn
effect). For details, refer to the Drypack information in the Data Handbook IC26; Integrated Circuit
Packages; Section: Packing Methods.
SSTUP32866_2
Product data sheet
not suitable
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Rev. 02 — 14 September 2006
27 of 31
SSTUP32866
Philips Semiconductors
1.8 V DDR2-667/800 programmable registered buffer with parity
[3]
These transparent plastic packages are extremely sensitive to reflow soldering conditions and must on no
account be processed through more than one soldering cycle or subjected to infrared reflow soldering with
peak temperature exceeding 217 °C ± 10 °C measured in the atmosphere of the reflow oven. The package
body peak temperature must be kept as low as possible.
[4]
These packages are not suitable for wave soldering. On versions with the heatsink on the bottom side, the
solder cannot penetrate between the printed-circuit board and the heatsink. On versions with the heatsink
on the top side, the solder might be deposited on the heatsink surface.
[5]
If wave soldering is considered, then the package must be placed at a 45° angle to the solder wave
direction. The package footprint must incorporate solder thieves downstream and at the side corners.
[6]
Wave soldering is suitable for LQFP, QFP and TQFP packages with a pitch (e) larger than 0.8 mm; it is
definitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm.
[7]
Wave soldering is suitable for SSOP, TSSOP, VSO and VSSOP packages with a pitch (e) equal to or larger
than 0.65 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm.
[8]
Image sensor packages in principle should not be soldered. They are mounted in sockets or delivered
pre-mounted on flex foil. However, the image sensor package can be mounted by the client on a flex foil by
using a hot bar soldering process. The appropriate soldering profile can be provided on request.
[9]
Hot bar soldering or manual soldering is suitable for PMFP packages.
14. Abbreviations
Table 17.
Abbreviations
Acronym
Description
CMOS
Complementary Metal Oxide Semiconductor
DDR
Double Data Rate
DIMM
Dual In-line Memory Module
LVCMOS
Low Voltage Complementary Metal Oxide Semiconductor
PPO
Partial Parity Out
PRR
Pulse Repetition Rate
RDIMM
Registered Dual In-line Memory Module
SSTL
Stub Series Terminated Logic
SSTUP32866_2
Product data sheet
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Rev. 02 — 14 September 2006
28 of 31
SSTUP32866
Philips Semiconductors
1.8 V DDR2-667/800 programmable registered buffer with parity
15. Revision history
Table 18.
Revision history
Document ID
Release date
Data sheet status
Change notice
Supersedes
SSTUP32866_2
20060914
Product data sheet
-
SSTUP32866_1
Modifications:
•
•
•
•
Table 1 “Ordering information”: added Type number SSTUP32866EC/S
•
Table 8 “Recommended operating conditions”, Symbol Tamb: added separate specifications for
SSTUP32866EC/G and SSTUP32866EC/S
•
Table 10 “Timing requirements”, description below table title: changed “See Figure 2.” to
“See Section 11.1.”
•
Table 11 “Switching characteristics (667 mode, SELAB = HIGH)” and Table 12 “Switching
characteristics (800 mode, SELAB = LOW)”:
added Section 4.1 “Ordering options”
Figure 3 “Pin configuration for LFBGA96” modified (added Type number SSTUP32866EC/S)
Table 5 “Parity and standby function table”: added reference to Table note 4 at column heading
“QERR”
– changed parameter description of tPDM from “propagation delay, single bit switching” to “peak
propagation delay” (moved “single bit switching” to Conditions column)
– changed parameter description of tPDMSS from “propagation delay, simultaneous switching” to
“simultaneous switching peak propagation delay”
•
SSTUP32866_1
Figure 26 “Partial parity out voltage waveforms; propagation delay times with respect to RESET
input”, 4th note: changed “VIL = VDD” to “VIL = GND”
20060406
Product data sheet
-
SSTUP32866_2
Product data sheet
-
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Rev. 02 — 14 September 2006
29 of 31
SSTUP32866
Philips Semiconductors
1.8 V DDR2-667/800 programmable registered buffer with parity
16. Legal information
16.1 Data sheet status
Document status[1][2]
Product status[3]
Definition
Objective [short] data sheet
Development
This document contains data from the objective specification for product development.
Preliminary [short] data sheet
Qualification
This document contains data from the preliminary specification.
Product [short] data sheet
Production
This document contains the product specification.
[1]
Please consult the most recently issued document before initiating or completing a design.
[2]
The term ‘short data sheet’ is explained in section “Definitions”.
[3]
The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.semiconductors.philips.com.
16.2 Definitions
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. Philips Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liability for the consequences of
use of such information.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is intended
for quick reference only and should not be relied upon to contain detailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local Philips Semiconductors
sales office. In case of any inconsistency or conflict with the short data sheet,
the full data sheet shall prevail.
16.3 Disclaimers
General — Information in this document is believed to be accurate and
reliable. However, Philips Semiconductors does not give any representations
or warranties, expressed or implied, as to the accuracy or completeness of
such information and shall have no liability for the consequences of use of
such information.
Right to make changes — Philips Semiconductors reserves the right to
make changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
Suitability for use — Philips Semiconductors products are not designed,
authorized or warranted to be suitable for use in medical, military, aircraft,
space or life support equipment, nor in applications where failure or
malfunction of a Philips Semiconductors product can reasonably be expected
to result in personal injury, death or severe property or environmental
damage. Philips Semiconductors accepts no liability for inclusion and/or use
of Philips Semiconductors products in such equipment or applications and
therefore such inclusion and/or use is at the customer’s own risk.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. Philips Semiconductors makes no
representation or warranty that such applications will be suitable for the
specified use without further testing or modification.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) may cause permanent
damage to the device. Limiting values are stress ratings only and operation of
the device at these or any other conditions above those given in the
Characteristics sections of this document is not implied. Exposure to limiting
values for extended periods may affect device reliability.
Terms and conditions of sale — Philips Semiconductors products are sold
subject to the general terms and conditions of commercial sale, as published
at http://www.semiconductors.philips.com/profile/terms, including those
pertaining to warranty, intellectual property rights infringement and limitation
of liability, unless explicitly otherwise agreed to in writing by Philips
Semiconductors. In case of any inconsistency or conflict between information
in this document and such terms and conditions, the latter will prevail.
No offer to sell or license — Nothing in this document may be interpreted
or construed as an offer to sell products that is open for acceptance or the
grant, conveyance or implication of any license under any copyrights, patents
or other industrial or intellectual property rights.
16.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks
are the property of their respective owners.
17. Contact information
For additional information, please visit: http://www.semiconductors.philips.com
For sales office addresses, send an email to: [email protected]
SSTUP32866_2
Product data sheet
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Rev. 02 — 14 September 2006
30 of 31
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Philips Semiconductors
1.8 V DDR2-667/800 programmable registered buffer with parity
18. Contents
1
2
3
4
4.1
5
6
6.1
6.2
7
7.1
8
9
10
10.1
11
11.1
11.2
11.3
11.4
12
13
13.1
13.2
13.3
13.4
13.5
14
15
16
16.1
16.2
16.3
16.4
17
18
General description . . . . . . . . . . . . . . . . . . . . . . 1
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Ordering information . . . . . . . . . . . . . . . . . . . . . 2
Ordering options . . . . . . . . . . . . . . . . . . . . . . . . 2
Functional diagram . . . . . . . . . . . . . . . . . . . . . . 3
Pinning information . . . . . . . . . . . . . . . . . . . . . . 5
Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 7
Functional description . . . . . . . . . . . . . . . . . . . 8
Function table . . . . . . . . . . . . . . . . . . . . . . . . . 10
Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . 11
Recommended operating conditions. . . . . . . 12
Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 13
Timing diagrams . . . . . . . . . . . . . . . . . . . . . . . 16
Test information . . . . . . . . . . . . . . . . . . . . . . . . 19
Parameter measurement information for
data output load circuit . . . . . . . . . . . . . . . . . . 19
Data output slew rate measurement
information . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Error output load circuit and voltage
measurement information . . . . . . . . . . . . . . . . 22
Partial parity out load circuit and voltage
measurement information . . . . . . . . . . . . . . . . 23
Package outline . . . . . . . . . . . . . . . . . . . . . . . . 25
Soldering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Introduction to soldering surface mount
packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Reflow soldering . . . . . . . . . . . . . . . . . . . . . . . 26
Wave soldering . . . . . . . . . . . . . . . . . . . . . . . . 26
Manual soldering . . . . . . . . . . . . . . . . . . . . . . 27
Package related soldering information . . . . . . 27
Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Revision history . . . . . . . . . . . . . . . . . . . . . . . . 29
Legal information. . . . . . . . . . . . . . . . . . . . . . . 30
Data sheet status . . . . . . . . . . . . . . . . . . . . . . 30
Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Contact information. . . . . . . . . . . . . . . . . . . . . 30
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
© Koninklijke Philips Electronics N.V. 2006.
All rights reserved.
For more information, please visit: http://www.semiconductors.philips.com.
For sales office addresses, email to: [email protected]
Date of release: 14 September 2006
Document identifier: SSTUP32866_2