INTEGRATED CIRCUITS
DATA SHEET
P83CL781; P83CL782
Low voltage 8-bit microcontrollers
with UART and I2C-bus
Product specification
Supersedes data of 1995 Jul 13
File under Integrated Circuits, IC20
1997 Mar 14
Philips Semiconductors
Product specification
Low voltage 8-bit microcontrollers with
UART and I2C-bus
P83CL781; P83CL782
CONTENTS
14
STANDARD SERIAL INTERFACE SIO0: UART
1
FEATURES
14.1
14.2
2
GENERAL DESCRIPTION
3
APPLICATIONS
14.3
Multiprocessor communications
Serial Port Control and Status Register
(S0CON)
Baud rates
4
ORDERING INFORMATION
15
INTERRUPT SYSTEM
5
BLOCK DIAGRAM
6
FUNCTIONAL DIAGRAM
7
PINNING INFORMATION
15.1
15.2
15.3
External interrupts INT2 to INT9
Interrupt priority
Interrupt registers
7.1
7.2
Pinning
Pin description
16
OSCILLATOR CIRCUITRY
17
RESET
8
FUNCTIONAL DESCRIPTION OVERVIEW
8.1
8.2
General
CPU timing
17.1
17.2
External reset using the RST pin
Power-on reset
18
9
MEMORY ORGANIZATION
SPECIAL FUNCTION REGISTERS
OVERVIEW
9.1
9.2
9.3
9.4
Program memory
Data memory
Special Function Registers
Addressing
19
INSTRUCTION SET
20
LIMITING VALUES
21
DC CHARACTERISTICS
22
AC CHARACTERISTICS
10
I/O FACILITIES
10.1
10.2
10.3
10.4
Ports
Port options
Port 0 options
SET/RESET options
22.1
22.2
Program memory
External Data Memory
23
PACKAGE OUTLINES
24
SOLDERING
11
TIMER/EVENT COUNTERS
11.1
11.2
11.3
Timer 0 and Timer 1
Timer T2
Timer/Counter 2 Control Register (T2CON)
24.1
24.2
24.3
Introduction
DIP
QFP
25
DEFINITIONS
12
REDUCED POWER MODES
26
LIFE SUPPORT APPLICATIONS
12.1
12.2
12.3
12.4
12.5
Idle mode
Power-down mode
Wake-up from Power-down mode
Status of external pins
Power Control Register (PCON)
27
PURCHASE OF PHILIPS I2C COMPONENTS
13
I2C-BUS SERIAL I/O
13.1
13.2
13.3
13.4
Serial Control Register (S1CON)
Serial Status Register (S1STA)
Data Shift Register (S1DAT)
Address Register (S1ADR)
1997 Mar 14
2
Philips Semiconductors
Product specification
Low voltage 8-bit microcontrollers with
UART and I2C-bus
1
P83CL781; P83CL782
2
FEATURES
• Full static 80C51 CPU
GENERAL DESCRIPTION
The term P83CL78x is used throughout this data sheet to
refer to both the P83CL781 and P83CL782; differences
between the devices are highlighted in the text.
• 8-bit CPU, ROM, RAM, I/O in a 40-lead DIP or 44-lead
QFP package
• 16 kbytes ROM, expandable externally to 64 kbytes
The P83CL78x is manufactured in an advanced CMOS
technology. The P83CL78x has the same instruction set
as the 80C51, consisting of over 100 instructions:
49 one-byte, 46 two-byte, and 16 three-byte. The device
has low power consumption and a wide range of supply
voltage; there are two software-selectable modes of
reduced activity for further power reduction: Idle and
Power-down. For emulation purposes, the P85CL781
(piggy-back version) with 256 bytes of RAM is
recommended.
• 256 bytes RAM, expandable externally to 64 kbytes
• Four 8-bit ports, 32 I/O lines
• Three 16-bit timer/event counters
• External memory expandable up to 128 kbytes: RAM up
to 64 kbytes and ROM up to 64 kbytes
• On-chip oscillator suitable for RC, LC, quartz crystal or
ceramic resonator
• Fifteen source, fifteen vector interrupt structure with two
priority levels
The P83CL782 is a faster version of the P83CL781 and
operates at a maximum frequency of 12 MHz at
VDD ≥ 3.1 V.
• Full duplex serial port (UART)
• I2C-bus interface for serial transfer on two lines
This data sheet details the specific properties of the
P83CL78x. For details of the 80C51 core and the I2C-bus
see “Data Handbook IC20”.
• Enhanced architecture with:
– non-page oriented instructions
– direct addressing
– four 8 byte RAM register banks
3
– stack depth limited only by available internal RAM
(maximum 256 bytes)
The P83CL78x is an 8-bit general purpose microcontroller
especially suited for cordless telephone applications.
The P83CL78x also functions as an arithmetic processor
having facilities for both binary and BCD arithmetic plus
bit-handling capabilities.
– multiply, divide, subtract and compare instructions
• Reduced power consumption through Power-down and
Idle modes
• Wake-up via external interrupts at Port 1
• Single supply voltage of 1.8 to 6.0 V
• Operating ambient temperature:
– 83CL781: −40 to +85 °C
– 83CL782: −25 to +55 °C.
• Frequency range of DC to 12 MHz
• Very low current consumption.
1997 Mar 14
3
APPLICATIONS
Philips Semiconductors
Product specification
Low voltage 8-bit microcontrollers with
UART and I2C-bus
4
P83CL781; P83CL782
ORDERING INFORMATION
PACKAGE
TYPE NUMBER(1)
NAME
P83CL781HFP
DESCRIPTION
VERSION
DIP40
plastic dual in-line package; 40 leads (600 mil)
SOT129-1
QFP44
plastic quad flat package; 44 leads (lead length 2.35 mm);
body 14 × 14 × 2.2 mm
SOT205-1
QFP44
plastic quad flat package; 44 leads (lead length 1.3 mm);
body 10 × 10 × 1.75 mm
SOT307-2
P83CL782HDP
P83CL781HFH
P83CL782HDH
P83CL781HFH
P83CL781HDH
Note
1. Refer to the Order Entry Form (OEF) for this device for the full type number, including options/program.
1997 Mar 14
4
Philips Semiconductors
Product specification
Low voltage 8-bit microcontrollers with
UART and I2C-bus
5
P83CL781; P83CL782
BLOCK DIAGRAM
T0
handbook, full pagewidth
T1
3
INT0
INT1
3
3
3
MLA601
XTAL1
VDD
TWO
16-BIT
TIMER/
EVENT
COUNTERS
(T0, T1)
XTAL2
EA
ALE
CPU
PROGRAM
MEMORY
DATA
MEMORY
16 kbyte
ROM
256 byte
RAM
80C51
core
excluding
ROM/RAM
PSEN
WR
3
8-bit internal bus
RD
P83CL781
P83CL782
3
RST
AD0 to 7
0
A8 to 15
2
PARALLEL
I/O PORTS
AND
EXTERNAL
BUS
16-BIT
TIMER/
EVENT
COUNTER
SERIAL
UART
PORT
V SS
3
P0 P1 P2 P3
3
TXD RXD
1
T2
1
T2EX
0 alternative function of Port 0
2 alternative function of Port 2
1 alternative functions of Port 1
3 alternative function of Port 3
Fig.1 Block diagram.
1997 Mar 14
I2 C
INTERFACE
5
1
SCL
1
SDA
Philips Semiconductors
Product specification
Low voltage 8-bit microcontrollers with
UART and I2C-bus
6
P83CL781; P83CL782
FUNCTIONAL DIAGRAM
handbook, full pagewidth
XTAL1
LOW ORDER
ADDRESS
AND
DATA BUS
(AD0 to AD7)
XTAL2
PORT 0
EA
PSEN
ALE
T2
T2EX
PORT 1
SCL
SDA
P83CL781
P83CL782
INT2
INT3
INT4
INT5
INT6
INT7
INT8
INT9
HIGH ORDER
ADDRESS
BUS
(A8 to A15)
PORT 2
RXD/data
TXD/clock
PORT 3
INT0
INT1
T0
T1
WR
RD
VSS
RST
VDD
MBH885
Fig.2 Functional diagram.
1997 Mar 14
6
Philips Semiconductors
Product specification
Low voltage 8-bit microcontrollers with
UART and I2C-bus
7
7.1
P83CL781; P83CL782
PINNING INFORMATION
Pinning
P1.0/INT2/T2
1
40
V DD
P1.1/INT3/T2EX
2
39
P0.0/AD0
P1.2/INT4
3
38
P0.1/AD1
P1.3/INT5
4
37
P0.2/AD2
P1.4/INT6
5
36
P0.3/AD3
P1.5/INT7
6
35 P0.4/AD4
P1.6/INT8/SCL
7
34 P0.5/AD5
P1.7/INT9/SDA
8
33
P0.6/AD6
RST
9
32
P0.7/AD7
31
EA
P3.0/RXD/data 10
P3.1/TXD/clock 11
P83CL781
P83CL782
30 ALE
PSEN
P3.2/INT0 12
29
P3.3/INT1 13
28 P2.7/A15
P3.4/T0 14
27
P3.5/T1 15
26 P2.5/A13
P2.6/A14
P3.6/WR 16
25
P3.7/RD 17
24 P2.3/A11
P2.4/A12
XTAL2
18
23
XTAL1
19
22 P2.1/A9
V SS
20
21 P2.0/A8
P2.2/A10
MLA603
Fig.3 Pin configuration for DIP40 package.
1997 Mar 14
7
Philips Semiconductors
Product specification
Low voltage 8-bit microcontrollers with
UART and I2C-bus
34 P0.3/AD3
35 P0.2/AD2
36 P0.1/AD1
n.c.
39
37 P0.0/AD0
P1.0/INT2/T2
40
38 VDD
P1.1/INT3/T2EX
41
42 P1.2/INT4
43 P1.3/INT5
44 P1.4/INT6
handbook, full pagewidth
P83CL781; P83CL782
P1.5/INT7
1
33
P0.4/AD4
P1.6/INT8/SCL
2
32
P0.5/AD5
P1.7/INT9/SDA
3
31
P0.6/AD6
RST
4
30
P0.7/AD7
P3.0/RXD/data
5
29
EA
n.c.
6
28
n.c.
P3.1/TXD/clock
7
27
ALE
P3.2/INT0
8
26
PSEN
P3.3/INT1
9
25
P2.7/A15
P3.4/T0
10
24
P2.6/A14
P3.5/T1
11
23
P2.5/A13
P83CL781
P83CL782
20
21
22
P2.2/A10
P2.3/A11
P2.4/A12
P2.1/A9 19
P2.0/A8 18
TEST/V
SS 17
VSS 16
XTAL1 15
XTAL2 14
P3.7/RD 13
P3.6/WR 12
MLA604
Fig.4 Pin configuration for QFP44 packages.
1997 Mar 14
8
Philips Semiconductors
Product specification
Low voltage 8-bit microcontrollers with
UART and I2C-bus
7.2
P83CL781; P83CL782
Pin description
PIN
SYMBOL
DESCRIPTION
DIP40
QFP44
P1.0/INT2/T2
1
40
P1.1/INT3/T2EX
2
41
P1.2/INT4
3
42
P1.3/INT5
4
43
• Port 1: 8-bit bidirectional I/O port (P1.0 to P1.7). Port pins that have logic 1s
written to them are pulled HIGH by internal pull-ups, and in this state can be
used as inputs (note that P1.6 and P1.7 are open-drain only). As inputs, Port 1
pins that are externally pulled LOW will source current (IIL) due to the internal
pull-ups. Port 1 output buffers can sink/source 4 LS TTL loads.
P1.4/INT6
5
44
• Alternative functions:
P1.5/INT7
6
1
– INT2 to INT9 are external interrupt inputs
P1.6/INT8/SCL
7
2
– T2 and T2EX are the Timer/event counter 2 inputs
P1.7/INT9/SDA
8
3
– SCL and SDA are the I2C-bus clock and data lines.
RST
9
4
Reset: A HIGH level on this pin for two machine cycles while the oscillator is
running, resets the device.
n.c.
−
6
Not connected.
P3.0/RXD/data
10
5
P3.1/TXD/clock
11
7
• Port 3: 8-bit bidirectional I/O port (P3.0 to P3.7).
Same characteristics as Port 1.
P3.2/INT0
12
8
• Alternative functions:
P3.3/INT1
13
9
P3.4/T0
14
10
P3.5/T1
15
11
P3.6/WR
16
12
P3.7/RD
17
13
– RXD/data is the UART serial data input (asynchronous) or data I/O
(synchronous)
– TXD/clock is the UART serial data output (asynchronous) or clock output
(synchronous)
– INT0 and INT1 are external interrupt lines
– T0 and T1 are external inputs for Timer 0 and Timer 1 respectively
– WR is the external memory write strobe and RD is the external memory read
strobe.
XTAL2
18
14
Crystal Output: Output of the inverting amplifier that forms the oscillator. Left
open-circuit when an external oscillator clock is used.
XTAL1
19
15
Crystal Input: Input to the inverting amplifier that forms the oscillator, also the
input for an externally generated clock source.
VSS
20
16
Ground: Circuit ground potential.
TEST/VSS
−
17
Test Input: Must be connected to VSS or left open.
P2.0/A8
21
18
P2.1/A9
22
19
• Port 2: 8-bit bidirectional I/O port (P2.0 to P2.7).
Same characteristics as Port 1.
P2.2/A10
23
20
P2.3/A11
24
21
P2.4/A12
25
22
P2.5/A13
26
23
P2.6/A14
27
24
P2.7/A15
28
25
1997 Mar 14
• High-order addressing: A8 to A15 make up the high-order address byte
during accesses to external memory that use 16-bit addresses
(MOVX@DPTR). In this application the pins use the strong internal pull-ups
when emitting logic 1's. During accesses to external memory that use 8-bit
addresses (MOVX@Ri), the pins emit the contents of the P2 Special Function
Register.
9
Philips Semiconductors
Product specification
Low voltage 8-bit microcontrollers with
UART and I2C-bus
P83CL781; P83CL782
PIN
SYMBOL
DESCRIPTION
DIP40
QFP44
PSEN
29
26
Program Store Enable: Read strobe to external Program Memory. When
executing code out of external Program Memory, PSEN is activated twice each
machine cycle. However, during each access to external Data Memory two
PSEN activations are skipped.
ALE
30
27
Address Latch Enable: Latches the low byte of the address during accesses to
external memory. It is activated every six oscillator periods and may be used for
external timing or clocking purposes.
n.c.
−
28
Not connected.
EA
31
29
External Access: When EA is held HIGH, the CPU executes out of the internal
Program Memory (unless the Program Counter exceeds 3FFFH). When EA is
held LOW, the CPU executes out of external Program Memory regardless of the
value of the program counter.
P0.7/AD7
32
30
P0.6/AD6
33
31
P0.5/AD5
34
32
• Port 0: 8-bit open-drain bidirectional I/O port (P0.7 to P0.0). As an open-drain
output port it can sink/source 8 LS TTL loads. Port 0 pins that have logic 1s
written to them float, and in this state will function as high-impedance inputs.
P0.4/AD4
35
33
P0.3/AD3
36
34
P0.2/AD2
37
35
P0.1/AD1
38
36
P0.0/AD0
39
37
VDD
40
38
Power supply.
n.c.
−
39
Not connected.
1997 Mar 14
• Low-order addressing: AD7 to AD0 provide the multiplexed low-order
address and data bus during accesses to external memory. In this application
the pins use the strong internal pull-ups when emitting logic 1s.
10
Philips Semiconductors
Product specification
Low voltage 8-bit microcontrollers with
UART and I2C-bus
8
P83CL781; P83CL782
The device has two software-selectable modes of reduced
activity for power reduction:
FUNCTIONAL DESCRIPTION OVERVIEW
This chapter gives a brief overview of the device. The
detailed functional description is in the following chapters:
• Idle mode; freezes the CPU while allowing the timers,
serial I/O and interrupt system to continue functioning.
Chapter 9 “Memory organization”
Chapter 11 “Timer/event counters”
• Power-down mode; saves the RAM contents but
freezes the oscillator causing all other chip functions to
be inoperative.
Chapter 12 “Reduced power modes”
In addition, two serial interfaces are provided on-chip:
Chapter 13 “I2C-bus serial I/O”
• a standard UART serial interface, and
Chapter 14 “Standard serial interface SIO0: UART”
• a standard I2C-bus serial interface. The I2C-bus serial
interface has byte-oriented master and slave functions
allowing communication with the whole family of I2C-bus
compatible devices.
Chapter 10 “I/O facilities”
Chapter 15 “Interrupt system”
Chapter 16 “Oscillator circuitry”
Chapter 17 “Reset”.
8.1
8.2
General
A machine cycle consists of a sequence of 6 states. Each
state lasts for two oscillator periods, thus a machine cycle
takes 12 oscillator periods or 1 µs if the oscillator
frequency (fosc) is 12 MHz.
The P83CL78x is a stand-alone high-performance CMOS
microcontroller designed for use in real-time applications
such as instrumentation, industrial control, intelligent
computer peripherals and consumer products. The device
provides hardware features, architectural enhancements
and new instructions to function as a controller for
applications requiring up to 64 kbytes of Program Memory
and/or up to 64 kbytes of data storage.
The P83CL78x contains a non-volatile 16 kbyte read-only
Program Memory; a static 256 byte read/write Data
Memory; 32 I/O lines; three 16-bit timer/event counters; a
fifteen-source, two priority-level, nested interrupt structure
and on-chip oscillator and timing circuit.
1997 Mar 14
CPU timing
11
Philips Semiconductors
Product specification
Low voltage 8-bit microcontrollers with
UART and I2C-bus
9
P83CL781; P83CL782
MEMORY ORGANIZATION
9.4
Addressing
The P83CL78x has a 16 kbyte Program Memory (ROM)
plus 256 bytes of Data Memory (RAM) on-chip. The device
has separate address spaces for Program and Data
Memory (see Fig.6). Using Ports P0 and P2, the
P83CL78x can address up to 128 kbytes of external
memory. The CPU generates both read (RD) and write
(WR) signals for external Data Memory accesses, and the
read strobe (PSEN) for external Program Memory.
The P83CL78x has five methods for addressing source
operands:
9.1
The first three methods can be used for addressing
destination operands. Most instructions have a
‘destination/source’ field that specifies the data type,
addressing methods and operands involved.
For operations other than MOVs, the destination operand
is also a source operand.
• Direct
• Register-indirect
• Immediate
• Base-register plus index-register-indirect.
Program memory
The P83CL78x contains 16 kbytes of internal ROM. After
reset the CPU begins execution at location 0000H.
The lower 16 kbytes of Program Memory can be
implemented in either on-chip ROM or external memory.
If the EA pin is strapped to VDD, then Program Memory
fetches from addresses 0000H through to 3FFFH are
directed to the internal ROM. Fetches from addresses
4000H through to FFFFH are directed to external ROM.
Program Counter values greater than 3FFFH are
automatically addressed to external memory regardless of
the state of the EA pin.
9.2
• Register
30H
2FH
Data memory
The P83CL78x contains 256 bytes of internal RAM and
34 Special Function Registers (SFRs). The memory map
(Fig.6 ) shows the internal Data Memory space divided into
the lower 128 bytes, the upper 128 bytes and the SFR
space. Internal RAM locations 0 to 127 are directly and
indirectly addressable. Internal RAM locations 128 to 255
are only indirectly addressable. The Special Function
Register locations 128 to 255 bytes are only directly
addressable.
9.3
7FH
alfpage
bit-addressable space
(bit addresses 0 to 7F)
Special Function Registers
The upper 128 bytes are the address locations of the
Special Function Registers. Figures 7 and 8 show the
Special Function Registers space. The SFRs include the
port latches, timers, peripheral control, serial I/O registers,
and so on. These registers can only be accessed by direct
addressing. There are 128 addressable locations in the
SFR address space (SFRs with addresses divisible by
eight).
1997 Mar 14
R7
20H
1FH
R0
R7
18H
17H
R0
R7
10H
0FH
R0
R7
08H
07H
R0
0
4 banks of 8 registers
(R0 to R7)
MLA560 - 1
Fig.5 The lower 128 bytes of internal RAM.
12
Philips Semiconductors
Product specification
Low voltage 8-bit microcontrollers with
UART and I2C-bus
Access to memory addressing is as follows:
The P83CL78x is classified as an 8-bit device since the
internal ROM, RAM, Special Function Registers,
Arithmetic Logic Unit and external data bus are all 8-bits
wide. It performs operations on bit, nibble, byte and
double-byte data types.
• Registers in one of the four register banks through
register, direct or register-indirect
• 256 bytes of internal data RAM through direct or
register-indirect
Facilities are available for byte transfer, logic and integer
arithmetic operations. Data transfer, logic and conditional
branch operations can be performed directly on Boolean
variables to provide excellent bit handling.
• Special Function Registers through direct
• External Data Memory through register-indirect
• Program Memory look-up tables through base-register
plus index-register-indirect.
handbook, full pagewidth
P83CL781; P83CL782
64 kbytes
EXTERNAL
64 kbytes
16 kbytes
16 kbytes
16 kbytes
OVERLAPPED SPACE
INTERNAL
EXTERNAL
(EA = 1)
(EA = 0)
255
(INDIRECT
ONLY)
127
SPECIAL
FUNCTION
REGISTERS
INTERNAL
DATA RAM
0
0
INTERNAL DATA MEMORY
PROGRAM MEMORY
MLA605
Fig.6 Memory map.
1997 Mar 14
13
EXTERNAL
DATA MEMORY
Philips Semiconductors
Product specification
Low voltage 8-bit microcontrollers with
UART and I2C-bus
REGISTER
MNEMONIC
P83CL781; P83CL782
DIRECT
BYTE
ADDRESS (HEX)
BIT ADDRESS
FFH
FEH
FDH
FCH
IP1
B
FF FE
FD
FC
FB
FA
F9
F8
F8H
F7
F5
F4
F3
F2
F1
F0
F0H
F6
EFH
EEH
EDH
ECH
EBH
EAH
E9H
IX1
IEN1
EF EE ED EC
EB EA
E9
E8
E8H
ACC
E7
E3
E1
E0
E0H
E6
E5
E4
E2
S1ADR
DBH
S1DAT
DAH
S1STA
S1CON
PSW
SFRs containing
directly addressable
bits
D9H
DF DE DD DC DB DA
D9
D8
D8H
D7 D6
D1
D0
D0H
D5
D4
D3
D2
CFH
TH2
CEH
CDH
TL2
CCH
RCAP2H
CBH
RCAP2L
CAH
C9H
T2CON
IRQ1
CF CE CD CC
CB CA C9
C8
C8H
C7 C6
C3
C0
C0H
C5
C4
C2
C1
MLA606 - 1
Fig.7 Special Function Register memory map (continued in Fig.8).
1997 Mar 14
14
Philips Semiconductors
Product specification
Low voltage 8-bit microcontrollers with
UART and I2C-bus
REGISTER
MNEMONIC
DIRECT
BYTE
ADDRESS (HEX)
BIT ADDRESS
IP0
P3
P83CL781; P83CL782
B7
BE BD BC
BB BA
B9
B8
B8H
B6
B3
B1
B0
B0H
B5
B4
B2
AFH
AEH
ADH
ACH
ABH
AAH
A9H
IEN0
P2
AF AE AD AC
AB AA
A9
A8
A8H
A7
A3
A1
A0
A0H
A6
A5
A4
A2
S0BUF
99H
S0CON
9F
9E
9D
9C
9B
9A
99
98
98H
P1
97
96
95
94
93
92
91
90
90H
TH1
TH0
8DH
8CH
TL1
8BH
TL0
8AH
89H
TMOD
TCON
8F
8E
8D
8C
8B
8A
89
88
88H
PCON
87H
DPH
83H
DPL
82H
SP
P0
SFRs containing
directly addressable
bits
81H
87
86
85
84
83
82
81
80
80H
MLA607
Fig.8 Special Function Register memory map (continued from Fig.7).
1997 Mar 14
15
Philips Semiconductors
Product specification
Low voltage 8-bit microcontrollers with
UART and I2C-bus
P83CL781; P83CL782
LOW-to-HIGH transition in the port latch;
Fig.9(a).
10 I/O FACILITIES
10.1
Ports
Option 2 Open-drain; quasi-bidirectional I/O with
n-channel open-drain output. Use as an output
requires the connection of an external pull-up
resistor; Fig.9(b).
The P83CL78x has 32 I/O lines treated as 32 individually
addressable bits or as four parallel 8-bit ports. To enable a
port pin alternative function, the port bit latch in its SFR
must contain a logic 1. The alternative functions are
detailed below:
Option 3 Push-Pull; output with drive capability in both
polarities. Under this option, pins can only be
used as outputs; Fig.9(c).
Port 0 Provides the multiplexed low-order address and
data bus for expanding the device with standard
memories and peripherals.
10.3
Port 1 Used for a number of special functions:
The definition of port options for Port 0 is slightly different.
Two cases are considered. First, access to external
memory (EA = 0 or access above the built-in memory
boundary) and second, I/O accesses.
• Provides the inputs for the eight external
interrupts: INT2 to INT9
• External activation of Timer 2: T2
• The I2C-bus interface: SCL and SDA.
10.3.1
Port 2 Provides the high-order address when expanding
the device with external Program or Data memory.
Option 2 An external pull-up resistor is required for
external accesses.
• External interrupt request inputs: INT1 and INT0
• Timer/counter inputs: T1 and T0
Option 3 Not allowed for external memory accesses as
the port can only be used as output.
• Control signals to read and write to external
memories: RD and WR
10.3.2
• UART asynchronous input and output (RXD and
TXD); or UART synchronous I/O and clock lines
(data and clock).1
I/O ACCESSES
Option 1 When writing a logic 1 to the port latch, the
strong pull-up ‘p1’ will be on for 2 oscillator
periods. No weak pull-up exists. Without an
external pull-up, this option can be used as a
high-impedance input.
Each port consists of a latch (SFRs P0 to P3), an output
driver and input buffer. Ports 1, 2 and 3 have internal
pull-ups (except P1.6 and P1.7). Figure 9(a) shows that
the strong transistor ‘p1’ is turned on for only 2 oscillator
periods after a LOW-to-HIGH transition in the port latch.
When on, it turns on p3 (a weak pull-up) through the
inverter. This inverter and p3 form a latch which holds the
logic 1. In Port 0 the pull-up ‘p1’ is only on when emitting
logic 1s for external memory access. Writing a logic 1 to a
Port 1 bit latch leaves both output transistors switched off
so that the pin can be used as an high-impedance input.
Option 2 Open-drain; quasi-directional I/O with n-channel
open-drain output. Use as an output requires the
connection of an external pull-up resistor. See
Fig.9(b).
Option 3 Push-Pull; output with drive capability in both
polarities. Under this option pins can only be
used as outputs. See Fig.9(c).
10.4
Port options
SET/RESET options
Individual mask selection of the post-reset state is
available with any of the above pins. The required
selection is made by appending ‘S’ or ‘R’ to Options 1, 2,
or 3 above.
30 of the 32 port pins (excluding P1.6 and P1.7 with option
2S only) may be individually configured with one of the
following options. These options are also shown in Fig.9.
Option 1 Standard Port; quasi-bidirectional I/O with
pull-up. The strong booster pull-up ‘p1’ is turned
on for two oscillator periods after a
1997 Mar 14
EXTERNAL MEMORY ACCESSES
Option 1 True logic 0 and logic 1 are written as address to
the external memory (strong pull-up to be used).
Port 3 Pins can be configured individually to provide:
10.2
Port 0 options
Option R RESET, at reset this pin will be initialized LOW.
Option S SET, at reset this pin will be initialized HIGH.
16
Philips Semiconductors
Product specification
Low voltage 8-bit microcontrollers with
UART and I2C-bus
P83CL781; P83CL782
strong pull-up
handbook, full pagewidth
+5 V
2 oscillator
periods
p2
p3
p1
I/O pin
Q
from port latch
n
input data
INPUT
BUFFER
read port pin
(a) Standard
+5 V
external
pull-up
Q
from port latch
I/O pin
n
input data
read port pin
INPUT
BUFFER
(b) Open-drain
strong pull-up
+5 V
p1
I/O pin
Q
from port latch
n
(c) Push-pull
Fig.9 Port configuration options.
1997 Mar 14
17
MGD677
Philips Semiconductors
Product specification
Low voltage 8-bit microcontrollers with
UART and I2C-bus
P83CL781; P83CL782
11 TIMER/EVENT COUNTERS
11.2.1
The P83CL78x contains three 16-bit timer/event counter
registers; Timer 0, Timer 1 and Timer 2 which can perform
the following functions:
Figure 10 shows the Capture mode. Two options in this
mode, may be selected by the EXEN2 bit in T2CON:
• If EXEN2 = 0, then Timer 2 is a 16-bit timer or counter
which upon overflowing sets the Timer 2 overflow bit
TF2, this may then be used to generate an interrupt.
• Measure time intervals and pulse durations
• Count events
• If EXEN2 = 1, Timer 2 operates as described above but
with the additional feature that a HIGH-to-LOW
transition at external input T2EX causes the current
value in TL2 and TH2 to be captured into registers
RCAP2L and RCAP2H respectively. In addition, the
transition at T2EX causes the EXF2 bit in T2CON to be
set; this may also be used to generate an interrupt.
• Generate interrupt requests.
In the ‘Timer’ operating mode the register is incremented
every machine cycle. Since a machine cycle consists of
12 oscillator periods, the count rate is 1⁄12 × fosc.
In the ‘Counter’ operating mode, the register is
incremented in response to a HIGH-to-LOW transition.
Since it takes 2 machine cycles (24 oscillator periods) to
recognize a HIGH-to-LOW transition, the maximum count
rate is 1⁄24 × fosc. To ensure a given level is sampled, it
should be held for at least one complete machine cycle.
11.1
11.2.2
• If EXEN2 = 0, then when Timer 2 rolls over, it sets the
TF2 bit but also causes the Timer 2 registers to be
reloaded with the 16-bit value held in registers RCAP2L
and RCAP2H. The 16-bit value held in these registers is
preset by software.
Timer 0 and Timer 1
Mode 0 8-bit timer or 8-bit counter each with divide-by-32
prescaler.
• If EXEN2 = 1, Timer 2 operates as described above but
with the additional feature that a HIGH-to-LOW
transition at external input T2EX will also trigger the
16-bit reload and set the EXF2 bit.
Mode 1 16-bit time-interval or event counter.
Mode 2 8-bit time-interval or event counter with automatic
reload upon overflow.
11.2.3
Mode 3 Timer 0 establishes TL0 and TH0 as two
separate counters.
BAUD RATE GENERATOR MODE
The Baud Rate Generator mode is selected when
RTCLK = 1. It will be described in conjunction with the
serial port (UART); see Section 14.3.2.
Timer T2
Timer T2 is a 16-bit timer/counter that can operate (like
Timer 0 and 1) either as a timer or as an event counter.
These functions are selected by the state of the C/T2 bit in
the T2CON register; see Tables 1 and 2.
Three operating modes are available Capture, Auto-reload
and Baud Rate Generator, which also are selected via the
T2CON register; see Table 3.
1997 Mar 14
AUTO-RELOAD MODE
Figure 11 shows the Auto-reload mode. Also two options
in this mode are selected by the EXEN2 bit in T2CON:
Timer 0 and Timer 1 can be programmed independently to
operate in four modes:
11.2
CAPTURE MODE
18
Philips Semiconductors
Product specification
Low voltage 8-bit microcontrollers with
UART and I2C-bus
handbook, full pagewidth
OSC
12
C/T2 = 0
TL2
(8 BITS)
T2 PIN
P83CL781; P83CL782
C/T2 = 1
TH2
(8 BITS)
TF2
control
TR2
Timer 2
interrupt
capture
transition
detector
RCAP2L
RCAP2H
T2EX PIN
EXF2
MLA608
control
EXEN2
Fig.10 Timer 2 in Capture mode.
handbook, full pagewidth
OSC
12
C/T2 = 0
TL2
(8 BITS)
T2 PIN
C/T2 = 1
TH2
(8 BITS)
TF2
control
TR2
Timer 2
interrupt
reload
RCAP2L
transition
detector
RCAP2H
T2EX PIN
EXF2
MLA609
control
EXEN2
Fig.11 Timer 2 in Auto-Reload mode.
1997 Mar 14
19
Philips Semiconductors
Product specification
Low voltage 8-bit microcontrollers with
UART and I2C-bus
11.3
P83CL781; P83CL782
Timer/Counter 2 Control Register (T2CON)
Table 1
Timer/Counter 2 Control Register (SFR address C8H)
7
6
5
4
3
2
1
0
TF2
EXF2
GF2
RTCLK
EXEN2
TR2
C/T2
CP/RL2
Table 2
Description of T2CON bits
BIT
SYMBOL
DESCRIPTION
7
TF2
Timer 2 overflow flag. Set by a Timer 2 overflow and must be cleared by software. TF2
will not be set when RTCLK = 1.
6
EXF2
Timer 2 external flag. Set when either a capture or reload is caused by a negative
transition on T2EX and when EXEN2 = 1. When Timer T2 interrupt is enabled,
EXF2 = 1 will cause the CPU to vector to Timer 2 interrupt routine. EXF2 must be
cleared by software.
5
GF2
General purpose flag bit.
4
RTCLK
Receive/transmit clock flag. When set, causes the UART serial port to use Timer 2
overflow pulses for its receive and transmit clock in Modes 1 and 3. RTCLK = 0 causes
Timer 1 overflows to be used for the receive and transmit clock.
3
EXEN2
Timer 2 external enable flag. When set, allows a capture or reload to occur as a result
of a negative transition on T2EX, if Timer 2 is not being used to clock the serial port.
EXEN2 = 0, causes Timer 2 to ignore events at T2EX.
2
TR2
Start/stop control for Timer 2. TR2 = 1 starts the timer.
1
C/T2
Timer or counter select for Timer 2. C/T2 = 0 selects the internal timer with a clock
frequency of 1⁄12 × fosc. C/T2 = 1 selects the external event counter; negative edge
triggered.
0
CP/RL2
Table 3
Capture/Reload flag. When set, captures will occur on negative transitions at T2EX, if
EXEN2 = 1. When cleared, auto-reloads will occur either with Timer 2 overflows or
negative transitions at T2EX when EXEN2 = 1. When RTCLK = 1, this bit is ignored and
the timer is forced to auto-reload on a Timer 2 overflow.
Timer 2 operating modes; X = don’t care
RTCLK
CP/RL2
TR2
0
0
1
16-bit Auto-reload
0
1
1
16-bit Capture
1
X
1
Baud Rate Generator
X
X
0
Off
1997 Mar 14
MODE
20
Philips Semiconductors
Product specification
Low voltage 8-bit microcontrollers with
UART and I2C-bus
P83CL781; P83CL782
12 REDUCED POWER MODES
12.2
There are two software-selectable modes which further
reduce power consumption: ‘Idle’ and ‘Power-down’.
Operation in Power-down mode freezes the oscillator.
The internal connections which link both Idle and
Power-down signals to the clock generation circuit are
shown in Fig.12.
12.1
Idle mode
Power-down mode
Power-down mode is entered by setting the PD bit in the
Power Control Register (PCON.1, see Table 5).
The instruction that sets PD is the last executed prior to
going into the Power-down mode.
Operation in Idle mode permits the interrupt, serial ports
and timer blocks to continue to function while the clock to
the CPU is halted.
Idle mode is entered by setting the IDL bit in the Power
Control Register (PCON.0, see Table 5). The instruction
that sets IDL is the last instruction executed in the normal
operating mode before the Idle mode is activated.
Once in the Power-down mode, the oscillator is stopped.
The contents of the on-chip RAM and the SFRs are
preserved. The port pins output the value held by their
respective SFRs. ALE and PSEN are held LOW.
Once in the Idle mode, the CPU status is preserved along
with the Stack Pointer, Program Counter, Program Status
Word and Accumulator. The RAM and all other registers
maintain their data during Idle mode. The status of the
external pins during Idle mode is shown in Table 4.
In the Power-down mode, VDD may be reduced to
minimize circuit power consumption. The supply voltage
must not be reduced until the Power-down mode is
entered, and must be restored before the hardware reset
is applied which will free the oscillator. Reset should not be
released until the oscillator has restarted and stabilized.
The following functions remain active during the Idle
mode:
• Timer 0, Timer 1 and Timer 2
12.3
• UART, I2C-bus interface
Wake-up from Power-down mode
When in Power-down mode the controller can be
woken-up with either the external interrupts INT2 to INT9,
or a reset operation. The wake-up operation has two basic
approaches as explained in Section 12.3.1; 12.3.2 and
illustrated in Fig.13.
• External interrupt.
These functions may generate an interrupt or reset; thus
ending the Idle mode.
There are two ways to terminate the Idle mode:
12.3.1
1. Activation of any enabled interrupt will cause PCON.0
to be cleared by hardware thus terminating the Idle
mode. The interrupt is serviced, and following the
RETI instruction, the next instruction to be executed
will be the one following the instruction that put the
device in the Idle mode. The flag bits GF0 and GF1
may be used to determine whether the interrupt was
received during normal execution or during the Idle
mode. For example, the instruction that writes to
PCON.0 can also set or clear one or both flag bits.
When the Idle mode is terminated by an interrupt, the
service routine can examine the status of the flag bits.
If any of the interrupts INT2 to INT9 are enabled, the
device can be woken-up from the Power-down mode with
the external interrupts. To ensure that the oscillator is
stable before the controller restarts, the internal clock will
remain inactive for 1536 oscillator periods. This is
controlled by an on-chip delay counter.
12.3.2
WAKE-UP USING RST
To wake-up the P83CL78x, the RST pin must be kept
HIGH for a minimum of 24 periods. The on-chip delay
counter is inactive. The user must ensure that the oscillator
is stable before any operation is attempted.
2. The second way of terminating the Idle mode is with an
external hardware reset, or an internal reset caused by
an overflow of Timer T2. Since the oscillator is still
running, the hardware reset is required to be active for
two machine cycles (24 oscillator periods) to complete
the reset operation. Reset redefines all SFRs but does
not affect the on-chip RAM.
1997 Mar 14
WAKE-UP USING INT2 TO INT9
21
Philips Semiconductors
Product specification
Low voltage 8-bit microcontrollers with
UART and I2C-bus
12.4
If the data is a logic 1, the port pin is held HIGH during the
Power-down mode by the strong pull-up transistor ‘p1’;
see Fig.9(a).
Status of external pins
The status of the external pins during Idle and Power-down
mode is shown in Table 4. If the Power-down mode is
activated whilst accessing external Program Memory, the
port data that is held in the Special Function Register P2 is
restored to Port 2.
Table 4
P83CL781; P83CL782
Status of external pins during Idle and Power-down modes
MODE
MEMORY
ALE
PSEN
PORT 0
PORT 1
PORT 2
PORT 3
Idle
internal
1
1
port data
port data
port data
port data
Idle
external
1
1
floating
port data
address
port data
Power-down
internal
0
0
port data
port data
port data
port data
Power-down
external
0
0
floating
port data
port data
port data
12.5
Power Control Register (PCON)
The reduced power modes are activated by software using this Special Function Register. PCON is not bit addressable.
Table 5
Power Control Register (SFR address 87H)
7
6
5
4
3
2
1
0
SMOD
−
−
−
GF1
GF0
PD
IDL
Table 6
Description of PCON bits
BIT
SYMBOL
FUNCTION
PCON.7
SMOD
Double Baud rate bit. When set to a logic 1 the baud rate is doubled when the serial port
SIO0 is being used in modes 1, 2 or 3.
PCON.6
−
Reserved
PCON.5
−
Reserved
PCON.4
−
Reserved
PCON.3
GF1
PCON.2
GF0
General purpose flag bit
PCON.1
PD
Power-down bit. Setting this bit activates the Power-down mode; see note 1.
PCON.0
IDL
Idle mode bit. Setting this bit activates the Idle mode; see note 1.
General purpose flag bit
Note
1. If logic 1s are written to PD and IDL at the same time, PD takes precedence. The reset value of PCON is (0XX00000).
1997 Mar 14
22
Philips Semiconductors
Product specification
Low voltage 8-bit microcontrollers with
UART and I2C-bus
P83CL781; P83CL782
handbook, full pagewidth
XTAL2
XTAL1
OSCILLATOR
interrupts
serial ports
timer blocks
CLOCK
GENERATOR
CPU
P83CL781
P83CL782
IDL
PD
MBB552
Fig.12 Internal clock control in Idle and Power-down modes.
handbook, full pagewidth
power-down
RST pin
external
interrupt
oscillator
MGD679
24 periods
delay counter
1536 periods
Fig.13 Wake-up operation.
1997 Mar 14
23
Philips Semiconductors
Product specification
Low voltage 8-bit microcontrollers with
UART and I2C-bus
P83CL781; P83CL782
These functions are controlled by the Serial Control
Register S1CON. S1STA is the Status Register whose
contents may also be used as a vector to various service
routines. S1DAT is the Data Shift Register and S1ADR is
the Slave Address Register. Slave address recognition is
performed by on-chip hardware.
13 I2C-BUS SERIAL I/O
The serial port supports the twin line I2C-bus, which
consists of a serial data line (SDA) and a serial clock line
(SCL). These lines also function as the I/O port lines P1.7
and P1.6 respectively.
The system is unique because data transport, clock
generation, address recognition and bus control arbitration
are all controlled by hardware.
Figure 14 is the block diagram of the I2C-bus serial I/O.
The I2C-bus serial I/O has complete autonomy in byte
handling and operates in 4 modes:
• Master transmitter
• Master receiver
• Slave transmitter
• Slave receiver.
7
0
SLAVE ADDRESS
GC
S1ADR
7
0
S1DAT
ARBITRATION
SYNC LOGIC
SCL
BUS CLOCK GENERATOR
7
0
CONTROL REGISTER
S1CON
7
0
STATUS REGISTER
S1STA
MLB199
Fig.14 Block diagram of I2C-bus serial I/O.
1997 Mar 14
24
INTERNAL BUS
SHIFT REGISTER
SDA
Philips Semiconductors
Product specification
Low voltage 8-bit microcontrollers with
UART and I2C-bus
13.1
P83CL781; P83CL782
Serial Control Register (S1CON)
Table 7
Serial Control Register (SFR address D8H)
7
6
5
4
3
2
1
0
CR2
ENS1
STA
STO
SI
AA
CR1
CR0
Table 8
Description of S1CON bits
BIT
SYMBOL
DESCRIPTION
7
CR2
This bit along with bits CR1 (S1CON.1) and CR0 (S1CON.0) determines the serial clock
frequency when SIO is in the Master mode. See Table 9.
6
ENS1
ENABLE serial I/O. When ENS1 = 0, the serial I/O is disabled. SDA and SCL outputs
are in the high impedance state; P1.6 and P1.7 function as open-drain ports. When
ENS1 = 1, the serial I/O is enabled. Output port latches P1.6 and P1.7 must be set to
logic 1.
5
STA
START flag. When this bit is set in Slave mode, the SIO hardware checks the status of
the I2C-bus and generates a START condition if the bus is free or after the bus becomes
free. If STA is set while the SIO is in Master mode, SIO will generate a repeated START
condition.
4
STO
STOP flag. With this bit set while in Master mode a STOP condition is generated. When
a STOP condition is detected on the I2C-bus, the SIO hardware clears the STO flag.
STO may also be set in Slave mode in order to recover from an error condition. In this
case no STOP condition is transmitted to the I2C-bus. However, the SIO hardware
behaves as if a STOP condition has been received and releases the SDA and SCL. The
SIO then switches to the not addressed slave receiver mode. The STOP flag is cleared
by the hardware.
3
SI
SIO interrupt flag. This flag is set, and an interrupt is generated, after any of the
following events occur:
• A start condition is generated in Master mode
• Own slave address has been received during AA = 1
• The general call address has been received while GC (S1ADR.0) = 1 and AA = 1
• A data byte has been received or transmitted in Master mode (even if arbitration is lost)
• A data byte has been received or transmitted as selected slave
• A Stop or Start condition is received as selected slave receiver or transmitter.
2
AA
Assert Acknowledge. When this bit is set, an acknowledge (low level to SDA) is
returned during the acknowledge clock pulse on the SCL line when:
• Own slave address is received
• General call address is received; GC (S1ADR.0) = 1
• A data byte is received while the device is programmed to be a Master Receiver
• A data byte is received while the device is a selected Slave Receiver.
When this bit is reset, no acknowledge is returned. Consequently, no interrupt is
requested when the own slave address or general call address is received.
1
CR1
0
CR0
1997 Mar 14
These two bits along with the CR2 (S1CON.7) bit determine the serial clock frequency
when SIO is in the Master mode. See Table 9.
25
Philips Semiconductors
Product specification
Low voltage 8-bit microcontrollers with
UART and I2C-bus
Table 9
Selection of the serial clock frequency SCL in a Master mode of operation
CR2
13.2
P83CL781; P83CL782
CR1
CR0
BIT RATE (kHz) AT fosc
fosc DIVISOR
3.58 MHz
6 MHz
12 MHz
0
0
0
256
14.0
23.4
46.9
0
0
1
224
16.0
26.8
53.6
0
1
0
192
18.6
31.3
62.5
0
1
1
160
22.4
37.5
75.0
1
0
0
960
1
0
1
120
29.8
50.0
1
1
0
60
59.7
100.0
1
1
1
not allowed
−
3.73
6.25
12.5
100.0
−
−
−
Serial Status Register (S1STA)
S1STA is a read-only register.The contents of this register may be used as a vector to a service routine. This optimizes
the response time of the software and consequently that of the I2C-bus. The status codes for all possible modes of the
I2C-bus interface are given in Tables 12 to 16.
Table 10 Serial Status Register (address D9H)
7
6
5
4
3
2
1
0
SC4
SC3
SC2
SC1
SC0
0
0
0
Table 11 Description of S1STA bits
BIT
SYMBOL
3 to 7
SC4 to SC0
0 to 2
−
DESCRIPTION
5-bit status code.
These three bits are always zero.
Table 12 MST/TRX mode
S1STA VALUE
1997 Mar 14
DESCRIPTION
08H
A START condition has been transmitted.
10H
A repeated START condition has been transmitted.
18H
SLA and W have been transmitted, ACK has been received.
20H
SLA and W have been transmitted, ACK received.
28H
DATA of S1DAT has been transmitted, ACK received.
30H
DATA of S1DAT has been transmitted, ACK received.
38H
Arbitration lost in SLA, R/W or DATA.
26
Philips Semiconductors
Product specification
Low voltage 8-bit microcontrollers with
UART and I2C-bus
P83CL781; P83CL782
Table 13 MST/REC mode
S1STA VALUE
DESCRIPTION
08H
A START condition has been transmitted.
10H
A repeated START condition has been transmitted.
38H
Arbitration lost while returning ACK.
40H
SLA and R have been transmitted, ACK received.
48H
SLA and R have been transmitted, ACK received.
50H
DATA has been received, ACK returned.
58H
DATA has been received, ACK returned.
Table 14 SLV/REC mode
S1STA VALUE
DESCRIPTION
60H
Own SLA and W have been received, ACK returned.
68H
Arbitration lost in SLA, R/W as MST. Own SLA and W have been received, ACK returned.
70H
General CALL has been received, ACK returned.
78H
Arbitration lost in SLA, R/W as MST. General CALL has been received.
80H
Previously addressed with own SLA. DATA byte received, ACK returned.
88H
Previously addressed with own SLA. DATA byte received, ACK returned.
90H
Previously addressed with general CALL. DATA byte has been received, ACK has been returned.
98H
Previously addressed with general CALL. DATA byte has been received, ACK has been returned.
A0H
A STOP condition or repeated START condition has been received while still addressed as SLV/REC
or SLV/TRX.
Table 15 SLV/TRX mode
S1STA VALUE
DESCRIPTION
A8H
Own SLA and R have been received, ACK returned.
B0H
Arbitration lost in SLA, R/W as MST. Own SLA and R have been received, ACK returned.
B8H
DATA byte has been transmitted, ACK received.
C0H
DATA byte has been transmitted, ACK received.
C8H
Last DATA byte has been transmitted (AA = 0), ACK received.
Table 16 Miscellaneous
S1STA VALUE
DESCRIPTION
00H
Bus error during MST mode or selected SLV mode, due to an erroneous START or STOP condition.
F8H
No relevant state information available, SI = 0.
1997 Mar 14
27
Philips Semiconductors
Product specification
Low voltage 8-bit microcontrollers with
UART and I2C-bus
P83CL781; P83CL782
Table 17 Symbols used in Tables 12 to 16
SYMBOL
DESCRIPTION
SLA
7-bit slave address
R
Read bit
W
Write bit
ACK
Acknowledgement (acknowledge bit is logic 0)
ACK
No acknowledgement (acknowledge bit is logic 1)
DATA
8-bit data byte to or from I2C-bus
MST
Master
SLV
Slave
TRX
Transmitter
REC
Receiver
13.3
Data Shift Register (S1DAT)
S1DAT contains the serial data to be transmitted or data which has just been received. The MSB (bit 7) is transmitted or
received first; i.e. data shifted from right to left.
Table 18 Data Shift Register (SFR address DAH)
7
6
5
4
3
2
1
0
S1DAT.7
S1DAT.6
S1DAT.5
S1DAT.4
S1DAT.3
S1DAT.2
S1DAT.1
S1DAT.0
13.4
Address Register (S1ADR)
This 8-bit register may be loaded with the 7-bit slave address to which the controller will respond when programmed as
a slave receiver/transmitter.
Table 19 Address Register (SFR address DBH)
7
6
5
4
3
2
1
0
SLA6
SLA5
SLA4
SLA3
SLA2
SLA1
SLA0
GC
Table 20 Description of S1ADR bits
BIT
SYMBOL
7 to 1
SLA6 to SLA0
0
GC
1997 Mar 14
DESCRIPTION
Own slave address.
This bit is used to determine whether the general call address is recognized. When
GC = 0, the general call address is not recognized; when GC = 1, the general call
address is recognized.
28
Philips Semiconductors
Product specification
Low voltage 8-bit microcontrollers with
UART and I2C-bus
P83CL781; P83CL782
14 STANDARD SERIAL INTERFACE SIO0: UART
14.1
This serial port is full duplex which means that it can
transmit and receive simultaneously. It is also
receive-buffered and can commence reception of a
second byte before a previously received byte has been
read from the register. (However, if the first byte has not
been read by the time the reception of the second byte is
complete, one of the bytes will be lost). The serial port
receive and transmit registers are both accessed via the
Special Function Register S0BUF. Writing to S0BUF loads
the transmit register and reading S0BUF accesses a
physically separate receive register.
Modes 2 and 3 have a special provision for multiprocessor
communications. In these modes, 9 data bits are received.
The 9th bit goes into RB8. The following bit is the stop bit.
The port can be programmed such that when the stop bit
is received, the serial port interrupt will be activated, but
only if RB8 = 1. This feature is enabled by setting bit SM2
in S0CON. One use of this feature, in multiprocessor
systems, is as follows.
When the master processor wants to transmit a block of
data to one of several slaves, it first sends out an address
byte which identifies the target slave. An address byte
differs from a data byte in that the 9th bit is HIGH in an
address byte and LOW in a data byte. With SM2 = 1, no
slave will be interrupted by a data byte. An address byte,
however, will interrupt all slaves, so that each slave can
examine the received byte and see if it is being addressed.
The addressed slave will clear its SM2 bit and prepare to
receive the data bytes that will be sent. The slaves that
were not being addressed leave their SM2 bits set and go
on about their business, ignoring the coming data bytes.
The serial port can operate in 4 modes:
Mode 0 Serial data enters and exits through RXD. TXD
outputs the shift clock. Eight bits are
transmitted/received (LSB first). The baud rate is
fixed at 1⁄12 × fosc.
Mode 1 10 bits are transmitted (through TXD) or received
(through RXD): a start bit (logic 0), 8 data bits
(LSB first), and a stop bit (logic 1). On receive,
the stop bit goes into RB8 in Special Function
Register S0CON. The baud rate is variable.
SM2 has no effect in Mode 0, and in Mode 1 can be used
to check the validity of the stop bit. In a Mode 1 reception,
if SM2 = 1, the receive interrupt will not be activated unless
a valid stop bit is received.
Mode 2 11 bits are transmitted (through TXD) or received
(through RXD): start bit (logic 0), 8 data bits (LSB
first), a programmable 9th data bit, and a stop bit
(logic 1). On transmit, the 9th data bit (TB8 in
S0CON) can be assigned the value of a logic 0 or
logic 1. Or, for example, the parity bit (P, in the
PSW) could be moved into TB8. On receive, the
9th data bit goes into RB8 in S0CON, while the
stop bit is ignored. The baud rate is
programmable to either 1⁄32 or 1⁄64 × fosc.
Mode 3 11 bits are transmitted (through TXD) or received
(through RXD): a start bit (logic 0), 8 data bits
(LSB first), a programmable 9th data bit and a
stop bit (logic 1). In fact, Mode 3 is the same as
Mode 2 in all respects except baud rate.
The baud rate in Mode 3 is variable.
In all four modes, transmission is initiated by any
instruction that uses S0BUF as a destination register.
Reception is initiated in Mode 0 by the condition RI = 0 and
REN = 1. Reception is initiated in the other modes by the
incoming start bit if REN = 1.
1997 Mar 14
Multiprocessor communications
29
Philips Semiconductors
Product specification
Low voltage 8-bit microcontrollers with
UART and I2C-bus
14.2
P83CL781; P83CL782
Serial Port Control and Status Register (S0CON)
The Serial Port Control and Status Register is the Special Function Register S0CON. The register contains not only the
mode selection bits, but also the 9th data bit for transmit and receive (TB8 and RB8), and the serial port interrupt bits
(TI and RI).
Table 21 Serial Port Control Register (address 98H)
7
6
5
4
3
2
1
0
SMO
SM1
SM2
REN
TB8
RB8
TI
RI
Table 22 Description of S0CON bits
BIT
SYMBOL
DESCRIPTION
7
SM0
6
SM1
5
SM2
Enables the multiprocessor communication feature in Modes 2 and 3. In these modes,
if SM2 = 1, then RI will not be activated if the received 9th data bit (RB8) is a logic 0.
In Mode 1, if SM2 = 1, then RI will not be activated unless a valid stop bit was received.
In Mode 0, SM2 should be a logic 0.
4
REN
Enables serial reception and is set by software to enable reception, and cleared by
software to disable reception.
3
TB8
Is the 9th data bit that will be transmitted in Modes 2 and 3. Set or cleared by software as
desired.
2
RB8
In Modes 2 and 3, is the 9th data bit received. In Mode 1, if SM2 = 0 then RB8 is the stop
bit that was received. In Mode 0, RB8 is not used.
1
TI
The transmit interrupt flag. Set by hardware at the end of the 8th bit time in Mode 0, or
at the beginning of the stop bit time in the other modes, in any serial transmission. Must
be cleared by software.
0
RI
The receive interrupt flag. Set by hardware at the end of the 8th bit time in Mode 0, or
halfway through the stop bit time in the other modes, in any serial transmission (except
see SM2). Must be cleared by software.
These bits are used to select the serial port mode; see Table 23.
Table 23 Selection of the serial port modes
SMO
SM1
MODE
DESCRIPTION
0
0
Mode 0
Shift register
0
1
Mode 1
8-bit UART
1
0
Mode 2
9-bit UART
1
1
Mode 3
9-bit UART
1997 Mar 14
30
BAUD RATE
1⁄
12
× fosc
variable
1⁄
32
or 1⁄64 × fosc
variable
Philips Semiconductors
Product specification
Low voltage 8-bit microcontrollers with
UART and I2C-bus
14.3
The Timer 1 interrupt should be disabled in this
application. The Timer itself can be configured for either
‘timer’ or ‘counter’ operation in any of its 3 running modes.
In most typical applications, it is configured for ‘timer’
operation, in the Auto-reload mode (high nibble of
TMOD = 0010B). In this case the baud rate is given by the
formula:
Baud rates
The baud rate in Mode 0 is fixed and may be calculated as:
f osc
Baud Rate = -------12
The baud rate in Mode 2 depends on the value of the
SMOD bit in Special Function Register PCON and may be
calculated as:
SMOD
f osc
2
Baud Rate = ----------------- × -------------------------------------------------------32
{ 12 × ( 256 – TH1 ) }
SMOD
2
Baud Rate = ----------------- × f osc
64
• If SMOD = 0 (value on reset), the baud rate is
By configuring Timer 1 to run as a 16-bit timer (high nibble
of TMOD = 0001B), and using the Timer 1 interrupt to do
a 16-bit software reload, very low baud rates can be
achieved. Table 24 lists commonly used baud rates and
how they can be obtained from Timer 1.
1⁄ × f
64
osc
• If SMOD = 1, the baud rate is 1⁄32 × fosc
The baud rates in Modes 1 and 3 are determined by the
Timer 1 or Timer 2 overflow rate.
14.3.1
P83CL781; P83CL782
USING TIMER 1 TO GENERATE BAUD RATES
When Timer 1 is used as the Baud Rate Generator, the
baud rates in Modes 1 and 3 are determined by the
Timer 1 overflow rate and the value of the SMOD bit as
follows:
SMOD
2
Baud Rate = ----------------- × Timer 1 Overflow Rate.
32
Table 24 Commonly used baud rates generated by Timer 1
fosc (MHz)
SMOD
C/T
TIMER 1 MODE
RELOAD VALUE
1000.0(1)
12.000
X(2)
X
X
X
375.0(3)
12.000
1
X
X
X
62.5(4)
12.000
1
0
Mode 2
FFH
19.2
11.059
1
0
Mode 2
FDH
9.6
11.059
0
0
Mode 2
FDH
4.8
11.059
0
0
Mode 2
FAH
2.4
11.059
0
0
Mode 2
F4H
1.2
11.059
0
0
Mode 2
E8H
137.5
11.986
0
0
Mode 2
1DH
110.0
6.000
0
0
Mode 2
72H
110.0
12.000
0
0
Mode 1
FEEBH
BAUD RATE (kb/s)
Notes
1. Maximum in Mode 0.
2. X = don’t care.
3. Maximum in Mode 2.
4. Maximum in Modes 1 and 3.
1997 Mar 14
31
Philips Semiconductors
Product specification
Low voltage 8-bit microcontrollers with
UART and I2C-bus
14.3.2
USING TIMER 2 TO GENERATE BAUD RATES
P83CL781; P83CL782
Where (RCAP2H; RCAP2L) is the content of registers
RCAP2H and RCAP2L taken as a 16-bit unsigned integer.
Timer 2 is selected as a Baud Rate Generator by setting
the RTCLK bit in T2CON. The Baud Rate Generator mode
is similar to the Auto-reload mode, in that a roll-over in TH2
causes Timer 2 registers to be reloaded with the 16-bit
value held in the registers RCAP2H and RCAP2L, which
are preset by software. Baud rates in Modes 1 and 3 are
determined by Timer 2's overflow rate as specified below.
Timer 2 Overflow Rate
Baud Rate = -----------------------------------------------------------16
The Baud Rate Generator mode for Timer 2 is shown in
Fig.15. This figure is only valid if RTCLK = 1. At roll-over
TH2 does not set the TF2 bit in T2CON and therefore, will
not generate an interrupt. Consequently, the Timer 2
interrupt does not need to be disabled when in the Baud
Rate Generator mode. If EXEN2 is set, a HIGH-to-LOW
transition on T2EX will set the EXF2 bit, also in T2CON,
but will not cause a reload from (RCAP2H; RCAP2L) to
(TH2, TL2). Therefore, in this mode T2EX may be used as
an additional external interrupt.
The Timer 2 can be configured for either ‘timer’ or ‘counter’
operation. In the most typical applications, it is configured
for ‘timer’ operation (C/T2 = 0). ‘Timer’ operation is slightly
different for Timer 2 when it is being used as a Baud Rate
Generator. Normally, as a timer it would increment every
machine cycle at a frequency of 1⁄12 × fosc. However, as a
Baud Rate Generator it increments every state time at a
frequency of 1⁄2 × fosc. In this case the baud rate in
Modes 1 and 3 is determined as:
f osc
Baud Rate = ---------------------------------------------------------------------------------------------------32 × { 65536 – ( RCAP2H; RCAP2L ) }
When Timer 2 is operating as a timer (TR2 = 1), in the
Baud Rate Generator mode, registers TH2 and TL2 should
not be accessed (read or write). Under these conditions
the timer is being incremented every state time and
therefore the results of a read or write may not be
accurate. The registers RCAP2H and RCAP2L however,
may be read but not written to. A write might overlap a
reload and cause write and/or reload errors. If a write
operation is required, Timer 2 or RCAP2H/RCAP2L
should first be turned off by clearing the TR2 bit.
TIMER 1
overflow
handbook, full pagewidth
2
(note: divided by 2
not by 12)
OSC
2
0
SMOD
C/T2 = 0
TL2
(8 BITS)
T2 PIN
C/T2 = 1
1
TH2
(8 BITS)
1
0
RTCLK
control
TR2
16
RELOAD
CLK
UART receive/
transmit clock
RCAP2L
transition
detector
T2EX PIN
EXF2
RCAP2H
TIMER 2 interrupt
(additional external interrupt)
control
EXEN2
Fig.15 Timer 2 in Baud Rate Generator mode.
1997 Mar 14
32
MGD622
Philips Semiconductors
Product specification
Low voltage 8-bit microcontrollers with
UART and I2C-bus
handbook, full pagewidth
P83CL781; P83CL782
INTERNAL BUS
write to
SBUF
D S
CL
Q
S0 BUFFER
ZERO DETECTOR
START
S6
RXD
P3.0 ALT
output
function
TX CONTROL
TX CLOCK
SHIFT
SHIFT
SEND
T1
serial port
interrupt
TXD
P3.1 ALT
output
function
SHIFT
CLOCK
R1
RX CLOCK
REN
RI
START
RECEIVE
RX CONTROL
SHIFT
1 1 1 1 1 1 1 0
RXD
P3.0 ALT
input
function
INPUT SHIFT
REGISTER
SHIFT
LOAD
SBUF
S0 BUFFER
READ
SBUF
INTERNAL BUS
MGC752
Fig.16 Serial port Mode 0.
1997 Mar 14
33
34
TXD (SHIFT CLOCK)
SHIFT
RXD (DATA IN)
RECEIVE
RI
TSC (SHIFT CLOCK)
RXD (DATA OUT)
SHIFT
S6P2
D0
S3P1
S6P1
S5P2
D0
WRITE TO SCON (CLEAR R1)
WRITE TO SBUF
D1
D1
D2
D3
D3
D4
D4
D5
D5
D6
D6
D7
D7
MLA567
R
E
C
E
I
V
E
T
R
A
N
S
M
I
T
Low voltage 8-bit microcontrollers with
UART and I2C-bus
Fig.17 Serial port Mode 0 timing.
D2
...s6 s1...s6 s1...s6 s1...s6 s1...s6 s1...s6 s1...s6 s1...s6 s1...s6 s1...s6 s1...s6 s1...s6 s1...s6 s1...s6 s1...s6 s1...s6 s1...s6 s1...s6 s1...s6 s1...s6 s1...s6
handbook, full pagewidth
1997 Mar 14
SEND
ALE
Philips Semiconductors
Product specification
P83CL781; P83CL782
Philips Semiconductors
Product specification
Low voltage 8-bit microcontrollers with
UART and I2C-bus
handbook, full pagewidth
P83CL781; P83CL782
INTERNAL BUS
TB8
Timer 1
overflow
Timer 2
overflow
D S
Q
CL
2
0
SMOD
write to
SBUF
TXD
S0 BUFFER
1
0
1
SHIFT
ZERO DETECTOR
RTCLK
START
16
TX CONTROL
TX CLOCK
SHIFT
DATA
SEND
T1
serial port
interrupt
16
sample
HIGH-TO-LOW
TRANSITION
DETECTOR
RX CLOCK
START
R1
RX CONTROL
LOAD
SBUF
SHIFT
INPUT SHIFT
REGISTER
(9-BITS)
BIT
DETECTOR
RXD
SHIFT
LOAD
SBUF
S0 BUFFER
READ
SBUF
INTERNAL BUS
MGC755
Fig.18 Serial port Mode 1.
1997 Mar 14
35
1997 Mar 14
36
R
E
C
E
I
V
E
RI
SHIFT
BIT DETECTOR SAMPLE TIME
RXD
RX CLOCK
TI
TXD
SHIFT
DATA
START BIT
S1P1
SEND
WRITE TO SBUF
START BIT
÷16 RESET
D0
D0
D2
D1
D2
D3
D4
D3
D4
D5
D5
D6
D7
D6
D7
MLA569
STOP BIT
STOP BIT
T
R
A
N
S
M
I
T
Low voltage 8-bit microcontrollers with
UART and I2C-bus
Fig.19 Serial port Mode 1 timing.
D1
handbook, full pagewidth
TX CLOCK
Philips Semiconductors
Product specification
P83CL781; P83CL782
Philips Semiconductors
Product specification
Low voltage 8-bit microcontrollers with
UART and I2C-bus
handbook, full pagewidth
P83CL781; P83CL782
INTERNAL BUS
TB8
write to
SBUF
phase 2 clock
(fosc / 2)
D S
Q
TXD
S0 BUFFER
CL
2
0
SHIFT
1
ZERO DETECTOR
CSMOD at
PCON.7
STOP BIT
START
16
TX CONTROL
SHIFT
DATA
TX CLOCK
SEND
T1
serial port
interrupt
16
sample
HIGH-TO-LOW
TRANSITION
DETECTOR
RX CLOCK
START
R1
LOAD
SBUF
RX CONTROL
SHIFT
INPUT SHIFT
REGISTER
(9-BITS)
BIT
DETECTOR
SHIFT
RXD
LOAD
SBUF
S0 BUFFER
READ
SBUF
INTERNAL BUS
MGC754
Fig.20 Serial port Mode 2.
1997 Mar 14
37
1997 Mar 14
R
E
C
E
I
V
E
38
SHIFT
RI
SEND
START BIT
S1P1
BIT DETECTOR SAMPLE TIME
RXD
RX CLOCK
STOP BIT GEN
TI
TXD
SHIFT
DATA
D0
START BIT
÷16 RESET
WRITE TO SBUF
D1
D1
D3
D2
D4
D3
D5
D4
D6
D5
D7
D6
TB8
D7
RB8
STOP BIT
MLA571
STOP BIT
T
R
A
N
S
M
I
T
Low voltage 8-bit microcontrollers with
UART and I2C-bus
Fig.21 Serial port Mode 2 timing.
D0
D2
handbook, full pagewidth
TX CLOCK
Philips Semiconductors
Product specification
P83CL781; P83CL782
Philips Semiconductors
Product specification
Low voltage 8-bit microcontrollers with
UART and I2C-bus
handbook, full pagewidth
P83CL781; P83CL782
INTERNAL BUS
TB8
write to
SBUF
Timer 1
overflow
Timer 2
overflow
D S
Q
TXD
S0 BUFFER
CL
2
0
SMOD
1
SHIFT
ZERO DETECTOR
0
1
RTCLK
START
16
TX CONTROL
TX CLOCK
SHIFT
DATA
SEND
T1
serial port
interrupt
16
sample
HIGH-TO-LOW
TRANSITION
DETECTOR
RX CLOCK
START
R1
RX CONTROL
LOAD
SBUF
SHIFT
INPUT SHIFT
REGISTER
(9-BITS)
BIT
DETECTOR
RXD
SHIFT
LOAD
SBUF
S0 BUFFER
READ
SBUF
INTERNAL BUS
MGC753
Fig.22 Serial port Mode 3.
1997 Mar 14
39
1997 Mar 14
40
R
E
C
E
I
V
E
RI
SHIFT
SEND
START BIT
S1P1
BIT DETECTOR SAMPLE TIME
RXD
RX CLOCK
TI
TXD
SHIFT
DATA
WRITE TO SBUF
START BIT
÷16 RESET
D0
D1
D1
D2
D3
D3
D4
D4
D5
D5
D6
D7
D6
TB8
D7
TB8
STOP BIT
MLA573
STOP BIT
T
R
A
N
S
M
I
T
Low voltage 8-bit microcontrollers with
UART and I2C-bus
Fig.23 Serial port Mode 3 timing.
D0
D2
handbook, full pagewidth
TX CLOCK
Philips Semiconductors
Product specification
P83CL781; P83CL782
Philips Semiconductors
Product specification
Low voltage 8-bit microcontrollers with
UART and I2C-bus
P83CL781; P83CL782
15 INTERRUPT SYSTEM
15.2
Interrupt priority
External events and the real-time-driven on-chip
peripherals require service by the CPU at unpredictable
times. To tie the asynchronous activities of these functions
to normal program execution a multiple-source,
two-priority-level, nested interrupt system is provided.
The system is shown in Fig.24. The P83CL78x
acknowledges interrupt requests from fifteen sources as
follows:
Each interrupt source can be set to either a high priority or
to a low priority. If a low priority interrupt is received
simultaneously with a high priority interrupt, the high
priority interrupt will be dealt with first.
If interrupts of the same priority are requested
simultaneously, the processor will branch to the interrupt
polled first, according to the sequence shown in Table 25
and in Fig.24. The ‘vector address’ is the ROM location
where the appropriate interrupt service routine starts.
• INT0 to INT9
• Timer 0, Timer 1 and Timer 2
Table 25 Interrupt vector polling sequence
• I2C-bus serial I/O
• UART.
Each interrupt vectors to a separate location in Program
Memory for its service routine. Each source can be
individually enabled or disabled by its corresponding bit in
the Interrupt Enable Registers (IEN0 and IEN1).
The priority level is selected via the Interrupt Priority
Registers (IP0 and IP1). All enabled sources can be
globally disabled or enabled.
15.1
External interrupts INT2 to INT9
Port 1 lines serve an alternative purpose as eight
additional interrupts INT2 to INT9. When enabled, each of
these lines may wake-up the device from the Power-down
mode. Using the Interrupt Polarity Register (IX1), each pin
may be initialized to be either active HIGH or active LOW.
IRQ1 is the Interrupt Request Flag Register. If the interrupt
is enabled, each flag will be set on an interrupt request but
must be cleared by software, i.e. via the interrupt software
or when the interrupt is disabled.
Port 1 interrupts are level-sensitive. A Port 1 interrupt will
be recognized when a level (HIGH or LOW depending on
the Interrupt Polarity Register) on P1.n is held active for at
least one machine cycle. The interrupt request is not
serviced until the next machine cycle. Figure 25 shows the
external interrupt system.
1997 Mar 14
SYMBOL
VECTOR
ADDRESS (HEX)
X0 (first)
0003
External 0
S1
002B
I2C port
X5
0053
External 5
T0
000B
Timer 0
SOURCE
T2
0033
Timer 2
X6
005B
External 6
X1
0013
External 1
X2
003B
External 2
X7
0063
External 7
T1
001B
Timer 1
X3
0043
External 3
X8
006B
External 8
SO
0023
UART
X4
004B
External 4
X9 (last)
0073
External 9
A low priority interrupt routine can only be interrupted by a
high priority interrupt. A high priority interrupt routine
cannot be interrupted.
41
Philips Semiconductors
Product specification
Low voltage 8-bit microcontrollers with
UART and I2C-bus
INTERRUPT
SOURCES
IEN0/1
P83CL781; P83CL782
IP0/1
PRIORITY
REGISTERS
HIGH
X0
LOW
S1
X5
T0
T2
INTERRUPT POLLING SEQUENCE
X6
X1
X2
X7
T1
X3
X8
S0
X4
X9
GLOBAL
ENABLE
Fig.24 Interrupt system.
1997 Mar 14
42
MLA611
Philips Semiconductors
Product specification
Low voltage 8-bit microcontrollers with
UART and I2C-bus
P83CL781; P83CL782
IX1
handbook, full pagewidth
IEN1
IRQ1
P1.7
X9
P1.6
X8
P1.5
X7
P1.4
X6
P1.3
X5
P1.2
X4
P1.1
X3
P1.0
X2
MLA575
WAKE-UP
Fig.25 External interrupt configuration.
15.3
Interrupt registers
The registers used in the interrupt system are listed in Table 26. Tables 27 to 38 describe the contents of these registers.
Table 26 Special Function Registers related to the interrupt system
ADDRESS
REGISTER
DESCRIPTION
A8H
IEN0
Interrupt Enable Register
E8H
IEN1
Interrupt Enable Register (INT2 to INT9)
B8H
IP0
Interrupt Priority Register
F8H
IP1
Interrupt Priority Register (INT2 to INT9)
E9H
IX1
Interrupt Polarity Register
C0H
IRQ1
1997 Mar 14
Interrupt Request Flag Register
43
Philips Semiconductors
Product specification
Low voltage 8-bit microcontrollers with
UART and I2C-bus
15.3.1
P83CL781; P83CL782
INTERRUPT ENABLE REGISTER (IEN0)
Bit values: 0 = interrupt disabled; 1 = interrupt enabled.
Table 27 Interrupt Enable Register (SFR address A8H)
7
6
5
4
3
2
1
0
EA
ET2
ES1
ES0
ET1
EX1
ET0
EX0
Table 28 Description of IEN0 bits
BIT
SYMBOL
7
EA
DESCRIPTION
General enable/disable control. If EA = 0, no interrupt is enabled. If EA = 1, any
individually enabled interrupt will be accepted.
6
ET2
enable T2 interrupt
5
ES1
enable I2C interrupt
4
ES0
enable UART SIO interrupt
3
ET1
enable Timer 1 interrupt (T1)
2
EX1
enable external interrupt 1
1
ET0
enable Timer 0 interrupt (T0)
0
EX0
enable external interrupt 0
15.3.2
INTERRUPT ENABLE REGISTER (IEN1)
Bit values: 0 = interrupt disabled; 1 = interrupt enabled.
Table 29 Interrupt Enable Register (SFR address E8H)
7
6
5
4
3
2
1
0
EX9
EX8
EX7
EX6
EX5
EX4
EX3
EX2
Table 30 Description of IEN1 bits
BIT
SYMBOL
7
EX9
enable external interrupt 9
6
EX8
enable external interrupt 8
5
EX7
enable external interrupt 7
4
EX7
enable external interrupt 6
3
EX5
enable external interrupt 5
2
EX4
enable external interrupt 4
1
EX3
enable external interrupt 3
0
EX2
enable external interrupt 2
1997 Mar 14
DESCRIPTION
44
Philips Semiconductors
Product specification
Low voltage 8-bit microcontrollers with
UART and I2C-bus
15.3.3
P83CL781; P83CL782
INTERRUPT PRIORITY REGISTER (IP0)
Bit values: 0 = low priority; 1 = high priority.
Table 31 Interrupt Priority Register (SFR address B8H)
7
6
5
4
3
2
1
0
−
PT2
PS1
PS0
PT1
PX1
PT0
PX0
Table 32 Description of IP0 bits
BIT
SYMBOL
7
−
DESCRIPTION
reserved
6
PT2
Timer 2 interrupt priority level
5
PS1
I2C interrupt priority level
4
PS0
UART SIO interrupt priority level
3
PT1
Timer 1 interrupt priority level
2
PX1
external interrupt 1 priority level
1
PT0
Timer 0 interrupt priority level
0
PX0
external interrupt 0 priority level
15.3.4
INTERRUPT PRIORITY REGISTER (IP1)
Bit values: 0 = low priority; 1 = high priority.
Table 33 Interrupt Priority Register (SFR address F8H)
7
6
5
4
3
2
1
0
PX9
PX8
PX7
PX6
PX5
PX4
PX3
PX2
Table 34 Description of IP1 bits
BIT
SYMBOL
7
PX9
external interrupt 9 priority level
6
PX8
external interrupt 8 priority level
5
PX7
external interrupt 7 priority level
4
PX6
external interrupt 6 priority level
3
PX5
external interrupt 5 priority level
2
PX4
external interrupt 4 priority level
1
PX3
external interrupt 3 priority level
0
PX2
external interrupt 2 priority level
1997 Mar 14
DESCRIPTION
45
Philips Semiconductors
Product specification
Low voltage 8-bit microcontrollers with
UART and I2C-bus
15.3.5
P83CL781; P83CL782
INTERRUPT POLARITY REGISTER (IX1)
Writing either a logic 1 or logic 0 to any Interrupt Polarity Register bit sets the polarity level of the corresponding external
interrupt to an active HIGH or active LOW respectively.
Table 35 Interrupt Polarity Register (SFR address E9H)
7
6
5
4
3
2
1
0
IL9
IL8
IL7
IL6
IL5
IL4
IL3
IL2
Table 36 Description of IX1 bits
BIT
SYMBOL
7
IL9
external interrupt 9 polarity level
6
IL8
external interrupt 8 polarity level
5
IL7
external interrupt 7 polarity level
4
IL6
external interrupt 6 polarity level
3
IL5
external interrupt 5 polarity level
2
IL4
external interrupt 4 polarity level
1
IL3
external interrupt 3 polarity level
0
IL2
external interrupt 2 polarity level
15.3.6
DESCRIPTION
INTERRUPT REQUEST FLAG REGISTER (IRQ1)
Table 37 Interrupt Request Flag Register (SFR address C0H)
7
6
5
4
3
2
1
0
IQ9
IQ8
IQ7
IQ6
IQ5
IQ4
IQ3
IQ2
Table 38 Description of IRQ1 bits
BIT
SYMBOL
7
IQ9
external interrupt 9 request flag
6
IQ8
external interrupt 8 request flag
5
IQ7
external interrupt 7 request flag
4
IQ6
external interrupt 6 request flag
3
IQ5
external interrupt 5 request flag
2
IQ4
external interrupt 4 request flag
1
IQ3
external interrupt 3 request flag
0
IQ2
external interrupt 2 request flag
1997 Mar 14
DESCRIPTION
46
Philips Semiconductors
Product specification
Low voltage 8-bit microcontrollers with
UART and I2C-bus
P83CL781; P83CL782
To drive the device with an external clock source, apply the
external clock signal to XTAL1, and leave XTAL2 to float,
as shown in Fig.26(f). There are no requirements on the
duty cycle of the external clock, since the input to the
internal clocking circuitry is buffered by a flip-flop.
16 OSCILLATOR CIRCUITRY
The on-chip oscillator circuitry of the P8xCL580 is a
single-stage inverting amplifier biased by an internal
feedback resistor. The oscillator circuit is shown in Fig.26.
For operation as a standard quartz oscillator, no external
components are needed, except for the 32 kHz option.
When using external capacitors, ceramic resonators, coils
and RC networks to drive the oscillator, five different
configurations are supported (see Table 39 and Fig.26).
Various oscillator options are provided for optimum
on-chip oscillator performance; these are specified in
Table 40 and shown in Fig.26. The required option should
be stated when ordering.
In the Power-down mode the oscillator is stopped and
XTAL1 is pulled HIGH. The oscillator inverter is switched
off to ensure no current will flow regardless of the voltage
at XTAL1, for configurations (a), (b), (c), (d), (e) and (g) of
Fig.26.
Table 39 Oscillator options
OPTION
APPLICATION
Oscillator 1
For 32 kHz clock applications with external trimmer for frequency adjustment. A 4.7 MΩ bias resistor
is needed for use in parallel with the crystal; see Fig.26(c).
Oscillator 2
Low-power, low-frequency operations using LC components; see Fig.26(e).
Oscillator 3
Medium frequency range applications.
Oscillator 4
High frequency range applications.
RC oscillator
RC oscillator configuration; see Figs 26(g) and 28.
QUARTZ OSCILLATOR
WITH EXTERNAL
CAPACITORS
STANDARD
QUARTZ
OSCILLATOR
handbook, full pagewidth
XTAL1
XTAL2
XTAL1
(a)
CERAMIC
RESONATOR
XTAL1
XTAL2
XTAL1
(b)
LC - OSCILLATOR
XTAL2
32 kHz
OSCILLATOR
XTAL1
(c)
EXTERNAL CLOCK
XTAL2
XTAL2
XTAL1
XTAL2
n.c.
RC - OSCILLATOR
XTAL1
XTAL2
n.c.
VDD
(d)
(e)
(f)
Fig.26 Oscillator configurations.
1997 Mar 14
47
(g)
MLA577
Philips Semiconductors
Product specification
Low voltage 8-bit microcontrollers with
UART and I2C-bus
P83CL781; P83CL782
VDD
to internal
timing circuits
P83CL781
P83CL782
VDD
PD
C1 i
VDD
C2 i
R bias
XTAL1
XTAL2
MLA613
Fig.27 Standard oscillator.
MLA579
600
handbook, halfpage
f osc
(kHz)
400
200
0
0
2
4
RC (µs)
6
RC oscillator frequency is externally adjustable; 100 kHz ≤ fosc ≤ 500 kHz.
Fig.28 RC oscillator; frequency as a function of RC.
1997 Mar 14
48
Philips Semiconductors
Product specification
Low voltage 8-bit microcontrollers with
UART and I2C-bus
P83CL781; P83CL782
Table 40 Oscillator type selection guide
RESONATOR
Quartz
FREQUENCY
(MHz)
0.032
OPTION
(see Table 39)
MIN.
MAX.
MIN.
MAX.
Oscillator 1
0
0
5
15
15 kΩ; note 1
0
30
0
30
600 Ω
Oscillator 2
0
15
0
15
100 Ω
0
20
0
20
75 Ω
0
10
0
10
60 Ω
0
15
0
15
60 Ω
0
10
0
10
40Ω
4.0
6.0
Oscillator 3
10.0
12.0
Oscillator 4
0
15
0
15
20 Ω
0.455
40
50
40
50
10 Ω
1.0
15
50
15
50
100 Ω
0
40
0
40
10 Ω
4.0
0
40
0
40
10 Ω
6.0
0
20
0
20
5Ω
0
15
0
15
6Ω
16.0
PXE
3.58
10.0
12.0
LC
C2 EXT. (pF)
RESONATOR MAX.
SERIES RESISTANCE
1.0
3.58
C1 EXT. (pF)
Oscillator 2
Oscillator 3
Oscillator 4
10
40
10
40
6Ω
Oscillator 2
20
90
20
90
10 µH = 1 Ω
100 µH = 5 Ω
1 mH = 75 Ω
Note
1. 32 kHz quartz crystals with a series resistance >15 kΩ will reduce the guaranteed supply voltage range to
2.5 to 3.5 V.
1997 Mar 14
49
Philips Semiconductors
Product specification
Low voltage 8-bit microcontrollers with
UART and I2C-bus
P83CL781; P83CL782
Rf
handbook, full pagewidth
XTAL1
XTAL2
C1 i
V1
gm
R2
C2 i
MLA578
Fig.29 Oscillator equivalent circuit diagram.
Table 41 Oscillator equivalent circuit parameters
The equivalent circuit data of the internal oscillator compares with that of matched crystals.
SYMBOL
gm
PARAMETER
transconductance
OPTION
CONDITION
Tamb = +25 °C;
VDD = 4.5 V
C2i
R2
1997 Mar 14
input capacitance
output capacitance
output resistance
TYP.
MAX.
UNIT
−
15
−
µS
200
600
1000
µS
Oscillator 3
400
1500
4000
µS
Oscillator 4
1000
4000
10000
µS
Oscillator 1; 32 kHz
−
3.0
−
pF
Oscillator 2
−
8.0
−
pF
Oscillator 3
−
8.0
−
pF
Oscillator 4
−
8.0
−
pF
Oscillator 1; 32 kHz
−
23
−
pF
Oscillator 2
−
8.0
−
pF
Oscillator 3
−
8.0
−
pF
Oscillator 4
−
8.0
−
pF
Oscillator 1; 32 kHz
Oscillator 2
C1i
MIN.
Oscillator 1; 32 kHz
−
3800
−
kΩ
Oscillator 2
−
65
−
kΩ
Oscillator 3
−
18
−
kΩ
Oscillator 4
−
5.0
−
kΩ
50
Philips Semiconductors
Product specification
Low voltage 8-bit microcontrollers with
UART and I2C-bus
P83CL781; P83CL782
17 RESET
17.2
To initialize the P83CL78x a reset is performed by either of
two methods:
The device contains on-chip circuitry which switches the
port pins to the customer defined logic level as soon as
VDD exceeds 1.3 V; if the mask option ‘ON’ has been
chosen. As soon as the minimum supply voltage is
reached, the oscillator will start up. However, to ensure
that the oscillator is stable before the controller starts, the
clock signals are gated away from the CPU for a further
1536 oscillator periods. A hysteresis of approximately
50 mV at a typical power-on switching level of 1.3 V will
ensure correct operation. See Fig.32.
• Applying an external signal to the RST pin
• Via Power-on reset circuitry.
The reset state of the port pins is mask-programmable and
can be defined by the user. The standard reset value for
Ports 0 to 3 is FFH. A reset leaves the internal registers as
shown in Chapter 18.
17.1
External reset using the RST pin
Power-on reset
The on-chip Power-on reset circuitry can also be switched
off via the mask option ‘OFF’. This option reduces the
Power-down current to typically 800 nA and can be
chosen if external reset circuitry is used. For applications
not requiring the internal reset, option ‘OFF’ should be
chosen.
The reset input for the P83CL78x is RST. A Schmitt trigger
is used at the input for noise rejection. The output of the
Schmitt trigger is sampled by the reset circuitry every
machine cycle. A reset is accomplished by holding the
RST pin HIGH for at least two machine cycles
(24 oscillator periods) while the oscillator is running.
The CPU responds by executing an internal reset. Port
pins adopt their reset state immediately after the RST goes
HIGH. During reset, ALE and PSEN are held HIGH.
An automatic reset can be obtained by connecting the RST
pin to VDD via a 10 µF capacitor. At power-on, the voltage
on the RST pin is equal to VDD minus the capacitor voltage,
and decreases from VDD as the capacitor charges through
the internal resistor (RRST) to ground. The larger the
capacitor, the more slowly VRST decreases. VRST must
remain above the lower threshold of the Schmitt trigger
long enough to effect a complete reset. The time required
is the oscillator start-up time, plus 2 machine cycles.
The Power-on reset circuitry is shown in Fig.31.
The external reset is asynchronous to the internal clock.
The RST pin is sampled during state 5, phase 2 of every
machine cycle. After a HIGH is detected at the RST pin, an
internal reset is repeated until RST goes LOW.
The internal RAM is not affected by reset. When VDD is
turned on, the RAM contents are indeterminate.
VDD
handbook, halfpage
RST
V
DD
10 µF
SCHMITT
TRIGGER
P83CL781
P83CL782
RESET
CIRCUITRY
RST
MLA580
R RST
MLA612
Fig.30 Reset configuration.
1997 Mar 14
Fig.31 Power-on reset circuitry.
51
Philips Semiconductors
Product specification
Low voltage 8-bit microcontrollers with
UART and I2C-bus
P83CL781; P83CL782
switching level
POR
handbook, full pagewidth
SUPPLY
hysteresis
VOLTAGE
POWER-ON-RESET
(INTERNAL)
OSCILLATOR
CPU RUNNING
MLA581
Start-up
time
1536 oscillator
periods delay
Fig.32 Power-on reset switching level.
1997 Mar 14
52
Philips Semiconductors
Product specification
Low voltage 8-bit microcontrollers with
UART and I2C-bus
P83CL781; P83CL782
18 SPECIAL FUNCTION REGISTERS OVERVIEW
The P83CL78x has 34 SFRs available to the user.
ADDRESS
(HEX)
NAME
RESET VALUE
(B)
FUNCTION
F8
IP1(1)
00000000
Interrupt Priority Register (INT2 to INT9)
F0
B(1)
00000000
B Register
E9
IX1
00000000
Interrupt Polarity Register
E8
IEN1(1)
00000000
Interrupt Enable Register 1
E0
ACC(1)
00000000
Accumulator
DB
S1ADR
00000000
I2C-bus Slave Address Register
DA
S1DAT
00000000
I2C-bus Data Shift Register
D9
S1STA
11111000
I2C-bus Serial Status Register
D8
S1CON(1)
00000000
I2C-bus Serial Control Register
D0
PSW(1)
00000000
Program Status Word
CD
TH2
00000000
Timer 2 High byte
CC
TL2
00000000
Timer 2 Low byte
CB
RCAP2H
00000000
Timer 2 Reload/Capture Register High byte
CA
RCAP2L
00000000
Timer 2 Reload/Capture Register Low byte
C8
T2CON(1)
00000000
Timer/Counter 2 Control Register
C0
IRQ1(1)
00000000
Interrupt Request Flag Register
B8
IP0(1)
X0000000
Interrupt Priority Register 0
B0
P3(1)
XXXXXXXX(2)
Digital I/O Port Register 3
A8
IEN0(1)
00000000
Interrupt Enable Register
A0
P2(1)
XXXXXXXX(2)
Digital I/O Port Register 2
99
S0BUF
XXXXXXXX
Serial Data Buffer Register 0
98
S0CON(1)
00000000
Serial Port Control Register 0
90
P1(1)
XXXXXXXX(2)
8D
TH1
00000000
Timer 1 High byte
8C
TH0
00000000
Timer 0 High byte
8B
TL1
00000000
Timer 1 Low byte
Digital I/O Port Register 1
8A
TL0
00000000
Timer 0 Low byte
89
TMOD
00000000
Timer 0 and 1 Mode Control Register
88
TCON(1)
00000000
Timer 0 and 1 Control/External Interrupt Control Register
87
PCON
0XX00000
Power Control Register
83
DPH
00000000
Data Pointer High byte
82
DPL
00000000
Data Pointer Low byte
81
SP
80
P0(1)
00000111
XXXXXXXX(2)
Stack Pointer
Digital I/O Port Register 0
Notes
1. Bit addressable register.
2. Port reset state determined by the customer.
1997 Mar 14
53
Philips Semiconductors
Product specification
Low voltage 8-bit microcontrollers with
UART and I2C-bus
P83CL781; P83CL782
19 INSTRUCTION SET
The P83CL78x uses a powerful instruction set which permits the expansion of on-chip CPU peripherals and optimizes
byte efficiency and execution speed. Assigned opcodes add new high-power operation and permit new addressing
modes. The instruction set consists of 49 single-byte, 46 two-byte and 16 three-byte instructions. When using a 12 MHz
oscillator, 64 instructions execute in 1 µs and 45 instructions execute in 2 µs. Multiply and divide instructions execute in
4 µs.
For the description of the Data Addressing modes and Hexadecimal opcode cross-reference see Table 46.
Table 42 Instruction set description: Arithmetic operations
MNEMONIC
DESCRIPTION
BYTES
CYCLES
OPCODE
(HEX)
Arithmetic operations
ADD
A,Rr
Add register to A
1
1
2*
ADD
A,direct
Add direct byte to A
2
1
25
ADD
A,@Ri
Add indirect RAM to A
1
1
26, 27
ADD
A,#data
Add immediate data to A
2
1
24
ADDC
A,Rr
Add register to A with carry flag
1
1
3*
ADDC
A,direct
Add direct byte to A with carry flag
2
1
35
ADDC
A,@Ri
Add indirect RAM to A with carry flag
1
1
36, 37
ADDC
A,#data
Add immediate data to A with carry flag
2
1
34
SUBB
A,Rr
Subtract register from A with borrow
1
1
9*
SUBB
A,direct
Subtract direct byte from A with borrow
2
1
95
SUBB
A,@Ri
Subtract indirect RAM from A with borrow
1
1
96, 97
SUBB
A,#data
Subtract immediate data from A with borrow
2
1
94
INC
A
Increment A
1
1
04
INC
Rr
Increment register
1
1
0*
INC
direct
Increment direct byte
2
1
05
INC
@Ri
Increment indirect RAM
1
1
06, 07
DEC
A
Decrement A
1
1
14
DEC
Rr
Decrement register
1
1
1*
DEC
direct
Decrement direct byte
2
1
15
DEC
@Ri
Decrement indirect RAM
1
1
16, 17
INC
DPTR
Increment data pointer
1
2
A3
MUL
AB
Multiply A and B
1
4
A4
DIV
AB
Divide A by B
1
4
84
DA
A
Decimal adjust A
1
1
D4
1997 Mar 14
54
Philips Semiconductors
Product specification
Low voltage 8-bit microcontrollers with
UART and I2C-bus
P83CL781; P83CL782
Table 43 Instruction set description: Logic operations
MNEMONIC
DESCRIPTION
BYTES
CYCLES
OPCODE
(HEX)
Logic operations
ANL
A,Rr
AND register to A
1
1
5*
ANL
A,direct
AND direct byte to A
2
1
55
ANL
A,@Ri
AND indirect RAM to A
1
1
56, 57
ANL
A,#data
AND immediate data to A
2
1
54
ANL
direct,A
AND A to direct byte
2
1
52
ANL
direct,#data
AND immediate data to direct byte
3
2
53
ORL
A,Rr
OR register to A
1
1
4*
ORL
A,direct
OR direct byte to A
2
1
45
ORL
A,@Ri
OR indirect RAM to A
1
1
46, 47
ORL
A,#data
OR immediate data to A
2
1
44
ORL
direct,A
OR A to direct byte
2
1
42
ORL
direct,#data
OR immediate data to direct byte
3
2
43
XRL
A,Rr
Exclusive-OR register to A
1
1
6*
XRL
A,direct
Exclusive-OR direct byte to A
2
1
65
XRL
A,@Ri
Exclusive-OR indirect RAM to A
1
1
66, 67
XRL
A,#data
Exclusive-OR immediate data to A
2
1
64
XRL
direct,A
Exclusive-OR A to direct byte
2
1
62
XRL
direct,#data
Exclusive-OR immediate data to direct byte
3
2
63
CLR
A
Clear A
1
1
E4
CPL
A
Complement A
1
1
F4
RL
A
Rotate A left
1
1
23
RLC
A
Rotate A left through the carry flag
1
1
33
RR
A
Rotate A right
1
1
03
RRC
A
Rotate A right through the carry flag
1
1
13
SWAP
A
Swap nibbles within A
1
1
C4
1997 Mar 14
55
Philips Semiconductors
Product specification
Low voltage 8-bit microcontrollers with
UART and I2C-bus
P83CL781; P83CL782
Table 44 Instruction set description: Data transfer
MNEMONIC
DESCRIPTION
BYTES
CYCLES
1
1
OPCODE
(HEX)
Data transfer
MOV
A,Rr
Move register to A
MOV
A,direct (note 1) Move direct byte to A
2
1
E5
MOV
A,@Ri
Move indirect RAM to A
1
1
E6, E7
MOV
A,#data
Move immediate data to A
2
1
74
MOV
Rr,A
Move A to register
1
1
F*
MOV
Rr,direct
Move direct byte to register
2
2
A*
MOV
Rr,#data
Move immediate data to register
2
1
7*
MOV
direct,A
Move A to direct byte
2
1
F5
MOV
direct,Rr
Move register to direct byte
2
2
8*
MOV
direct,direct
Move direct byte to direct
3
2
85
MOV
direct,@Ri
Move indirect RAM to direct byte
2
2
86, 87
MOV
direct,#data
Move immediate data to direct byte
3
2
75
MOV
@Ri,A
Move A to indirect RAM
1
1
F6, F7
MOV
@Ri,direct
Move direct byte to indirect RAM
2
2
A6, A7
MOV
@Ri,#data
Move immediate data to indirect RAM
2
1
76, 77
MOV
DPTR,#data 16 Load data pointer with a 16-bit constant
3
2
90
MOVC
A,@A+DPTR
Move code byte relative to DPTR to A
1
2
93
MOVC
A,@A+PC
Move code byte relative to PC to A
1
2
83
MOVX
A,@Ri
Move external RAM (8-bit address) to A
1
2
E2, E3
MOVX
A,@DPTR
Move external RAM (16-bit address) to A
1
2
E0
MOVX
@Ri,A
Move A to external RAM (8-bit address)
1
2
F2, F3
MOVX
@DPTR,A
Move A to external RAM (16-bit address)
1
2
F0
PUSH
direct
Push direct byte onto stack
2
2
C0
POP
direct
Pop direct byte from stack
2
2
D0
XCH
A,Rr
Exchange register with A
1
1
C*
XCH
A,direct
Exchange direct byte with A
2
1
C5
XCH
A,@Ri
Exchange indirect RAM with A
1
1
C6, C7
XCHD
A,@Ri
Exchange LOW-order digit indirect RAM with A
1
1
D6, D7
Note
1. MOV A,ACC is not permitted.
1997 Mar 14
56
E*
Philips Semiconductors
Product specification
Low voltage 8-bit microcontrollers with
UART and I2C-bus
P83CL781; P83CL782
Table 45 Instruction set description: Boolean variable manipulation, Program and machine control
MNEMONIC
DESCRIPTION
BYTES
CYCLES
OPCODE
(HEX)
Boolean variable manipulation
CLR
C
Clear carry flag
1
1
C3
CLR
bit
Clear direct bit
2
1
C2
SETB
C
Set carry flag
1
1
D3
SETB
bit
Set direct bit
2
1
D2
CPL
C
Complement carry flag
1
1
B3
CPL
bit
Complement direct bit
2
1
B2
ANL
C,bit
AND direct bit to carry flag
2
2
82
ANL
C,/bit
AND complement of direct bit to carry flag
2
2
B0
ORL
C,bit
OR direct bit to carry flag
2
2
72
ORL
C,/bit
OR complement of direct bit to carry flag
2
2
A0
MOV
C,bit
Move direct bit to carry flag
2
1
A2
MOV
bit,C
Move carry flag to direct bit
2
2
92
Program and machine control
ACALL
addr11
Absolute subroutine call
2
2
•1
LCALL
addr16
Long subroutine call
3
2
12
RET
Return from subroutine
1
2
22
RETI
Return from interrupt
1
2
32
AJMP
addr11
Absolute jump
2
2
♦1
LJMP
addr16
Long jump
3
2
02
SJMP
rel
Short jump (relative address)
2
2
80
JMP
@A+DPTR
Jump indirect relative to the DPTR
1
2
73
JZ
rel
Jump if A is zero
2
2
60
JNZ
rel
Jump if A is not zero
2
2
70
JC
rel
Jump if carry flag is set
2
2
40
JNC
rel
Jump if carry flag is not set
2
2
50
JB
bit,rel
Jump if direct bit is set
3
2
20
JNB
bit,rel
Jump if direct bit is not set
3
2
30
JBC
bit,rel
Jump if direct bit is set and clear bit
3
2
10
CJNE
A,direct,rel
Compare direct to A and jump if not equal
3
2
B5
CJNE
A,#data,rel
Compare immediate to A and jump if not equal
3
2
B4
CJNE
Rr,#data,rel
Compare immediate to register and jump if not equal
3
2
B*
CJNE
@Ri,#data,rel Compare immediate to indirect and jump if not equal
3
2
B6, B7
DJNZ
Rr,rel
Decrement register and jump if not zero
2
2
D*
DJNZ
direct,rel
Decrement direct and jump if not zero
3
2
D5
No operation
1
1
00
NOP
1997 Mar 14
57
Philips Semiconductors
Product specification
Low voltage 8-bit microcontrollers with
UART and I2C-bus
P83CL781; P83CL782
Table 46 Description of the mnemonics in the Instruction set
MNEMONIC
DESCRIPTION
Data addressing modes
Rr
Working register R0-R7.
direct
128 internal RAM locations and any special function register (SFR).
@Ri
Indirect internal RAM location addressed by register R0 or R1 of the actual register bank.
#data
8-bit constant included in instruction.
#data 16
16-bit constant included as bytes 2 and 3 of instruction.
bit
Direct addressed bit in internal RAM or SFR.
addr16
16-bit destination address. Used by LCALL and LJMP.
The branch will be anywhere within the 64 kbytes Program Memory address space.
addr11
111-bit destination address. Used by ACALL and AJMP. The branch will be within the same 2 kbytes
page of Program Memory as the first byte of the following instruction.
rel
Signed (two's complement) 8-bit offset byte. Used by SJMP and all conditional jumps.
Range is −128 to +127 bytes relative to first byte of the following instruction.
Hexadecimal opcode cross-reference
*
8, 9, A, B, C, D, E, F.
•
1, 3, 5, 7, 9, B, D, F.
♦
0, 2, 4, 6, 8, A, C, E.
1997 Mar 14
58
1997 Mar 14
59
ACALL
addr11
MOVX
@DTPR,A
3
RR
A
RRC
A
RL
A
RLC
A
ORL
ORL
direct,A
direct,#data
ANL
ANL
direct,A
direct,#data
XRL
XRL
direct,A
direct,#data
ORL
JMP
C,bit
@A+DPTR
ANL
MOVC
C,bit
A,@A+PC
MOV
MOVC
bit,C
A,@A+DPTR
MOV
INC
bit,C
DPTR
CPL
CPL
bit
C
CLR
CLR
bit
C
SETB
SETB
bit
C
MOVX A,@Ri
0
1
MOVX @Ri,A
0
1
1. MOV A, ACC is not a valid instruction.
Note
F
E
D
C
AJMP
addr11
ACALL
addr11
AJMP
addr11
ACALL
addr11
AJMP
addr11
ACALL
addr11
AJMP
addr11
ACALL
addr11
AJMP
addr11
ACALL
addr11
AJMP
addr11
JC
rel
JNC
rel
JZ
rel
JNZ
rel
SJMP
rel
MOV
DTPR,#data16
ORL
C,/bit
ANL
C,/bit
PUSH
direct
POP
direct
MOVX
A,@DTPR
RETI
RET
2
LJMP
addr16
LCALL
addr16
CPL
A
ORL
A,#data
ANL
A,#data
XRL
A,#data
MOV
A,#data
DIV
AB
SUBB
A,#data
MUL
AB
CJNE
A,#data,rel
SWAP
A
DA
A
CLR
A
4
INC
A
DEC
A
ADD
A,#data
ADDC
A,#data
MOV
direct,A
CJNE
A,direct,rel
XCH
A,direct
DJNZ
direct,rel
MOV
A,direct (1)
ORL
A,direct
ANL
A,direct
XRL
A,direct
MOV
direct,#data
MOV
direct,direct
SUBB
A,direct
5
INC
direct
DEC
direct
ADD
A,direct
ADDC
A,direct
DEC @Ri
INC @Ri
1
7
0
1
ADD A,@Ri
0
1
ADDC A,@Ri
0
1
ORL A,@Ri
0
1
ANL A,@Ri
0
1
XRL A,@Ri
0
1
MOV @Ri,#data
0
1
MOV direct,@Ri
0
1
SUBB A,@Ri
0
1
MOV @Ri,direct
0
1
CJNE @Ri,#data,rel
0
1
XCH A,@Ri
0
1
XCHD A,@Ri
0
1
MOV A,@Ri
0
1
MOV @Ri,A
0
1
0
6
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
8
← Second hexadecimal character of opcode →
9 A B C D E
INC Rr
1 2 3 4 5 6
DEC Rr
1 2 3 4 5 6
ADD A,Rr
1 2 3 4 5 6
ADDC A,Rr
1 2 3 4 5 6
ORL A,Rr
1 2 3 4 5 6
ANL A,Rr
1 2 3 4 5 6
XRL A,Rr
1 2 3 4 5 6
MOV Rr,#data
1 2 3 4 5 6
MOV direct,Rr
1 2 3 4 5 6
SUB A,Rr
1 2 3 4 5 6
MOV Rr,direct
1 2 3 4 5 6
CJNE Rr,#data,rel
1 2 3 4 5 6
XCH A,Rr
1 2 3 4 5 6
DJNZ Rr,rel
1 2 3 4 5 6
MOV A,Rr
1 2 3 4 5 6
MOV Rr,A
1 2 3 4 5 6
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
F
Low voltage 8-bit microcontrollers with
UART and I2C-bus
B
A
9
8
7
6
5
4
3
2
1
JBC
bit,rel
JB
bit,rel
JNB
bit,rel
NOP
0
1
AJMP
addr11
ACALL
addr11
AJMP
addr11
ACALL
addr11
0
↓
First hexadecimal character of opcode
Table 47 Instruction map
Philips Semiconductors
Product specification
P83CL781; P83CL782
Philips Semiconductors
Product specification
Low voltage 8-bit microcontrollers with
UART and I2C-bus
P83CL781; P83CL782
20 LIMITING VALUES
In accordance with the Absolute Maximum Rating System (IEC 134)
SYMBOL
PARAMETER
MIN.
MAX.
UNIT
VDD
supply voltage
−0.5
+6.5
VI
input voltage on any pin with respect to ground (VSS)
−0.5
VDD + 0.5 V
II
DC current on any input
−5.0
+5.0
mA
IO
DC current on any output
−5.0
+5.0
mA
Ptot
total power dissipation
−
300
mW
Tstg
storage temperature
−65
+150
°C
Tamb
operating ambient temperature - P83CL781
−40
+85
°C
operating ambient temperature - P83CL782
−25
+55
°C
operating junction temperature
−
+125
°C
Tj
V
21 DC CHARACTERISTICS
The DC characteristics apply to both the P83CL781 and the P83CL782 unless otherwise stated. VDD = 1.8 to 6 V;
VSS = 0 V; Tamb = −40 to +85 °C for the P83CL781 and −25 to +55 °C for the P83CL782; all voltages with respect to
VSS unless otherwise specified. See notes 1, 2 and 3.
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
Supply
VDD
supply voltage
1.8
−
6.0
V
VDD
RAM retention voltage in
Power-down mode
1.0
−
6.0
V
IDD
supply current operating;
P83CL781
IDD(idle)
IDD(pd)
1997 Mar 14
VDD = 5 V; fCLK = 12 MHz; note 4
−
17
25
mA
VDD = 3 V; fCLK = 3.58 MHz; note 4
−
2.4
5
mA
supply current operating;
P83CL782
VDD = 3.1 V; fCLK = 12 MHz; note 4
−
8.4
12
mA
VDD = 3 V; fCLK = 3.58 MHz; note 4
−
2.4
5
µA
supply current Idle mode;
P83CL781
VDD = 5 V; fCLK = 12 MHz; note 5
−
5.1
12
mA
VDD = 3 V; fCLK = 3.58 MHz; note 5
−
0.75
3
mA
supply current Idle mode;
P83CL782
VDD = 5 V; fCLK = 12 MHz; note 5
−
2.7
5
mA
VDD = 3 V; fCLK = 3.58 MHz; note 5
−
0.75
3
mA
supply current Power-down
mode
VDD = 1.8 V; Tamb = 25 °C; note 6
−
−
10
µA
60
Philips Semiconductors
Product specification
Low voltage 8-bit microcontrollers with
UART and I2C-bus
SYMBOL
PARAMETER
CONDITIONS
P83CL781; P83CL782
MIN.
TYP.
MAX.
UNIT
Inputs
−
VIL
LOW level input voltage
note 7
VSS
VIH
HIGH level input voltage
note 7
0.7VDD −
IIL
LOW level input current
0.3VDD V
VDD
V
VDD = 5 V; VIN = 0.4 V; note 7
−
−
−100
µA
VDD = 2.5 V; VIN = 0.4 V; note 7
−
−
−50
µA
−
−
−1.0
mA
IIL(T)
LOW level input current
(HIGH-to-LOW transition)
VDD = 5 V; VIN = 0.5VDD; note 7
VDD = 2.5 V; VIN = 0.5VDD; note 7
−
−
−500
µA
ILI
input leakage current
VSS < VI < VDD; note 7
−
−
±10
µA
LOW level output current;
except SDA and SCL
VDD = 5 V; VOL = 0.4 V
1.6
−
−
mA
VDD = 2.5 V; VOL = 0.4 V
0.7
−
−
mA
3.0
−
−
mA
Outputs
IOL
IOL1
LOW level output current; SDA
and SCL
VDD = 5 V; VOL = 0.4 V
IOH
HIGH level output current
(push-pull options only)
VDD = 5 V; VOH = VDD − 0.4 V
−1.6
−
−
mA
VDD = 2.5 V; VOH = VDD − 0.4 V
−0.7
−
−
mA
10
−
200
kΩ
RRST
RST pull-down resistor
Notes
1. Capacitive loading on Ports 0 and 2 may cause spurious noise pulses to be superimposed on the LOW level output
voltage of ALE, Port 1 and Port 3 pins when these make a HIGH-to-LOW transition during bus operations. The noise
is due to external bus capacitance discharging into the Port 0 and Port 2 pins when these pins make HIGH-to-LOW
transitions during bus operations. In the most adverse conditions (capacitive loading >100 pF), the noise pulse on
the ALE line may exceed 0.8 V. In such events it may be required to qualify ALE with a Schmitt trigger, or use an
address latch with a Schmitt trigger strobe input.
2. Capacitive loading on Ports 0 and 2 may cause the HIGH level output voltage on ALE and PSEN to momentarily fall
below the 0.9% of VDD specification when the address bits are stabilizing.
3. Circuits with Power-on reset option ‘OFF’ are tested at VDDmin = 1.8 V; with the ‘ON’ option (typically 1.3 V) they are
tested at VDDmin = 2.3 V.
4. The operating supply current is measured with all output pins disconnected; XTAL1 driven with tr = tf =10 ns;
VIL = VSS; VIH = VDD; XTAL2 not connected; EA = RST = Port 0 = VDD.
5. The Idle mode supply current is measured with all output pins disconnected; XTAL1 driven with tr = tf = 10 ns;
VIL = VSS; VIH = VDD; XTAL2 not connected; EA = Port 0 = VDD.
6. The Power-down current is measured with all output pins disconnected; XTAL1 not connected; EA = Port 0 = VDD;
RST = VSS.
7. The input threshold voltage of P1.6/SCL and P1.7/SDA meet the I2C-bus specification. Therefore, an input voltage
below 0.3VDD will be recognized as a logic 0 and an input voltage above 0.7VDD will be recognized as a logic 1.
1997 Mar 14
61
Philips Semiconductors
Product specification
Low voltage 8-bit microcontrollers with
UART and I2C-bus
f xtal
(MHz)
P83CL781; P83CL782
MLA588 - 1
14
f xtal
(MHz)
12
MGC441
14
12
10
10
8
8
6
6
4
4
2
2
0
0
0
2
4
0
6
VDD (V)
Fig.33 Frequency operating range - P83CL781.
4
VDD (V)
6
Fig.34 Frequency operating range - P83CL782.
MSA759 - 1
24
2
MSA758
8
handbook, halfpage
I DD
(mA)
I DD(idle)
(mA)
18
6
12 MHz
12 MHz
12
4
8 MHz
8 MHz
6
2
3.58 MHz
3.58 MHz
0
0
2
4
VDD (V)
0
6
0
2
4
VDD (V)
6
Tamb = 25 °C.
Oscillator option = Oscillator 3.
Tamb = 25 °C.
Oscillator option = Oscillator 3.
Fig.35 P83CL781: typical operating current as a
function of frequency and VDD.
Fig.36 P83CL781: typical Idle current as a function
of frequency and VDD.
1997 Mar 14
62
Philips Semiconductors
Product specification
Low voltage 8-bit microcontrollers with
UART and I2C-bus
P83CL781; P83CL782
MLB166
24
MLB165
8
I DD(idle)
I DD
(mA)
(mA)
18
6
12 MHz
12 MHz
12
4
8 MHz
8 MHz
6
2
3.58 MHz
3.58 MHz
0
0
0
2
4
VDD (V)
6
0
Fig.37 P83CL782: typical operating current as a
function of frequency and VDD.
MSA756
6
I DD(pd)
(µA)
4
2
0
4
VDD (V)
6
Tamb = 25 °C.
Fig.39 Typical Power-down current as a function of
VDD.
1997 Mar 14
VDD (V)
6
Fig.38 P83CL782: typical Idle current as a function
of frequency and VDD.
handbook, halfpage
2
4
Tamb = 25 °C.
Oscillator option = Oscillator 3.
Tamb = 25 °C.
Oscillator option = Oscillator 3.
0
2
63
Philips Semiconductors
Product specification
Low voltage 8-bit microcontrollers with
UART and I2C-bus
P83CL781; P83CL782
22 AC CHARACTERISTICS
The following AC characteristics apply to both the P83CL781 and P83CL782 unless otherwise stated.
22.1 Program memory
VDD = 5 V; VSS = 0 V; Tamb = −40 to +85 °C for the P83CL781 and −25 to +55 °C for the P83CL782; CL = 50 pF for
Port 0, ALE and PSEN; CL = 80 pF for all other outputs unless specified. See Fig.40.
SYMBOL
PARAMETER
fosc = 12 MHz
fosc = VARIABLE
MIN.
MIN.
MAX.
UNIT
MAX.
tLL
ALE pulse duration
127
−
2tCK − 40
−
ns
tAL
Address set-up time to ALE
43
−
tCK − 40
−
ns
tLA
Address hold time after ALE
48
−
tCK − 35
−
ns
tLIV
Time from ALE to valid instruction input
−
233
−
4tCK − 100
ns
tLC
Time from ALE to control pulse PSEN
58
−
tCK − 25
−
ns
tCC
Control pulse duration PSEN
215
−
3tCK − 35
−
ns
tCIV
Time from PSEN to valid instruction input
−
125
−
3tCK − 125
ns
tCI
Input instruction hold time after PSEN
0
−
0
−
ns
tCIF
Input instruction float delay after PSEN
−
63
−
tCK − 20
ns
tAC
Address valid after PSEN
75
−
tCK − 8
−
ns
tAIV
Address to valid instruction input
−
302
−
5tCK − 115
ns
tAFC
Address float delay after PSEN
12
−
0
−
ns
t CY
handbook, full pagewidth
t LIV
t LL
ALE
t LC
t CC
PSEN
t LA
t AL
PORT 0
t CIV
t CIF
instruction input
AD0 to AD7
t AFC
AD0 to AD7
instruction input
t CI
t AIV
PORT 2
address A8 to A15
address A8 to A15
MLA583
Fig.40 Read from Program Memory.
1997 Mar 14
64
Philips Semiconductors
Product specification
Low voltage 8-bit microcontrollers with
UART and I2C-bus
P83CL781; P83CL782
22.2 External Data Memory
VDD = 5 V; VSS = 0 V; Tamb = −40 to +85 °C for P83CL781 and −25 to +55 °C for the P83CL782; CL = 50 pF for Port 0,
ALE and PSEN; CL = 40 pF for all other outputs unless specified. See note 1 and Figs 41 and 42.
SYMBOL
PARAMETER
fosc = 12 MHz
fosc = VARIABLE
MIN.
MIN.
MAX.
UNIT
MAX.
tRR
RD pulse duration
400
−
6tCK − 100
−
ns
tWW
WR pulse duration
400
−
6tCK − 100
−
ns
tLA
Address hold time after ALE
48
−
tCK − 35
−
ns
tRD
RD to valid data input
−
150
−
5tCK − 165
ns
tDFR
Data float delay after RD
−
97
−
2tCK − 70
ns
tLD
Time from ALE to valid data input
−
517
−
8tCK − 150
ns
tAD
Address to valid data input
−
585
−
9tCK − 165
ns
tLW
Time from ALE to RD or WR
200
300
3tCK − 50
3tCK + 50
ns
tAW
Time from address to RD or WR
203
−
4
−
ns
tWHLH
Time from RD or WR HIGH to ALE HIGH
43
123
tCK − 40
tCK + 40
ns
tDWX
Data valid to WR transition
23
−
tCK − 60
−
ns
tDW
Data set-up time before WR
433
−
7tCK − 150
−
ns
tWD
Data hold time after WR
33
−
tCK − 50
−
ns
tAFR
Address float delay after RD
−
12
−
12
ns
Note
1. Interfacing the P83CL781 or the P83CL782 to devices with float times up to 75 ns is permitted. This limited bus
contention will not cause damage to Port 0 drivers.
1997 Mar 14
65
Philips Semiconductors
Product specification
Low voltage 8-bit microcontrollers with
UART and I2C-bus
P83CL781; P83CL782
t LD
handbook, full pagewidth
t WHLH
ALE
PSEN
t LW
t RR
RD
t AL
t LA
t DFR
t AW
PORT 0
t RD
AD0 to AD7
data input
t AFR
t AD
PORT 2
address A8 to A15 or Port 2 output
MLA584
Fig.41 Read from Data Memory.
t WHLH
handbook, full pagewidth
ALE
PSEN
t LW
t WW
WR
t AW
t AL
t LA
t DW
t WD
t DWX
PORT 0
PORT 2
AD0 to AD7
data output
address A8 to A15 or Port 2 output
MLA585 - 1
Fig.42 Write to Data Memory.
1997 Mar 14
66
Philips Semiconductors
Product specification
Low voltage 8-bit microcontrollers with
UART and I2C-bus
P83CL781; P83CL782
one machine cycle
one machine cycle
1/1 page = 296 mm (Datasheet)
S1
P1 P2
dotted lines
are valid when
RD or WR are
active
S2
P1 P2
S3
P1 P2
S4
P1 P2
S5
P1 P2
S6
P1 P2
S1
P1 P2
S2
P1 P2
S3
P1 P2
S4
P1 P2
S5
P1 P2
S6
P1 P2
27 mm
XTAL1
INPUT
ALE
only active
during a read
from external
data memory
only active
during a write
to external
data memory
PSEN
RD
WR
external
program
memory
fetch
BUS
(PORT 0)
inst.
in
BUS
(PORT 0)
PORT 2
PORT 0, 2, 3
OUTPUT
PORT 1
OUTPUT
inst.
in
address A8 - A15
PORT 2
read or
write of
external data
memory
address
A0 - A7
inst.
in
address
A0 - A7
inst.
in
address
A0 - A7
inst.
in
address A8 - A15
address
A0 - A7
address A8 - A15
address
A0 - A7
inst.
in
address A8 - A15
address
A0 - A7
address A8 - A15
address
A0 - A7
data output or data input
address A8 - A15 or Port 2 output
address A8 - A15
old data
new data
old data
new data
PORT 0, 2, 3
INPUT
sampling time of I/O port pins during input
SERIAL
PORT
CLOCK
MLA929
Fig.43 Instruction cycle timing.
1997 Mar 14
67
Philips Semiconductors
Product specification
Low voltage 8-bit microcontrollers with
UART and I2C-bus
handbook, halfpage
0.7 VDD
P83CL781; P83CL782
0.7 VDD
0.9 VDD
test points
0.4 VDD
0.3 VDD
0.3 VDD
MLA586
Fig.44 AC testing input waveform.
MSA763
handbook, 4 columns
500 µA
I IL(T)
II
I IL
100 µA
0
0.5 VDD
Fig.45 Input current.
1997 Mar 14
68
VDD
Philips Semiconductors
Product specification
Low voltage 8-bit microcontrollers with
UART and I2C-bus
P83CL781; P83CL782
23 PACKAGE OUTLINES
seating plane
DIP40: plastic dual in-line package; 40 leads (600 mil)
SOT129-1
ME
D
A2
L
A
A1
c
e
Z
w M
b1
(e 1)
b
MH
21
40
pin 1 index
E
1
20
0
5
10 mm
scale
DIMENSIONS (inch dimensions are derived from the original mm dimensions)
UNIT
A
max.
A1
min.
A2
max.
b
b1
c
mm
4.7
0.51
4.0
1.70
1.14
0.53
0.38
0.36
0.23
52.50
51.50
inches
0.19
0.020
0.16
0.067
0.045
0.021
0.015
0.014
0.009
2.067
2.028
D
(1)
e
e1
L
ME
MH
w
Z (1)
max.
14.1
13.7
2.54
15.24
3.60
3.05
15.80
15.24
17.42
15.90
0.254
2.25
0.56
0.54
0.10
0.60
0.14
0.12
0.62
0.60
0.69
0.63
0.01
0.089
E
(1)
Note
1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.
REFERENCES
OUTLINE
VERSION
IEC
JEDEC
SOT129-1
051G08
MO-015AJ
1997 Mar 14
EIAJ
EUROPEAN
PROJECTION
ISSUE DATE
92-11-17
95-01-14
69
Philips Semiconductors
Product specification
Low voltage 8-bit microcontrollers with
UART and I2C-bus
P83CL781; P83CL782
QFP44: plastic quad flat package; 44 leads (lead length 2.35 mm); body 14 x 14 x 2.2 mm
SOT205-1
c
y
X
33
A
23
34
22
ZE
e
Q
E HE
A
A2
(A 3)
A1
wM
θ
bp
Lp
pin 1 index
44
L
12
detail X
1
11
ZD
e
v M A
wM
bp
D
B
HD
v M B
0
5
10 mm
scale
DIMENSIONS (mm are the original dimensions)
UNIT
A
max.
A1
A2
A3
bp
c
D (1)
E (1)
e
HD
HE
L
Lp
Q
v
w
y
mm
2.60
0.25
0.05
2.3
2.1
0.25
0.50
0.35
0.25
0.14
14.1
13.9
14.1
13.9
1
19.2
18.2
19.2
18.2
2.35
2.0
1.2
1.2
0.9
0.3
0.15
0.1
Z D (1) Z E (1)
2.4
1.8
2.4
1.8
θ
Note
1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.
REFERENCES
OUTLINE
VERSION
IEC
SOT205-1
133E01A
1997 Mar 14
JEDEC
EIAJ
EUROPEAN
PROJECTION
ISSUE DATE
92-11-17
95-02-04
70
o
7
0o
Philips Semiconductors
Product specification
Low voltage 8-bit microcontrollers with
UART and I2C-bus
P83CL781; P83CL782
QFP44: plastic quad flat package; 44 leads (lead length 1.3 mm); body 10 x 10 x 1.75 mm
SOT307-2
c
y
X
A
33
23
34
22
ZE
e
Q
E HE
A A2
wM
(A 3)
A1
θ
bp
Lp
pin 1 index
L
12
44
1
detail X
11
wM
bp
e
ZD
v M A
D
B
HD
v M B
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
UNIT
A
max.
A1
A2
A3
bp
c
D (1)
E (1)
e
HD
HE
L
Lp
Q
v
w
y
mm
2.10
0.25
0.05
1.85
1.65
0.25
0.40
0.20
0.25
0.14
10.1
9.9
10.1
9.9
0.8
12.9
12.3
12.9
12.3
1.3
0.95
0.55
0.85
0.75
0.15
0.15
0.1
Z D (1) Z E (1)
1.2
0.8
1.2
0.8
θ
Note
1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.
OUTLINE
VERSION
REFERENCES
IEC
JEDEC
EIAJ
ISSUE DATE
92-11-17
95-02-04
SOT307-2
1997 Mar 14
EUROPEAN
PROJECTION
71
o
10
0o
Philips Semiconductors
Product specification
Low voltage 8-bit microcontrollers with
UART and I2C-bus
Reflow soldering requires solder paste (a suspension of
fine solder particles, flux and binding agent) to be applied
to the printed-circuit board by screen printing, stencilling or
pressure-syringe dispensing before package placement.
24 SOLDERING
24.1
Introduction
There is no soldering method that is ideal for all IC
packages. Wave soldering is often preferred when
through-hole and surface mounted components are mixed
on one printed-circuit board. However, wave soldering is
not always suitable for surface mounted ICs, or for
printed-circuits with high population densities. In these
situations reflow soldering is often used.
Several techniques exist for reflowing; for example,
thermal conduction by heated belt. Dwell times vary from
50 to 300 seconds depending on heating method. Typical
reflow temperatures range from 215 to 250 °C.
Preheating is necessary to dry the paste and evaporate
the binding agent. Preheat for 45 minutes at 45 °C.
This text gives a very brief insight to a complex technology.
A more in-depth account of soldering ICs can be found in
our “IC Package Databook” (order code 9398 652 90011).
24.2
24.2.1
P83CL781; P83CL782
24.3.2
WAVE SOLDERING
Wave soldering is not recommended for QFP packages.
This is because of the likelihood of solder bridging due to
closely-spaced leads and the possibility of incomplete
solder penetration in multi-lead devices.
DIP
SOLDERING BY DIPPING OR BY WAVE
The maximum permissible temperature of the solder is
260 °C; solder at this temperature must not be in contact
with the joint for more than 5 seconds. The total contact
time of successive solder waves must not exceed
5 seconds.
If wave soldering cannot be avoided, the following
conditions must be observed:
The device may be mounted up to the seating plane, but
the temperature of the plastic body must not exceed the
specified maximum storage temperature (Tstg max). If the
printed-circuit board has been pre-heated, forced cooling
may be necessary immediately after soldering to keep the
temperature within the permissible limit.
• The footprint must be at an angle of 45° to the board
direction and must incorporate solder thieves
downstream and at the side corners.
24.2.2
• A double-wave (a turbulent wave with high upward
pressure followed by a smooth laminar wave)
soldering technique should be used.
Even with these conditions, do not consider wave
soldering the following packages: QFP52 (SOT379-1),
QFP100 (SOT317-1), QFP100 (SOT317-2),
QFP100 (SOT382-1) or QFP160 (SOT322-1).
REPAIRING SOLDERED JOINTS
During placement and before soldering, the package must
be fixed with a droplet of adhesive. The adhesive can be
applied by screen printing, pin transfer or syringe
dispensing. The package can be soldered after the
adhesive is cured. Maximum permissible solder
temperature is 260 °C, and maximum duration of package
immersion in solder is 10 seconds, if cooled to less than
150 °C within 6 seconds. Typical dwell time is 4 seconds
at 250 °C.
Apply a low voltage soldering iron (less than 24 V) to the
lead(s) of the package, below the seating plane or not
more than 2 mm above it. If the temperature of the
soldering iron bit is less than 300 °C it may remain in
contact for up to 10 seconds. If the bit temperature is
between 300 and 400 °C, contact may be up to 5 seconds.
24.3
24.3.1
QFP
REFLOW SOLDERING
A mildly-activated flux will eliminate the need for removal
of corrosive residues in most applications.
Reflow soldering techniques are suitable for all QFP
packages.
24.3.3
The choice of heating method may be influenced by larger
plastic QFP packages (44 leads, or more). If infrared or
vapour phase heating is used and the large packages are
not absolutely dry (less than 0.1% moisture content by
weight), vaporization of the small amount of moisture in
them can cause cracking of the plastic body. For more
information, refer to the Drypack chapter in our “Quality
Reference Handbook” (order code 9398 510 63011).
1997 Mar 14
REPAIRING SOLDERED JOINTS
Fix the component by first soldering two diagonallyopposite end leads. Use only a low voltage soldering iron
(less than 24 V) applied to the flat part of the lead. Contact
time must be limited to 10 seconds at up to 300 °C. When
using a dedicated tool, all other leads can be soldered in
one operation within 2 to 5 seconds between
270 and 320 °C.
72
Philips Semiconductors
Product specification
Low voltage 8-bit microcontrollers with
UART and I2C-bus
P83CL781; P83CL782
25 DEFINITIONS
Data sheet status
Objective specification
This data sheet contains target or goal specifications for product development.
Preliminary specification
This data sheet contains preliminary data; supplementary data may be published later.
Product specification
This data sheet contains final product specifications.
Limiting values
Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or
more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation
of the device at these or at any other conditions above those given in the Characteristics sections of the specification
is not implied. Exposure to limiting values for extended periods may affect device reliability.
Application information
Where application information is given, it is advisory and does not form part of the specification.
26 LIFE SUPPORT APPLICATIONS
These products are not designed for use in life support appliances, devices, or systems where malfunction of these
products can reasonably be expected to result in personal injury. Philips customers using or selling these products for
use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such
improper use or sale.
27 PURCHASE OF PHILIPS I2C COMPONENTS
Purchase of Philips I2C components conveys a license under the Philips’ I2C patent to use the
components in the I2C system provided the system conforms to the I2C specification defined by
Philips. This specification can be ordered using the code 9398 393 40011.
1997 Mar 14
73
Philips Semiconductors
Product specification
Low voltage 8-bit microcontrollers with
UART and I2C-bus
NOTES
1997 Mar 14
74
P83CL781; P83CL782
Philips Semiconductors
Product specification
Low voltage 8-bit microcontrollers with
UART and I2C-bus
NOTES
1997 Mar 14
75
P83CL781; P83CL782
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Internet: http://www.semiconductors.philips.com
© Philips Electronics N.V. 1997
SCA53
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner.
The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed
without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license
under patent- or other industrial or intellectual property rights.
Printed in The Netherlands
457047/1200/02/pp76
Date of release: 1997 Mar 14
Document order number:
9397 750 01511