PHU97NQ03LT N-channel TrenchMOS logic level FET Rev. 01 — 25 February 2008 Product data sheet 1. Product profile 1.1 General description Logic level N-channel enhancement mode Field-Effect Transistor (FET) in a plastic package using TrenchMOS technology. 1.2 Features n Logic level threshold n Low on-state resistance n Fast switching n Lead-free packing 1.3 Applications n DC-to-DC converters n Voltage regulators n Switched-mode power supplies n Computer motherboards 1.4 Quick reference data n VDS ≤ 25 V n RDSon ≤ 6.6 mΩ n ID ≤ 75 A n QGD = 1.9 nC (typ) 2. Pinning information Table 1. Pinning Pin Description 1 gate (G) 2 drain (D) 3 source (S) mb mounting base; connected to drain (D) Simplified outline Symbol D mb G mbb076 1 2 3 SOT533 (IPAK) S PHU97NQ03LT NXP Semiconductors N-channel TrenchMOS logic level FET 3. Ordering information Table 2. Ordering information Type number PHU97NQ03LT Package Name Description Version IPAK plastic single-ended package (IPAK); 3 leads (In-line) SOT533 4. Limiting values Table 3. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol Parameter Conditions Min Max Unit VDS drain-source voltage 25 °C ≤ Tj ≤ 175 °C - 25 V VDGR drain-gate voltage (DC) 25 °C ≤ Tj ≤ 175 °C; RGS = 20 kΩ - 25 V VGS gate-source voltage - ±20 V ID drain current Tmb = 25 °C; VGS = 10 V; see Figure 2 and 3 - 75 A Tmb = 100 °C; VGS = 10 V; see Figure 2 - 69 A IDM peak drain current Tmb = 25 °C; pulsed; tp ≤ 10 µs; see Figure 3 - 300 A Ptot total power dissipation Tmb = 25 °C; see Figure 1 - 107 W Tstg storage temperature −55 +175 °C Tj junction temperature −55 +175 °C Source-drain diode IS source current Tmb = 25 °C - 75 A ISM peak source current Tmb = 25 °C; pulsed; tp ≤ 10 µs - 240 A unclamped inductive load; ID = 35 A; tp = 0.1 ms; VDS ≤ 25 V; RGS = 50 Ω; VGS = 10 V; starting at Tj = 25 °C - 60 mJ Avalanche ruggedness EDS(AL)S non-repetitive drain-source avalanche energy PHU97NQ03LT_1 Product data sheet © NXP B.V. 2008. All rights reserved. Rev. 01 — 25 February 2008 2 of 12 PHU97NQ03LT NXP Semiconductors N-channel TrenchMOS logic level FET 003aab844 120 003aab533 120 Pder (%) Ider (%) 80 80 40 40 0 0 50 100 150 0 200 0 Tmb (°C) 50 100 200 Tj (°C) P tot P der = ------------------------ × 100 % P tot ( 25°C ) ID I der = -------------------- × 100 % I D ( 25°C ) Fig 1. Normalized total power dissipation as a function of mounting base temperature Fig 2. Normalized continuous drain current as a function of mounting base temperature 003aab556 103 ID (A) 150 RDSon = VDS / ID tp = 10 µs 102 100 µs DC 10 1 ms 10 ms 1 10−1 1 102 10 VDS (V) Tmb = 25 °C; IDM is single pulse Fig 3. Safe operating area; continuous and peak drain currents as a function of drain-source voltage PHU97NQ03LT_1 Product data sheet © NXP B.V. 2008. All rights reserved. Rev. 01 — 25 February 2008 3 of 12 PHU97NQ03LT NXP Semiconductors N-channel TrenchMOS logic level FET 5. Thermal characteristics Table 4. Thermal characteristics Symbol Parameter thermal resistance from junction to mounting base see Figure 4 Rth(j-mb) [1] thermal resistance from junction to ambient Rth(j-a) [1] Conditions Min Typ Max Unit - - 1.4 K/W - 70 - K/W Vertical in still air; SOT533 package. 003aab535 10 Zth(j-mb) (K/W) 1 δ = 0.5 0.2 0.1 10-1 0.05 0.02 δ= P single pulse t tp T -2 10 10-5 tp T 10-4 10-3 10-2 10-1 1 tp (s) 10 Fig 4. Transient thermal impedance from junction to mounting base as a function of pulse duration PHU97NQ03LT_1 Product data sheet © NXP B.V. 2008. All rights reserved. Rev. 01 — 25 February 2008 4 of 12 PHU97NQ03LT NXP Semiconductors N-channel TrenchMOS logic level FET 6. Characteristics Table 5. Characteristics Tj = 25 °C unless otherwise specified. Symbol Parameter Conditions Min Typ Max Unit Tj = 25 °C 25 - - V Tj = −55 °C 22 - - V Static characteristics V(BR)DSS drain-source breakdown voltage VGS(th) IDSS gate-source threshold voltage drain leakage current ID = 250 µA; VGS = 0 V ID = 1 mA; VDS = VGS; see Figure 9 and 10 Tj = 25 °C 1.3 1.7 2.15 V Tj = 175 °C 0.7 - - V Tj = −55 °C - - 2.6 V VDS = 25 V; VGS = 0 V Tj = 25 °C - - 1 µA Tj = 175 °C - - 100 µA IGSS gate leakage current VGS = ±16 V; VDS = 0 V - - 100 nA RG gate resistance f = 1 MHz - 1.5 - Ω RDSon drain-source on-state resistance VGS = 10 V; ID = 25 A; see Figure 6 and 8 Tj = 25 °C - 5.6 6.6 mΩ Tj = 175 °C - 10.4 12.3 mΩ VGS = 4.5 V; ID = 25 A; see Figure 6 and 8 - 8.3 10.9 mΩ ID = 25 A; VDS = 12 V; VGS = 4.5 V; - 11.7 - nC ID = 0 A; VDS = 0 V; VGS = 4.5 V - 10.2 - nC see Figure 11 and 12 - 6.2 - nC Dynamic characteristics QG(tot) total gate charge QGS gate-source charge QGS1 pre-VGS(th) gate-source charge - 3.4 - nC QGS2 post-VGS(th) gate-source charge - 2.8 - nC QGD gate-drain charge - 1.9 - nC VGS(pl) gate-source plateau voltage - 3.1 - V - 1570 - pF - 380 - pF - 160 - pF 1800 - pF Ciss input capacitance Coss output capacitance VGS = 0 V; VDS = 12 V; f = 1 MHz; see Figure 14 Crss reverse transfer capacitance Ciss input capacitance VGS = 0 V; VDS = 0 V; f = 1 MHz - VDS = 12 V; RL = 0.5 Ω; VGS = 4.5 V; RG = 5.6 Ω - 18 - ns - 33 - ns td(on) turn-on delay time tr rise time td(off) turn-off delay time - 20 - ns tf fall time - 12 - ns Source-drain diode VSD source-drain voltage IS = 25 A; VGS = 0 V; see Figure 13 - 0.87 1.2 V trr reverse recovery time IS = 20 A; dIS/dt = −100 A/µs; VGS = 0 V - 38 - ns Qr recovered charge - 14 - nC PHU97NQ03LT_1 Product data sheet © NXP B.V. 2008. All rights reserved. Rev. 01 — 25 February 2008 5 of 12 PHU97NQ03LT NXP Semiconductors N-channel TrenchMOS logic level FET 003aab536 80 10 6 5 4.5 4.1 ID (A) 003aab537 25 RDSon (mΩ) 3.7 VGS (V) = 3.3 20 60 15 3.7 3.3 40 4.1 4.5 5 6 10 10 2.9 20 5 VGS (V) = 2.5 0 0 0 0.2 0.4 0.6 0.8 VDS (V) 0 1 Tj = 25 °C 20 40 60 ID (A) 80 Tj = 25 °C Fig 5. Output characteristics: drain current as a function of drain-source voltage; typical values Fig 6. Drain-source on-state resistance as a function of drain current; typical values 003aac094 80 003aab467 2 a ID (A) 1.6 60 1.2 40 0.8 20 Tj = 175 °C 25 °C 0.4 0 0 1 2 3 4 VGS (V) Tj = 25 °C and 175 °C; VDS > ID × RDSon 0 −60 60 120 180 Tj (°C) R DSon a = ----------------------------R DSon ( 25°C ) Fig 7. Transfer characteristics: drain current as a function of gate-source voltage; typical values Fig 8. Normalized drain-source on-state resistance factor as a function of junction temperature PHU97NQ03LT_1 Product data sheet 0 © NXP B.V. 2008. All rights reserved. Rev. 01 — 25 February 2008 6 of 12 PHU97NQ03LT NXP Semiconductors N-channel TrenchMOS logic level FET 003aab986 2.5 003aab938 10−1 ID (A) VGS(th) (V) 2.0 10−2 max 1.5 10−3 typ min min 1.0 typ max 10−4 10−5 0.5 0.0 −60 10−6 0 60 120 180 0 1 2 Tj (°C) 3 VGS (V) Tj = 25 °C; VDS = 5 V ID = 1 mA; VDS = VGS Fig 9. Gate-source threshold voltage as a function of junction temperature Fig 10. Sub-threshold drain current as a function of gate-source voltage 003aab539 10 VGS ID = 25 A Tj = 25 °C (V) 8 VDS ID 6 VDS = 19 V 12 V VGS(pl) 4 VGS(th) VGS 2 QGS1 QGS2 QGS 0 0 10 20 QG (nC) 30 QGD QG(tot) 003aaa508 ID = 25 A; VDS = 12 V and 19 V Fig 11. Gate-source voltage as a function of gate charge; typical values Fig 12. Gate charge waveform definitions PHU97NQ03LT_1 Product data sheet © NXP B.V. 2008. All rights reserved. Rev. 01 — 25 February 2008 7 of 12 PHU97NQ03LT NXP Semiconductors N-channel TrenchMOS logic level FET 003aab541 80 IS (A) 003aab542 104 C (pF) 60 Ciss 10 40 3 Tj = 25 °C 175 °C 20 Coss Crss 0 0 0.4 0.8 VSD (V) 1.2 Tj = 25 °C and 175 °C; VGS = 0 V 102 10-1 10 VDS (V) 102 VGS = 0 V; f = 1 MHz Fig 13. Source current as a function of source-drain voltage; typical values Fig 14. Input, output and reverse transfer capacitances as a function of drain-source voltage; typical values PHU97NQ03LT_1 Product data sheet 1 © NXP B.V. 2008. All rights reserved. Rev. 01 — 25 February 2008 8 of 12 PHU97NQ03LT NXP Semiconductors N-channel TrenchMOS logic level FET 7. Package outline Plastic single-ended package (IPAK); 3 leads (in-line) SOT533 E A E1 A1 D1 mounting base D2 L1 Q L 1 2 3 e1 w b c M e 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT A A1 b c D1 D2 E mm 2.38 2.22 0.93 0.46 0.89 0.71 0.56 0.46 1.10 0.96 6.22 5.98 6.73 6.47 E1 e e1 2.285 5.21 4.57 5.00 BSC (1) BSC (1) L L1 (2) max Q w 9.6 9.2 2.7 1.1 1.0 0.3 Notes 1. Basic spacing between centers. 2. Terminal dimensions are uncontrolled within zone L1. OUTLINE VERSION SOT533 REFERENCES IEC JEDEC JEITA EUROPEAN PROJECTION ISSUE DATE 05-02-11 06-02-14 TO-251 Fig 15. Package outline SOT533 (IPAK) PHU97NQ03LT_1 Product data sheet © NXP B.V. 2008. All rights reserved. Rev. 01 — 25 February 2008 9 of 12 PHU97NQ03LT NXP Semiconductors N-channel TrenchMOS logic level FET 8. Revision history Table 6. Revision history Document ID Release date Data sheet status Change notice Supersedes PHU97NQ03LT_1 20080225 Product data sheet - - PHU97NQ03LT_1 Product data sheet © NXP B.V. 2008. All rights reserved. Rev. 01 — 25 February 2008 10 of 12 PHU97NQ03LT NXP Semiconductors N-channel TrenchMOS logic level FET 9. Legal information 9.1 Data sheet status Document status[1][2] Product status[3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification. [1] Please consult the most recently issued document before initiating or completing a design. [2] The term ‘short data sheet’ is explained in section “Definitions”. [3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com. 9.2 Definitions Draft — The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet — A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. 9.3 Disclaimers General — Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use — NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk. Applications — Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Limiting values — Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) may cause permanent damage to the device. Limiting values are stress ratings only and operation of the device at these or any other conditions above those given in the Characteristics sections of this document is not implied. Exposure to limiting values for extended periods may affect device reliability. Terms and conditions of sale — NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, including those pertaining to warranty, intellectual property rights infringement and limitation of liability, unless explicitly otherwise agreed to in writing by NXP Semiconductors. In case of any inconsistency or conflict between information in this document and such terms and conditions, the latter will prevail. No offer to sell or license — Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. Quick reference data — The Quick reference data is an extract of the product data given in the Limiting values and Characteristics sections of this document, and as such is not complete, exhaustive or legally binding. 9.4 Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. TrenchMOS — is a trademark of NXP B.V. 10. Contact information For additional information, please visit: http://www.nxp.com For sales office addresses, send an email to: [email protected] PHU97NQ03LT_1 Product data sheet © NXP B.V. 2008. All rights reserved. Rev. 01 — 25 February 2008 11 of 12 PHU97NQ03LT NXP Semiconductors N-channel TrenchMOS logic level FET 11. Contents 1 1.1 1.2 1.3 1.4 2 3 4 5 6 7 8 9 9.1 9.2 9.3 9.4 10 11 Product profile . . . . . . . . . . . . . . . . . . . . . . . . . . 1 General description. . . . . . . . . . . . . . . . . . . . . . 1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Quick reference data. . . . . . . . . . . . . . . . . . . . . 1 Pinning information . . . . . . . . . . . . . . . . . . . . . . 1 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 2 Thermal characteristics. . . . . . . . . . . . . . . . . . . 4 Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Package outline . . . . . . . . . . . . . . . . . . . . . . . . . 9 Revision history . . . . . . . . . . . . . . . . . . . . . . . . 10 Legal information. . . . . . . . . . . . . . . . . . . . . . . 11 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 11 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Contact information. . . . . . . . . . . . . . . . . . . . . 11 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. © NXP B.V. 2008. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: [email protected] Date of release: 25 February 2008 Document identifier: PHU97NQ03LT_1